1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef RTE_ETH_AXGBE_H_ 7 #define RTE_ETH_AXGBE_H_ 8 9 #include <rte_mempool.h> 10 #include <rte_lcore.h> 11 #include "axgbe_common.h" 12 #include "rte_time.h" 13 14 #define IRQ 0xff 15 #define VLAN_HLEN 4 16 17 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 18 #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 19 #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN) 20 #define AXGBE_MAX_MAC_ADDRS 32 21 #define AXGBE_MAX_HASH_MAC_ADDRS 256 22 23 #define AXGBE_RX_BUF_ALIGN 64 24 25 #define AXGBE_MAX_DMA_CHANNELS 16 26 #define AXGBE_MAX_QUEUES 16 27 #define AXGBE_PRIORITY_QUEUES 8 28 #define AXGBE_DMA_STOP_TIMEOUT 1 29 30 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 31 #define AXGBE_DMA_OS_AXDOMAIN 0x2 32 #define AXGBE_DMA_OS_ARCACHE 0xb 33 #define AXGBE_DMA_OS_AWCACHE 0xf 34 35 /* DMA cache settings - System, no caches used */ 36 #define AXGBE_DMA_SYS_AXDOMAIN 0x3 37 #define AXGBE_DMA_SYS_ARCACHE 0x0 38 #define AXGBE_DMA_SYS_AWCACHE 0x0 39 40 /* DMA channel interrupt modes */ 41 #define AXGBE_IRQ_MODE_EDGE 0 42 #define AXGBE_IRQ_MODE_LEVEL 1 43 44 #define AXGBE_DMA_INTERRUPT_MASK 0x31c7 45 46 #define AXGMAC_MIN_PACKET 60 47 #define AXGMAC_STD_PACKET_MTU 1500 48 #define AXGMAC_MAX_STD_PACKET 1518 49 #define AXGMAC_JUMBO_PACKET_MTU 9000 50 #define AXGMAC_MAX_JUMBO_PACKET 9018 51 /* Inter-frame gap + preamble */ 52 #define AXGMAC_ETH_PREAMBLE (12 + 8) 53 54 #define AXGMAC_PFC_DATA_LEN 46 55 #define AXGMAC_PFC_DELAYS 14000 56 57 /* PCI BAR mapping */ 58 #define AXGBE_AXGMAC_BAR 0 59 #define AXGBE_XPCS_BAR 1 60 #define AXGBE_MAC_PROP_OFFSET 0x1d000 61 #define AXGBE_I2C_CTRL_OFFSET 0x1e000 62 63 /* PCI clock frequencies */ 64 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000 65 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000 66 67 /* Timestamp support - values based on 50MHz PTP clock 68 * 50MHz => 20 nsec 69 */ 70 #define AXGBE_TSTAMP_SSINC 20 71 #define AXGBE_TSTAMP_SNSINC 0 72 #define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 73 74 #define AXGMAC_FIFO_MIN_ALLOC 2048 75 #define AXGMAC_FIFO_UNIT 256 76 #define AXGMAC_FIFO_ALIGN(_x) \ 77 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 78 #define AXGMAC_FIFO_FC_OFF 2048 79 #define AXGMAC_FIFO_FC_MIN 4096 80 81 #define AXGBE_TC_MIN_QUANTUM 10 82 83 /* Flow control queue count */ 84 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8 85 86 /* Flow control threshold units */ 87 #define AXGMAC_FLOW_CONTROL_UNIT 512 88 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \ 89 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \ 90 ~(AXGMAC_FLOW_CONTROL_UNIT - 1)) 91 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \ 92 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) 93 #define AXGMAC_FLOW_CONTROL_MAX 33280 94 95 /* Maximum MAC address hash table size (256 bits = 8 dword) */ 96 #define AXGBE_MAC_HASH_TABLE_SIZE 8 97 98 /* Receive Side Scaling */ 99 #define AXGBE_RSS_OFFLOAD ( \ 100 ETH_RSS_IPV4 | \ 101 ETH_RSS_NONFRAG_IPV4_TCP | \ 102 ETH_RSS_NONFRAG_IPV4_UDP | \ 103 ETH_RSS_IPV6 | \ 104 ETH_RSS_NONFRAG_IPV6_TCP | \ 105 ETH_RSS_NONFRAG_IPV6_UDP) 106 107 #define AXGBE_RSS_HASH_KEY_SIZE 40 108 #define AXGBE_RSS_MAX_TABLE_SIZE 256 109 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0 110 #define AXGBE_RSS_HASH_KEY_TYPE 1 111 112 /* Auto-negotiation */ 113 #define AXGBE_AN_MS_TIMEOUT 500 114 #define AXGBE_LINK_TIMEOUT 5 115 116 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1) 117 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 118 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04 119 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08 120 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4) 121 122 /* ECC correctable error notification window (seconds) */ 123 #define AXGBE_ECC_LIMIT 60 124 125 /* MDIO port types */ 126 #define AXGMAC_MAX_C22_PORT 3 127 128 /* Helper macro for descriptor handling 129 * Always use AXGBE_GET_DESC_DATA to access the descriptor data 130 * since the index is free-running and needs to be and-ed 131 * with the descriptor count value of the ring to index to 132 * the proper descriptor data. 133 */ 134 #define AXGBE_GET_DESC_DATA(_ring, _idx) \ 135 ((_ring)->rdata + \ 136 ((_idx) & ((_ring)->rdesc_count - 1))) 137 138 struct axgbe_port; 139 140 enum axgbe_state { 141 AXGBE_DOWN, 142 AXGBE_LINK_INIT, 143 AXGBE_LINK_ERR, 144 AXGBE_STOPPED, 145 }; 146 147 enum axgbe_int { 148 AXGMAC_INT_DMA_CH_SR_TI, 149 AXGMAC_INT_DMA_CH_SR_TPS, 150 AXGMAC_INT_DMA_CH_SR_TBU, 151 AXGMAC_INT_DMA_CH_SR_RI, 152 AXGMAC_INT_DMA_CH_SR_RBU, 153 AXGMAC_INT_DMA_CH_SR_RPS, 154 AXGMAC_INT_DMA_CH_SR_TI_RI, 155 AXGMAC_INT_DMA_CH_SR_FBE, 156 AXGMAC_INT_DMA_ALL, 157 }; 158 159 enum axgbe_int_state { 160 AXGMAC_INT_STATE_SAVE, 161 AXGMAC_INT_STATE_RESTORE, 162 }; 163 164 enum axgbe_ecc_sec { 165 AXGBE_ECC_SEC_TX, 166 AXGBE_ECC_SEC_RX, 167 AXGBE_ECC_SEC_DESC, 168 }; 169 170 enum axgbe_speed { 171 AXGBE_SPEED_1000 = 0, 172 AXGBE_SPEED_2500, 173 AXGBE_SPEED_10000, 174 AXGBE_SPEEDS, 175 }; 176 177 enum axgbe_xpcs_access { 178 AXGBE_XPCS_ACCESS_V1 = 0, 179 AXGBE_XPCS_ACCESS_V2, 180 }; 181 182 enum axgbe_an_mode { 183 AXGBE_AN_MODE_CL73 = 0, 184 AXGBE_AN_MODE_CL73_REDRV, 185 AXGBE_AN_MODE_CL37, 186 AXGBE_AN_MODE_CL37_SGMII, 187 AXGBE_AN_MODE_NONE, 188 }; 189 190 enum axgbe_an { 191 AXGBE_AN_READY = 0, 192 AXGBE_AN_PAGE_RECEIVED, 193 AXGBE_AN_INCOMPAT_LINK, 194 AXGBE_AN_COMPLETE, 195 AXGBE_AN_NO_LINK, 196 AXGBE_AN_ERROR, 197 }; 198 199 enum axgbe_rx { 200 AXGBE_RX_BPA = 0, 201 AXGBE_RX_XNP, 202 AXGBE_RX_COMPLETE, 203 AXGBE_RX_ERROR, 204 }; 205 206 enum axgbe_mode { 207 AXGBE_MODE_KX_1000 = 0, 208 AXGBE_MODE_KX_2500, 209 AXGBE_MODE_KR, 210 AXGBE_MODE_X, 211 AXGBE_MODE_SGMII_100, 212 AXGBE_MODE_SGMII_1000, 213 AXGBE_MODE_SFI, 214 AXGBE_MODE_UNKNOWN, 215 }; 216 217 enum axgbe_speedset { 218 AXGBE_SPEEDSET_1000_10000 = 0, 219 AXGBE_SPEEDSET_2500_10000, 220 }; 221 222 enum axgbe_mdio_mode { 223 AXGBE_MDIO_MODE_NONE = 0, 224 AXGBE_MDIO_MODE_CL22, 225 AXGBE_MDIO_MODE_CL45, 226 }; 227 228 struct axgbe_phy { 229 uint32_t supported; 230 uint32_t advertising; 231 uint32_t lp_advertising; 232 233 int address; 234 235 int autoneg; 236 int speed; 237 int duplex; 238 239 int link; 240 241 int pause_autoneg; 242 int tx_pause; 243 int rx_pause; 244 }; 245 246 enum axgbe_i2c_cmd { 247 AXGBE_I2C_CMD_READ = 0, 248 AXGBE_I2C_CMD_WRITE, 249 }; 250 251 struct axgbe_i2c_op { 252 enum axgbe_i2c_cmd cmd; 253 254 unsigned int target; 255 256 uint8_t *buf; 257 unsigned int len; 258 }; 259 260 struct axgbe_i2c_op_state { 261 struct axgbe_i2c_op *op; 262 263 unsigned int tx_len; 264 unsigned char *tx_buf; 265 266 unsigned int rx_len; 267 unsigned char *rx_buf; 268 269 unsigned int tx_abort_source; 270 271 int ret; 272 }; 273 274 struct axgbe_i2c { 275 unsigned int started; 276 unsigned int max_speed_mode; 277 unsigned int rx_fifo_size; 278 unsigned int tx_fifo_size; 279 280 struct axgbe_i2c_op_state op_state; 281 }; 282 283 struct axgbe_hw_if { 284 void (*config_flow_control)(struct axgbe_port *); 285 int (*config_rx_mode)(struct axgbe_port *); 286 287 int (*init)(struct axgbe_port *); 288 289 int (*read_mmd_regs)(struct axgbe_port *, int, int); 290 void (*write_mmd_regs)(struct axgbe_port *, int, int, int); 291 int (*set_speed)(struct axgbe_port *, int); 292 293 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int, 294 enum axgbe_mdio_mode); 295 int (*read_ext_mii_regs)(struct axgbe_port *, int, int); 296 int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t); 297 298 /* For FLOW ctrl */ 299 int (*config_tx_flow_control)(struct axgbe_port *); 300 int (*config_rx_flow_control)(struct axgbe_port *); 301 302 int (*exit)(struct axgbe_port *); 303 }; 304 305 /* This structure represents implementation specific routines for an 306 * implementation of a PHY. All routines are required unless noted below. 307 * Optional routines: 308 * kr_training_pre, kr_training_post 309 */ 310 struct axgbe_phy_impl_if { 311 /* Perform Setup/teardown actions */ 312 int (*init)(struct axgbe_port *); 313 void (*exit)(struct axgbe_port *); 314 315 /* Perform start/stop specific actions */ 316 int (*reset)(struct axgbe_port *); 317 int (*start)(struct axgbe_port *); 318 void (*stop)(struct axgbe_port *); 319 320 /* Return the link status */ 321 int (*link_status)(struct axgbe_port *, int *); 322 323 /* Indicate if a particular speed is valid */ 324 int (*valid_speed)(struct axgbe_port *, int); 325 326 /* Check if the specified mode can/should be used */ 327 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode); 328 /* Switch the PHY into various modes */ 329 void (*set_mode)(struct axgbe_port *, enum axgbe_mode); 330 /* Retrieve mode needed for a specific speed */ 331 enum axgbe_mode (*get_mode)(struct axgbe_port *, int); 332 /* Retrieve new/next mode when trying to auto-negotiate */ 333 enum axgbe_mode (*switch_mode)(struct axgbe_port *); 334 /* Retrieve current mode */ 335 enum axgbe_mode (*cur_mode)(struct axgbe_port *); 336 337 /* Retrieve current auto-negotiation mode */ 338 enum axgbe_an_mode (*an_mode)(struct axgbe_port *); 339 340 /* Configure auto-negotiation settings */ 341 int (*an_config)(struct axgbe_port *); 342 343 /* Set/override auto-negotiation advertisement settings */ 344 unsigned int (*an_advertising)(struct axgbe_port *port); 345 346 /* Process results of auto-negotiation */ 347 enum axgbe_mode (*an_outcome)(struct axgbe_port *); 348 349 /* Pre/Post auto-negotiation support */ 350 void (*an_pre)(struct axgbe_port *port); 351 void (*an_post)(struct axgbe_port *port); 352 353 /* Pre/Post KR training enablement support */ 354 void (*kr_training_pre)(struct axgbe_port *); 355 void (*kr_training_post)(struct axgbe_port *); 356 }; 357 358 struct axgbe_phy_if { 359 /* For PHY setup/teardown */ 360 int (*phy_init)(struct axgbe_port *); 361 void (*phy_exit)(struct axgbe_port *); 362 363 /* For PHY support when setting device up/down */ 364 int (*phy_reset)(struct axgbe_port *); 365 int (*phy_start)(struct axgbe_port *); 366 void (*phy_stop)(struct axgbe_port *); 367 368 /* For PHY support while device is up */ 369 void (*phy_status)(struct axgbe_port *); 370 int (*phy_config_aneg)(struct axgbe_port *); 371 372 /* For PHY settings validation */ 373 int (*phy_valid_speed)(struct axgbe_port *, int); 374 /* For single interrupt support */ 375 void (*an_isr)(struct axgbe_port *); 376 /* PHY implementation specific services */ 377 struct axgbe_phy_impl_if phy_impl; 378 }; 379 380 struct axgbe_i2c_if { 381 /* For initial I2C setup */ 382 int (*i2c_init)(struct axgbe_port *); 383 384 /* For I2C support when setting device up/down */ 385 int (*i2c_start)(struct axgbe_port *); 386 void (*i2c_stop)(struct axgbe_port *); 387 388 /* For performing I2C operations */ 389 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *); 390 }; 391 392 /* This structure contains flags that indicate what hardware features 393 * or configurations are present in the device. 394 */ 395 struct axgbe_hw_features { 396 /* HW Version */ 397 unsigned int version; 398 399 /* HW Feature Register0 */ 400 unsigned int gmii; /* 1000 Mbps support */ 401 unsigned int vlhash; /* VLAN Hash Filter */ 402 unsigned int sma; /* SMA(MDIO) Interface */ 403 unsigned int rwk; /* PMT remote wake-up packet */ 404 unsigned int mgk; /* PMT magic packet */ 405 unsigned int mmc; /* RMON module */ 406 unsigned int aoe; /* ARP Offload */ 407 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 408 unsigned int eee; /* Energy Efficient Ethernet */ 409 unsigned int tx_coe; /* Tx Checksum Offload */ 410 unsigned int rx_coe; /* Rx Checksum Offload */ 411 unsigned int addn_mac; /* Additional MAC Addresses */ 412 unsigned int ts_src; /* Timestamp Source */ 413 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 414 415 /* HW Feature Register1 */ 416 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 417 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 418 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 419 unsigned int dma_width; /* DMA width */ 420 unsigned int dcb; /* DCB Feature */ 421 unsigned int sph; /* Split Header Feature */ 422 unsigned int tso; /* TCP Segmentation Offload */ 423 unsigned int dma_debug; /* DMA Debug Registers */ 424 unsigned int rss; /* Receive Side Scaling */ 425 unsigned int tc_cnt; /* Number of Traffic Classes */ 426 unsigned int hash_table_size; /* Hash Table Size */ 427 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 428 429 /* HW Feature Register2 */ 430 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 431 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 432 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 433 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 434 unsigned int pps_out_num; /* Number of PPS outputs */ 435 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 436 }; 437 438 struct axgbe_version_data { 439 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *); 440 enum axgbe_xpcs_access xpcs_access; 441 unsigned int mmc_64bit; 442 unsigned int tx_max_fifo_size; 443 unsigned int rx_max_fifo_size; 444 unsigned int tx_tstamp_workaround; 445 unsigned int ecc_support; 446 unsigned int i2c_support; 447 unsigned int an_cdr_workaround; 448 }; 449 450 struct axgbe_mmc_stats { 451 /* Tx Stats */ 452 uint64_t txoctetcount_gb; 453 uint64_t txframecount_gb; 454 uint64_t txbroadcastframes_g; 455 uint64_t txmulticastframes_g; 456 uint64_t tx64octets_gb; 457 uint64_t tx65to127octets_gb; 458 uint64_t tx128to255octets_gb; 459 uint64_t tx256to511octets_gb; 460 uint64_t tx512to1023octets_gb; 461 uint64_t tx1024tomaxoctets_gb; 462 uint64_t txunicastframes_gb; 463 uint64_t txmulticastframes_gb; 464 uint64_t txbroadcastframes_gb; 465 uint64_t txunderflowerror; 466 uint64_t txoctetcount_g; 467 uint64_t txframecount_g; 468 uint64_t txpauseframes; 469 uint64_t txvlanframes_g; 470 471 /* Rx Stats */ 472 uint64_t rxframecount_gb; 473 uint64_t rxoctetcount_gb; 474 uint64_t rxoctetcount_g; 475 uint64_t rxbroadcastframes_g; 476 uint64_t rxmulticastframes_g; 477 uint64_t rxcrcerror; 478 uint64_t rxrunterror; 479 uint64_t rxjabbererror; 480 uint64_t rxundersize_g; 481 uint64_t rxoversize_g; 482 uint64_t rx64octets_gb; 483 uint64_t rx65to127octets_gb; 484 uint64_t rx128to255octets_gb; 485 uint64_t rx256to511octets_gb; 486 uint64_t rx512to1023octets_gb; 487 uint64_t rx1024tomaxoctets_gb; 488 uint64_t rxunicastframes_g; 489 uint64_t rxlengtherror; 490 uint64_t rxoutofrangetype; 491 uint64_t rxpauseframes; 492 uint64_t rxfifooverflow; 493 uint64_t rxvlanframes_gb; 494 uint64_t rxwatchdogerror; 495 }; 496 497 /* Flow control parameters */ 498 struct xgbe_fc_info { 499 uint32_t high_water[AXGBE_PRIORITY_QUEUES]; 500 uint32_t low_water[AXGBE_PRIORITY_QUEUES]; 501 uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; 502 uint16_t send_xon; 503 enum rte_eth_fc_mode mode; 504 uint8_t autoneg; 505 }; 506 507 /* 508 * Structure to store private data for each port. 509 */ 510 struct axgbe_port { 511 /* Ethdev where port belongs*/ 512 struct rte_eth_dev *eth_dev; 513 /* Pci dev info */ 514 const struct rte_pci_device *pci_dev; 515 /* Version related data */ 516 struct axgbe_version_data *vdata; 517 518 /* AXGMAC/XPCS related mmio registers */ 519 void *xgmac_regs; /* AXGMAC CSRs */ 520 void *xpcs_regs; /* XPCS MMD registers */ 521 void *xprop_regs; /* AXGBE property registers */ 522 void *xi2c_regs; /* AXGBE I2C CSRs */ 523 524 bool cdr_track_early; 525 /* XPCS indirect addressing lock */ 526 unsigned int xpcs_window_def_reg; 527 unsigned int xpcs_window_sel_reg; 528 unsigned int xpcs_window; 529 unsigned int xpcs_window_size; 530 unsigned int xpcs_window_mask; 531 532 /* Flags representing axgbe_state */ 533 uint32_t dev_state; 534 535 struct axgbe_hw_if hw_if; 536 struct axgbe_phy_if phy_if; 537 struct axgbe_i2c_if i2c_if; 538 539 /* AXI DMA settings */ 540 unsigned int coherent; 541 unsigned int axdomain; 542 unsigned int arcache; 543 unsigned int awcache; 544 545 unsigned int tx_max_channel_count; 546 unsigned int rx_max_channel_count; 547 unsigned int channel_count; 548 unsigned int tx_ring_count; 549 unsigned int tx_desc_count; 550 unsigned int rx_ring_count; 551 unsigned int rx_desc_count; 552 553 unsigned int tx_max_q_count; 554 unsigned int rx_max_q_count; 555 unsigned int tx_q_count; 556 unsigned int rx_q_count; 557 558 /* Tx/Rx common settings */ 559 unsigned int pblx8; 560 561 /* Tx settings */ 562 unsigned int tx_sf_mode; 563 unsigned int tx_threshold; 564 unsigned int tx_pbl; 565 unsigned int tx_osp_mode; 566 unsigned int tx_max_fifo_size; 567 568 /* Rx settings */ 569 unsigned int rx_sf_mode; 570 unsigned int rx_threshold; 571 unsigned int rx_pbl; 572 unsigned int rx_max_fifo_size; 573 unsigned int rx_buf_size; 574 575 /* Device clocks */ 576 unsigned long sysclk_rate; 577 unsigned long ptpclk_rate; 578 579 /* Keeps track of power mode */ 580 unsigned int power_down; 581 582 /* Current PHY settings */ 583 int phy_link; 584 int phy_speed; 585 586 pthread_mutex_t xpcs_mutex; 587 pthread_mutex_t i2c_mutex; 588 pthread_mutex_t an_mutex; 589 pthread_mutex_t phy_mutex; 590 591 /* Flow control settings */ 592 unsigned int pause_autoneg; 593 unsigned int tx_pause; 594 unsigned int rx_pause; 595 unsigned int rx_rfa[AXGBE_MAX_QUEUES]; 596 unsigned int rx_rfd[AXGBE_MAX_QUEUES]; 597 unsigned int fifo; 598 unsigned int pfc_map[AXGBE_MAX_QUEUES]; 599 600 /* Receive Side Scaling settings */ 601 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; 602 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; 603 uint32_t rss_options; 604 int rss_enable; 605 uint64_t rss_hf; 606 607 /* Hardware features of the device */ 608 struct axgbe_hw_features hw_feat; 609 610 struct rte_ether_addr mac_addr; 611 612 /* Software Tx/Rx structure pointers*/ 613 void **rx_queues; 614 void **tx_queues; 615 616 /* MDIO/PHY related settings */ 617 unsigned int phy_started; 618 void *phy_data; 619 struct axgbe_phy phy; 620 int mdio_mmd; 621 unsigned long link_check; 622 volatile int mdio_completion; 623 624 unsigned int kr_redrv; 625 626 /* Auto-negotiation atate machine support */ 627 unsigned int an_int; 628 unsigned int an_status; 629 enum axgbe_an an_result; 630 enum axgbe_an an_state; 631 enum axgbe_rx kr_state; 632 enum axgbe_rx kx_state; 633 unsigned int an_supported; 634 unsigned int parallel_detect; 635 unsigned int fec_ability; 636 unsigned long an_start; 637 enum axgbe_an_mode an_mode; 638 639 /* I2C support */ 640 struct axgbe_i2c i2c; 641 volatile int i2c_complete; 642 643 /* CRC stripping by H/w for Rx packet*/ 644 int crc_strip_enable; 645 /* csum enable to hardware */ 646 uint32_t rx_csum_enable; 647 648 struct axgbe_mmc_stats mmc_stats; 649 struct xgbe_fc_info fc; 650 651 /* Hash filtering */ 652 unsigned int hash_table_shift; 653 unsigned int hash_table_count; 654 unsigned int uc_hash_mac_addr; 655 unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; 656 657 /* For IEEE1588 PTP */ 658 struct rte_timecounter systime_tc; 659 struct rte_timecounter tx_tstamp; 660 unsigned int tstamp_addend; 661 662 }; 663 664 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); 665 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if); 666 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); 667 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); 668 void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, 669 uint32_t index); 670 void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); 671 int axgbe_write_rss_lookup_table(struct axgbe_port *pdata); 672 int axgbe_write_rss_hash_key(struct axgbe_port *pdata); 673 674 #endif /* RTE_ETH_AXGBE_H_ */ 675