1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef RTE_ETH_AXGBE_H_ 7 #define RTE_ETH_AXGBE_H_ 8 9 #include <rte_mempool.h> 10 #include <rte_lcore.h> 11 #include "axgbe_common.h" 12 #include "rte_time.h" 13 14 #define IRQ 0xff 15 16 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 17 #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 18 #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + RTE_VLAN_HLEN) 19 #define AXGBE_MAX_MAC_ADDRS 32 20 #define AXGBE_MAX_HASH_MAC_ADDRS 256 21 22 #define AXGBE_RX_BUF_ALIGN 64 23 24 #define AXGBE_MAX_DMA_CHANNELS 16 25 #define AXGBE_MAX_QUEUES 16 26 #define AXGBE_PRIORITY_QUEUES 8 27 #define AXGBE_DMA_STOP_TIMEOUT 1 28 29 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 30 #define AXGBE_DMA_OS_AXDOMAIN 0x2 31 #define AXGBE_DMA_OS_ARCACHE 0xb 32 #define AXGBE_DMA_OS_AWCACHE 0xf 33 34 /* DMA cache settings - System, no caches used */ 35 #define AXGBE_DMA_SYS_AXDOMAIN 0x3 36 #define AXGBE_DMA_SYS_ARCACHE 0x0 37 #define AXGBE_DMA_SYS_AWCACHE 0x0 38 39 /* DMA channel interrupt modes */ 40 #define AXGBE_IRQ_MODE_EDGE 0 41 #define AXGBE_IRQ_MODE_LEVEL 1 42 43 #define AXGBE_DMA_INTERRUPT_MASK 0x31c7 44 45 #define AXGMAC_MIN_PACKET 60 46 #define AXGMAC_STD_PACKET_MTU 1500 47 #define AXGMAC_MAX_STD_PACKET 1518 48 #define AXGMAC_JUMBO_PACKET_MTU 9000 49 #define AXGMAC_MAX_JUMBO_PACKET 9018 50 /* Inter-frame gap + preamble */ 51 #define AXGMAC_ETH_PREAMBLE (12 + 8) 52 53 #define AXGMAC_PFC_DATA_LEN 46 54 #define AXGMAC_PFC_DELAYS 14000 55 56 /* PCI BAR mapping */ 57 #define AXGBE_AXGMAC_BAR 0 58 #define AXGBE_XPCS_BAR 1 59 #define AXGBE_MAC_PROP_OFFSET 0x1d000 60 #define AXGBE_I2C_CTRL_OFFSET 0x1e000 61 62 /* PCI clock frequencies */ 63 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000 64 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000 65 66 /* Timestamp support - values based on 50MHz PTP clock 67 * 50MHz => 20 nsec 68 */ 69 #define AXGBE_TSTAMP_SSINC 20 70 #define AXGBE_TSTAMP_SNSINC 0 71 #define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 72 73 #define AXGMAC_FIFO_MIN_ALLOC 2048 74 #define AXGMAC_FIFO_UNIT 256 75 #define AXGMAC_FIFO_ALIGN(_x) \ 76 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 77 #define AXGMAC_FIFO_FC_OFF 2048 78 #define AXGMAC_FIFO_FC_MIN 4096 79 80 #define AXGBE_TC_MIN_QUANTUM 10 81 82 /* Flow control queue count */ 83 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8 84 85 /* Flow control threshold units */ 86 #define AXGMAC_FLOW_CONTROL_UNIT 512 87 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \ 88 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \ 89 ~(AXGMAC_FLOW_CONTROL_UNIT - 1)) 90 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \ 91 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) 92 #define AXGMAC_FLOW_CONTROL_MAX 33280 93 94 /* Maximum MAC address hash table size (256 bits = 8 dword) */ 95 #define AXGBE_MAC_HASH_TABLE_SIZE 8 96 97 /* Receive Side Scaling */ 98 #define AXGBE_RSS_OFFLOAD ( \ 99 RTE_ETH_RSS_IPV4 | \ 100 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 101 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 102 RTE_ETH_RSS_IPV6 | \ 103 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 104 RTE_ETH_RSS_NONFRAG_IPV6_UDP) 105 106 #define AXGBE_RSS_HASH_KEY_SIZE 40 107 #define AXGBE_RSS_MAX_TABLE_SIZE 256 108 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0 109 #define AXGBE_RSS_HASH_KEY_TYPE 1 110 111 /* Auto-negotiation */ 112 #define AXGBE_AN_MS_TIMEOUT 500 113 #define AXGBE_LINK_TIMEOUT 5 114 #define AXGBE_KR_TRAINING_WAIT_ITER 50 115 116 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1) 117 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 118 #define AXGBE_SGMII_AN_LINK_SPEED_10 0x00 119 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04 120 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08 121 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4) 122 123 /* ECC correctable error notification window (seconds) */ 124 #define AXGBE_ECC_LIMIT 60 125 126 /* MDIO port types */ 127 #define AXGMAC_MAX_C22_PORT 3 128 129 /* The max frame size with default MTU */ 130 #define AXGBE_ETH_MAX_LEN ( \ 131 RTE_ETHER_MTU + \ 132 RTE_ETHER_HDR_LEN + \ 133 RTE_ETHER_CRC_LEN) 134 135 /* Helper macro for descriptor handling 136 * Always use AXGBE_GET_DESC_DATA to access the descriptor data 137 * since the index is free-running and needs to be and-ed 138 * with the descriptor count value of the ring to index to 139 * the proper descriptor data. 140 */ 141 #define AXGBE_GET_DESC_DATA(_ring, _idx) \ 142 ((_ring)->rdata + \ 143 ((_idx) & ((_ring)->rdesc_count - 1))) 144 145 struct axgbe_port; 146 147 enum axgbe_state { 148 AXGBE_DOWN, 149 AXGBE_LINK_INIT, 150 AXGBE_LINK_ERR, 151 AXGBE_STOPPED, 152 }; 153 154 enum axgbe_int { 155 AXGMAC_INT_DMA_CH_SR_TI, 156 AXGMAC_INT_DMA_CH_SR_TPS, 157 AXGMAC_INT_DMA_CH_SR_TBU, 158 AXGMAC_INT_DMA_CH_SR_RI, 159 AXGMAC_INT_DMA_CH_SR_RBU, 160 AXGMAC_INT_DMA_CH_SR_RPS, 161 AXGMAC_INT_DMA_CH_SR_TI_RI, 162 AXGMAC_INT_DMA_CH_SR_FBE, 163 AXGMAC_INT_DMA_ALL, 164 }; 165 166 enum axgbe_int_state { 167 AXGMAC_INT_STATE_SAVE, 168 AXGMAC_INT_STATE_RESTORE, 169 }; 170 171 enum axgbe_ecc_sec { 172 AXGBE_ECC_SEC_TX, 173 AXGBE_ECC_SEC_RX, 174 AXGBE_ECC_SEC_DESC, 175 }; 176 177 enum axgbe_speed { 178 AXGBE_SPEED_1000 = 0, 179 AXGBE_SPEED_2500, 180 AXGBE_SPEED_10000, 181 AXGBE_SPEEDS, 182 }; 183 184 enum axgbe_xpcs_access { 185 AXGBE_XPCS_ACCESS_V1 = 0, 186 AXGBE_XPCS_ACCESS_V2, 187 }; 188 189 enum axgbe_an_mode { 190 AXGBE_AN_MODE_CL73 = 0, 191 AXGBE_AN_MODE_CL73_REDRV, 192 AXGBE_AN_MODE_CL37, 193 AXGBE_AN_MODE_CL37_SGMII, 194 AXGBE_AN_MODE_NONE, 195 }; 196 197 enum axgbe_an { 198 AXGBE_AN_READY = 0, 199 AXGBE_AN_PAGE_RECEIVED, 200 AXGBE_AN_INCOMPAT_LINK, 201 AXGBE_AN_COMPLETE, 202 AXGBE_AN_NO_LINK, 203 AXGBE_AN_ERROR, 204 }; 205 206 enum axgbe_rx { 207 AXGBE_RX_BPA = 0, 208 AXGBE_RX_XNP, 209 AXGBE_RX_COMPLETE, 210 AXGBE_RX_ERROR, 211 }; 212 213 enum axgbe_mode { 214 AXGBE_MODE_KX_1000 = 0, 215 AXGBE_MODE_KX_2500, 216 AXGBE_MODE_KR, 217 AXGBE_MODE_X, 218 AXGBE_MODE_SGMII_10, 219 AXGBE_MODE_SGMII_100, 220 AXGBE_MODE_SGMII_1000, 221 AXGBE_MODE_SFI, 222 AXGBE_MODE_UNKNOWN, 223 }; 224 225 enum axgbe_speedset { 226 AXGBE_SPEEDSET_1000_10000 = 0, 227 AXGBE_SPEEDSET_2500_10000, 228 }; 229 230 enum axgbe_mdio_mode { 231 AXGBE_MDIO_MODE_NONE = 0, 232 AXGBE_MDIO_MODE_CL22, 233 AXGBE_MDIO_MODE_CL45, 234 }; 235 236 enum axgbe_mb_cmd { 237 AXGBE_MB_CMD_POWER_OFF = 0, 238 AXGBE_MB_CMD_SET_1G, 239 AXGBE_MB_CMD_SET_2_5G, 240 AXGBE_MB_CMD_SET_10G_SFI, 241 AXGBE_MB_CMD_SET_10G_KR, 242 AXGBE_MB_CMD_RRC 243 }; 244 245 enum axgbe_mb_subcmd { 246 AXGBE_MB_SUBCMD_NONE = 0, 247 AXGBE_MB_SUBCMD_RX_ADAP, 248 249 /* 10GbE SFP subcommands */ 250 AXGBE_MB_SUBCMD_ACTIVE = 0, 251 AXGBE_MB_SUBCMD_PASSIVE_1M, 252 AXGBE_MB_SUBCMD_PASSIVE_3M, 253 AXGBE_MB_SUBCMD_PASSIVE_OTHER, 254 255 /* 1GbE Mode subcommands */ 256 AXGBE_MB_SUBCMD_10MBITS = 0, 257 AXGBE_MB_SUBCMD_100MBITS, 258 AXGBE_MB_SUBCMD_1G_SGMII, 259 AXGBE_MB_SUBCMD_1G_KX 260 }; 261 262 struct axgbe_phy { 263 uint32_t supported; 264 uint32_t advertising; 265 uint32_t lp_advertising; 266 267 int address; 268 269 int autoneg; 270 int speed; 271 int duplex; 272 273 int link; 274 275 int pause_autoneg; 276 int tx_pause; 277 int rx_pause; 278 }; 279 280 enum axgbe_i2c_cmd { 281 AXGBE_I2C_CMD_READ = 0, 282 AXGBE_I2C_CMD_WRITE, 283 }; 284 285 struct axgbe_i2c_op { 286 enum axgbe_i2c_cmd cmd; 287 288 unsigned int target; 289 290 uint8_t *buf; 291 unsigned int len; 292 }; 293 294 struct axgbe_i2c_op_state { 295 struct axgbe_i2c_op *op; 296 297 unsigned int tx_len; 298 unsigned char *tx_buf; 299 300 unsigned int rx_len; 301 unsigned char *rx_buf; 302 303 unsigned int tx_abort_source; 304 305 int ret; 306 }; 307 308 struct axgbe_i2c { 309 unsigned int started; 310 unsigned int max_speed_mode; 311 unsigned int rx_fifo_size; 312 unsigned int tx_fifo_size; 313 314 struct axgbe_i2c_op_state op_state; 315 }; 316 317 struct axgbe_hw_if { 318 void (*config_flow_control)(struct axgbe_port *); 319 int (*config_rx_mode)(struct axgbe_port *); 320 321 int (*init)(struct axgbe_port *); 322 323 int (*read_mmd_regs)(struct axgbe_port *, int, int); 324 void (*write_mmd_regs)(struct axgbe_port *, int, int, int); 325 int (*set_speed)(struct axgbe_port *, int); 326 327 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int, 328 enum axgbe_mdio_mode); 329 int (*read_ext_mii_regs_c22)(struct axgbe_port *pdata, int addr, int reg); 330 int (*write_ext_mii_regs_c22)(struct axgbe_port *pdata, int addr, int reg, uint16_t val); 331 int (*read_ext_mii_regs_c45)(struct axgbe_port *pdata, int addr, int devad, int reg); 332 int (*write_ext_mii_regs_c45)(struct axgbe_port *pdata, int addr, int devad, 333 int reg, uint16_t val); 334 335 /* For FLOW ctrl */ 336 int (*config_tx_flow_control)(struct axgbe_port *); 337 int (*config_rx_flow_control)(struct axgbe_port *); 338 339 /* vlan */ 340 int (*enable_rx_vlan_stripping)(struct axgbe_port *); 341 int (*disable_rx_vlan_stripping)(struct axgbe_port *); 342 int (*enable_rx_vlan_filtering)(struct axgbe_port *); 343 int (*disable_rx_vlan_filtering)(struct axgbe_port *); 344 int (*update_vlan_hash_table)(struct axgbe_port *); 345 346 int (*exit)(struct axgbe_port *); 347 }; 348 349 /* This structure represents implementation specific routines for an 350 * implementation of a PHY. All routines are required unless noted below. 351 * Optional routines: 352 * kr_training_pre, kr_training_post 353 */ 354 struct axgbe_phy_impl_if { 355 /* Perform Setup/teardown actions */ 356 int (*init)(struct axgbe_port *); 357 void (*exit)(struct axgbe_port *); 358 359 /* Perform start/stop specific actions */ 360 int (*reset)(struct axgbe_port *); 361 int (*start)(struct axgbe_port *); 362 void (*stop)(struct axgbe_port *); 363 364 /* Return the link status */ 365 int (*link_status)(struct axgbe_port *, int *); 366 367 /* Indicate if a particular speed is valid */ 368 int (*valid_speed)(struct axgbe_port *, int); 369 370 /* Check if the specified mode can/should be used */ 371 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode); 372 /* Switch the PHY into various modes */ 373 void (*set_mode)(struct axgbe_port *, enum axgbe_mode); 374 /* Retrieve mode needed for a specific speed */ 375 enum axgbe_mode (*get_mode)(struct axgbe_port *, int); 376 /* Retrieve new/next mode when trying to auto-negotiate */ 377 enum axgbe_mode (*switch_mode)(struct axgbe_port *); 378 /* Retrieve current mode */ 379 enum axgbe_mode (*cur_mode)(struct axgbe_port *); 380 381 /* Retrieve current auto-negotiation mode */ 382 enum axgbe_an_mode (*an_mode)(struct axgbe_port *); 383 384 /* Configure auto-negotiation settings */ 385 int (*an_config)(struct axgbe_port *); 386 387 /* Set/override auto-negotiation advertisement settings */ 388 unsigned int (*an_advertising)(struct axgbe_port *port); 389 390 /* Process results of auto-negotiation */ 391 enum axgbe_mode (*an_outcome)(struct axgbe_port *); 392 393 /* Pre/Post auto-negotiation support */ 394 void (*an_pre)(struct axgbe_port *port); 395 void (*an_post)(struct axgbe_port *port); 396 397 /* Pre/Post KR training enablement support */ 398 void (*kr_training_pre)(struct axgbe_port *); 399 void (*kr_training_post)(struct axgbe_port *); 400 }; 401 402 struct axgbe_phy_if { 403 /* For PHY setup/teardown */ 404 int (*phy_init)(struct axgbe_port *); 405 void (*phy_exit)(struct axgbe_port *); 406 407 /* For PHY support when setting device up/down */ 408 int (*phy_reset)(struct axgbe_port *); 409 int (*phy_start)(struct axgbe_port *); 410 void (*phy_stop)(struct axgbe_port *); 411 412 /* For PHY support while device is up */ 413 void (*phy_status)(struct axgbe_port *); 414 int (*phy_config_aneg)(struct axgbe_port *); 415 416 /* For PHY settings validation */ 417 int (*phy_valid_speed)(struct axgbe_port *, int); 418 /* For single interrupt support */ 419 void (*an_isr)(struct axgbe_port *); 420 /* PHY implementation specific services */ 421 struct axgbe_phy_impl_if phy_impl; 422 }; 423 424 struct axgbe_i2c_if { 425 /* For initial I2C setup */ 426 int (*i2c_init)(struct axgbe_port *); 427 428 /* For I2C support when setting device up/down */ 429 int (*i2c_start)(struct axgbe_port *); 430 void (*i2c_stop)(struct axgbe_port *); 431 432 /* For performing I2C operations */ 433 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *); 434 }; 435 436 /* This structure contains flags that indicate what hardware features 437 * or configurations are present in the device. 438 */ 439 struct axgbe_hw_features { 440 /* HW Version */ 441 unsigned int version; 442 443 /* HW Feature Register0 */ 444 unsigned int gmii; /* 1000 Mbps support */ 445 unsigned int vlhash; /* VLAN Hash Filter */ 446 unsigned int sma; /* SMA(MDIO) Interface */ 447 unsigned int rwk; /* PMT remote wake-up packet */ 448 unsigned int mgk; /* PMT magic packet */ 449 unsigned int mmc; /* RMON module */ 450 unsigned int aoe; /* ARP Offload */ 451 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 452 unsigned int eee; /* Energy Efficient Ethernet */ 453 unsigned int tx_coe; /* Tx Checksum Offload */ 454 unsigned int rx_coe; /* Rx Checksum Offload */ 455 unsigned int addn_mac; /* Additional MAC Addresses */ 456 unsigned int ts_src; /* Timestamp Source */ 457 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 458 459 /* HW Feature Register1 */ 460 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 461 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 462 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 463 unsigned int dma_width; /* DMA width */ 464 unsigned int dcb; /* DCB Feature */ 465 unsigned int sph; /* Split Header Feature */ 466 unsigned int tso; /* TCP Segmentation Offload */ 467 unsigned int dma_debug; /* DMA Debug Registers */ 468 unsigned int rss; /* Receive Side Scaling */ 469 unsigned int tc_cnt; /* Number of Traffic Classes */ 470 unsigned int hash_table_size; /* Hash Table Size */ 471 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 472 473 /* HW Feature Register2 */ 474 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 475 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 476 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 477 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 478 unsigned int pps_out_num; /* Number of PPS outputs */ 479 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 480 481 /* HW Feature Register3 */ 482 unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */ 483 /* insertion on Tx Enable */ 484 unsigned int no_of_vlan_extn; /* Number of Extended VLAN Tag */ 485 /* Filters Enabled */ 486 }; 487 488 struct axgbe_version_data { 489 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *); 490 enum axgbe_xpcs_access xpcs_access; 491 unsigned int mmc_64bit; 492 unsigned int tx_max_fifo_size; 493 unsigned int rx_max_fifo_size; 494 unsigned int tx_tstamp_workaround; 495 unsigned int ecc_support; 496 unsigned int i2c_support; 497 unsigned int an_cdr_workaround; 498 unsigned int enable_rrc; 499 }; 500 501 struct axgbe_mmc_stats { 502 /* Tx Stats */ 503 uint64_t txoctetcount_gb; 504 uint64_t txframecount_gb; 505 uint64_t txbroadcastframes_g; 506 uint64_t txmulticastframes_g; 507 uint64_t tx64octets_gb; 508 uint64_t tx65to127octets_gb; 509 uint64_t tx128to255octets_gb; 510 uint64_t tx256to511octets_gb; 511 uint64_t tx512to1023octets_gb; 512 uint64_t tx1024tomaxoctets_gb; 513 uint64_t txunicastframes_gb; 514 uint64_t txmulticastframes_gb; 515 uint64_t txbroadcastframes_gb; 516 uint64_t txunderflowerror; 517 uint64_t txoctetcount_g; 518 uint64_t txframecount_g; 519 uint64_t txpauseframes; 520 uint64_t txvlanframes_g; 521 522 /* Rx Stats */ 523 uint64_t rxframecount_gb; 524 uint64_t rxoctetcount_gb; 525 uint64_t rxoctetcount_g; 526 uint64_t rxbroadcastframes_g; 527 uint64_t rxmulticastframes_g; 528 uint64_t rxcrcerror; 529 uint64_t rxrunterror; 530 uint64_t rxjabbererror; 531 uint64_t rxundersize_g; 532 uint64_t rxoversize_g; 533 uint64_t rx64octets_gb; 534 uint64_t rx65to127octets_gb; 535 uint64_t rx128to255octets_gb; 536 uint64_t rx256to511octets_gb; 537 uint64_t rx512to1023octets_gb; 538 uint64_t rx1024tomaxoctets_gb; 539 uint64_t rxunicastframes_g; 540 uint64_t rxlengtherror; 541 uint64_t rxoutofrangetype; 542 uint64_t rxpauseframes; 543 uint64_t rxfifooverflow; 544 uint64_t rxvlanframes_gb; 545 uint64_t rxwatchdogerror; 546 }; 547 548 /* Flow control parameters */ 549 struct xgbe_fc_info { 550 uint32_t high_water[AXGBE_PRIORITY_QUEUES]; 551 uint32_t low_water[AXGBE_PRIORITY_QUEUES]; 552 uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; 553 uint16_t send_xon; 554 enum rte_eth_fc_mode mode; 555 uint8_t autoneg; 556 }; 557 558 /* 559 * Structure to store private data for each port. 560 */ 561 struct axgbe_port { 562 /* Ethdev where port belongs*/ 563 struct rte_eth_dev *eth_dev; 564 /* Pci dev info */ 565 const struct rte_pci_device *pci_dev; 566 /* Version related data */ 567 struct axgbe_version_data *vdata; 568 569 /* AXGMAC/XPCS related mmio registers */ 570 void *xgmac_regs; /* AXGMAC CSRs */ 571 void *xpcs_regs; /* XPCS MMD registers */ 572 void *xprop_regs; /* AXGBE property registers */ 573 void *xi2c_regs; /* AXGBE I2C CSRs */ 574 575 /* Port property registers */ 576 unsigned int pp0; 577 unsigned int pp1; 578 unsigned int pp2; 579 unsigned int pp3; 580 unsigned int pp4; 581 582 bool cdr_track_early; 583 /* XPCS indirect addressing lock */ 584 unsigned int xpcs_window_def_reg; 585 unsigned int xpcs_window_sel_reg; 586 unsigned int xpcs_window; 587 unsigned int xpcs_window_size; 588 unsigned int xpcs_window_mask; 589 590 /* Flags representing axgbe_state */ 591 uint32_t dev_state; 592 593 struct axgbe_hw_if hw_if; 594 struct axgbe_phy_if phy_if; 595 struct axgbe_i2c_if i2c_if; 596 597 /* AXI DMA settings */ 598 unsigned int coherent; 599 unsigned int axdomain; 600 unsigned int arcache; 601 unsigned int awcache; 602 603 unsigned int tx_max_channel_count; 604 unsigned int rx_max_channel_count; 605 unsigned int channel_count; 606 unsigned int tx_ring_count; 607 unsigned int tx_desc_count; 608 unsigned int rx_ring_count; 609 unsigned int rx_desc_count; 610 611 unsigned int tx_max_q_count; 612 unsigned int rx_max_q_count; 613 unsigned int tx_q_count; 614 unsigned int rx_q_count; 615 616 /* Tx/Rx common settings */ 617 unsigned int pblx8; 618 619 /* Tx settings */ 620 unsigned int tx_sf_mode; 621 unsigned int tx_threshold; 622 unsigned int tx_pbl; 623 unsigned int tx_osp_mode; 624 unsigned int tx_max_fifo_size; 625 unsigned int multi_segs_tx; 626 627 /* Rx settings */ 628 unsigned int rx_sf_mode; 629 unsigned int rx_threshold; 630 unsigned int rx_pbl; 631 unsigned int rx_max_fifo_size; 632 unsigned int rx_buf_size; 633 634 /* Device clocks */ 635 unsigned long sysclk_rate; 636 unsigned long ptpclk_rate; 637 638 /* Keeps track of power mode */ 639 unsigned int power_down; 640 641 /* Current PHY settings */ 642 int phy_link; 643 int phy_speed; 644 645 pthread_mutex_t xpcs_mutex; 646 pthread_mutex_t i2c_mutex; 647 pthread_mutex_t an_mutex; 648 pthread_mutex_t phy_mutex; 649 650 /* Flow control settings */ 651 unsigned int pause_autoneg; 652 unsigned int tx_pause; 653 unsigned int rx_pause; 654 unsigned int rx_rfa[AXGBE_MAX_QUEUES]; 655 unsigned int rx_rfd[AXGBE_MAX_QUEUES]; 656 unsigned int fifo; 657 unsigned int pfc_map[AXGBE_MAX_QUEUES]; 658 659 /* Receive Side Scaling settings */ 660 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; 661 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; 662 uint32_t rss_options; 663 int rss_enable; 664 uint64_t rss_hf; 665 666 /* Hardware features of the device */ 667 struct axgbe_hw_features hw_feat; 668 669 struct rte_ether_addr mac_addr; 670 671 /* Software Tx/Rx structure pointers*/ 672 void **rx_queues; 673 void **tx_queues; 674 675 /* MDIO/PHY related settings */ 676 unsigned int phy_started; 677 void *phy_data; 678 struct axgbe_phy phy; 679 int mdio_mmd; 680 unsigned long link_check; 681 volatile int mdio_completion; 682 683 unsigned int kr_redrv; 684 685 /* Auto-negotiation state machine support */ 686 unsigned int an_int; 687 unsigned int an_status; 688 enum axgbe_an an_result; 689 enum axgbe_an an_state; 690 enum axgbe_rx kr_state; 691 enum axgbe_rx kx_state; 692 unsigned int an_again; 693 unsigned int an_supported; 694 unsigned int parallel_detect; 695 unsigned int fec_ability; 696 unsigned long an_start; 697 unsigned long kr_start_time; 698 enum axgbe_an_mode an_mode; 699 700 /* I2C support */ 701 struct axgbe_i2c i2c; 702 volatile int i2c_complete; 703 704 /* CRC stripping by H/w for Rx packet*/ 705 int crc_strip_enable; 706 /* csum enable to hardware */ 707 uint32_t rx_csum_enable; 708 709 struct axgbe_mmc_stats mmc_stats; 710 struct xgbe_fc_info fc; 711 712 /* Hash filtering */ 713 unsigned int hash_table_shift; 714 unsigned int hash_table_count; 715 unsigned int uc_hash_mac_addr; 716 unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; 717 718 /* Filtering support */ 719 unsigned long active_vlans[VLAN_TABLE_SIZE]; 720 721 /* For IEEE1588 PTP */ 722 struct rte_timecounter systime_tc; 723 struct rte_timecounter tx_tstamp; 724 unsigned int tstamp_addend; 725 726 bool en_rx_adap; 727 int rx_adapt_retries; 728 bool rx_adapt_done; 729 bool mode_set; 730 }; 731 732 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); 733 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if); 734 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); 735 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); 736 void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, 737 uint32_t index); 738 void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); 739 int axgbe_write_rss_lookup_table(struct axgbe_port *pdata); 740 int axgbe_write_rss_hash_key(struct axgbe_port *pdata); 741 742 #endif /* RTE_ETH_AXGBE_H_ */ 743