1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef RTE_ETH_AXGBE_H_ 7 #define RTE_ETH_AXGBE_H_ 8 9 #include <rte_mempool.h> 10 #include <rte_lcore.h> 11 #include "axgbe_common.h" 12 #include "rte_time.h" 13 14 #define IRQ 0xff 15 #define VLAN_HLEN 4 16 17 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 18 #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 19 #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN) 20 #define AXGBE_MAX_MAC_ADDRS 32 21 #define AXGBE_MAX_HASH_MAC_ADDRS 256 22 23 #define AXGBE_RX_BUF_ALIGN 64 24 25 #define AXGBE_MAX_DMA_CHANNELS 16 26 #define AXGBE_MAX_QUEUES 16 27 #define AXGBE_PRIORITY_QUEUES 8 28 #define AXGBE_DMA_STOP_TIMEOUT 1 29 30 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 31 #define AXGBE_DMA_OS_AXDOMAIN 0x2 32 #define AXGBE_DMA_OS_ARCACHE 0xb 33 #define AXGBE_DMA_OS_AWCACHE 0xf 34 35 /* DMA cache settings - System, no caches used */ 36 #define AXGBE_DMA_SYS_AXDOMAIN 0x3 37 #define AXGBE_DMA_SYS_ARCACHE 0x0 38 #define AXGBE_DMA_SYS_AWCACHE 0x0 39 40 /* DMA channel interrupt modes */ 41 #define AXGBE_IRQ_MODE_EDGE 0 42 #define AXGBE_IRQ_MODE_LEVEL 1 43 44 #define AXGBE_DMA_INTERRUPT_MASK 0x31c7 45 46 #define AXGMAC_MIN_PACKET 60 47 #define AXGMAC_STD_PACKET_MTU 1500 48 #define AXGMAC_MAX_STD_PACKET 1518 49 #define AXGMAC_JUMBO_PACKET_MTU 9000 50 #define AXGMAC_MAX_JUMBO_PACKET 9018 51 /* Inter-frame gap + preamble */ 52 #define AXGMAC_ETH_PREAMBLE (12 + 8) 53 54 #define AXGMAC_PFC_DATA_LEN 46 55 #define AXGMAC_PFC_DELAYS 14000 56 57 /* PCI BAR mapping */ 58 #define AXGBE_AXGMAC_BAR 0 59 #define AXGBE_XPCS_BAR 1 60 #define AXGBE_MAC_PROP_OFFSET 0x1d000 61 #define AXGBE_I2C_CTRL_OFFSET 0x1e000 62 63 /* PCI clock frequencies */ 64 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000 65 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000 66 67 /* Timestamp support - values based on 50MHz PTP clock 68 * 50MHz => 20 nsec 69 */ 70 #define AXGBE_TSTAMP_SSINC 20 71 #define AXGBE_TSTAMP_SNSINC 0 72 #define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 73 74 #define AXGMAC_FIFO_MIN_ALLOC 2048 75 #define AXGMAC_FIFO_UNIT 256 76 #define AXGMAC_FIFO_ALIGN(_x) \ 77 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 78 #define AXGMAC_FIFO_FC_OFF 2048 79 #define AXGMAC_FIFO_FC_MIN 4096 80 81 #define AXGBE_TC_MIN_QUANTUM 10 82 83 /* Flow control queue count */ 84 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8 85 86 /* Flow control threshold units */ 87 #define AXGMAC_FLOW_CONTROL_UNIT 512 88 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \ 89 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \ 90 ~(AXGMAC_FLOW_CONTROL_UNIT - 1)) 91 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \ 92 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) 93 #define AXGMAC_FLOW_CONTROL_MAX 33280 94 95 /* Maximum MAC address hash table size (256 bits = 8 dword) */ 96 #define AXGBE_MAC_HASH_TABLE_SIZE 8 97 98 /* Receive Side Scaling */ 99 #define AXGBE_RSS_OFFLOAD ( \ 100 ETH_RSS_IPV4 | \ 101 ETH_RSS_NONFRAG_IPV4_TCP | \ 102 ETH_RSS_NONFRAG_IPV4_UDP | \ 103 ETH_RSS_IPV6 | \ 104 ETH_RSS_NONFRAG_IPV6_TCP | \ 105 ETH_RSS_NONFRAG_IPV6_UDP) 106 107 #define AXGBE_RSS_HASH_KEY_SIZE 40 108 #define AXGBE_RSS_MAX_TABLE_SIZE 256 109 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0 110 #define AXGBE_RSS_HASH_KEY_TYPE 1 111 112 /* Auto-negotiation */ 113 #define AXGBE_AN_MS_TIMEOUT 500 114 #define AXGBE_LINK_TIMEOUT 5 115 116 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1) 117 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 118 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04 119 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08 120 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4) 121 122 /* ECC correctable error notification window (seconds) */ 123 #define AXGBE_ECC_LIMIT 60 124 125 /* MDIO port types */ 126 #define AXGMAC_MAX_C22_PORT 3 127 128 /* The max frame size with default MTU */ 129 #define AXGBE_ETH_MAX_LEN ( \ 130 RTE_ETHER_MTU + \ 131 RTE_ETHER_HDR_LEN + \ 132 RTE_ETHER_CRC_LEN) 133 134 /* Helper macro for descriptor handling 135 * Always use AXGBE_GET_DESC_DATA to access the descriptor data 136 * since the index is free-running and needs to be and-ed 137 * with the descriptor count value of the ring to index to 138 * the proper descriptor data. 139 */ 140 #define AXGBE_GET_DESC_DATA(_ring, _idx) \ 141 ((_ring)->rdata + \ 142 ((_idx) & ((_ring)->rdesc_count - 1))) 143 144 struct axgbe_port; 145 146 enum axgbe_state { 147 AXGBE_DOWN, 148 AXGBE_LINK_INIT, 149 AXGBE_LINK_ERR, 150 AXGBE_STOPPED, 151 }; 152 153 enum axgbe_int { 154 AXGMAC_INT_DMA_CH_SR_TI, 155 AXGMAC_INT_DMA_CH_SR_TPS, 156 AXGMAC_INT_DMA_CH_SR_TBU, 157 AXGMAC_INT_DMA_CH_SR_RI, 158 AXGMAC_INT_DMA_CH_SR_RBU, 159 AXGMAC_INT_DMA_CH_SR_RPS, 160 AXGMAC_INT_DMA_CH_SR_TI_RI, 161 AXGMAC_INT_DMA_CH_SR_FBE, 162 AXGMAC_INT_DMA_ALL, 163 }; 164 165 enum axgbe_int_state { 166 AXGMAC_INT_STATE_SAVE, 167 AXGMAC_INT_STATE_RESTORE, 168 }; 169 170 enum axgbe_ecc_sec { 171 AXGBE_ECC_SEC_TX, 172 AXGBE_ECC_SEC_RX, 173 AXGBE_ECC_SEC_DESC, 174 }; 175 176 enum axgbe_speed { 177 AXGBE_SPEED_1000 = 0, 178 AXGBE_SPEED_2500, 179 AXGBE_SPEED_10000, 180 AXGBE_SPEEDS, 181 }; 182 183 enum axgbe_xpcs_access { 184 AXGBE_XPCS_ACCESS_V1 = 0, 185 AXGBE_XPCS_ACCESS_V2, 186 }; 187 188 enum axgbe_an_mode { 189 AXGBE_AN_MODE_CL73 = 0, 190 AXGBE_AN_MODE_CL73_REDRV, 191 AXGBE_AN_MODE_CL37, 192 AXGBE_AN_MODE_CL37_SGMII, 193 AXGBE_AN_MODE_NONE, 194 }; 195 196 enum axgbe_an { 197 AXGBE_AN_READY = 0, 198 AXGBE_AN_PAGE_RECEIVED, 199 AXGBE_AN_INCOMPAT_LINK, 200 AXGBE_AN_COMPLETE, 201 AXGBE_AN_NO_LINK, 202 AXGBE_AN_ERROR, 203 }; 204 205 enum axgbe_rx { 206 AXGBE_RX_BPA = 0, 207 AXGBE_RX_XNP, 208 AXGBE_RX_COMPLETE, 209 AXGBE_RX_ERROR, 210 }; 211 212 enum axgbe_mode { 213 AXGBE_MODE_KX_1000 = 0, 214 AXGBE_MODE_KX_2500, 215 AXGBE_MODE_KR, 216 AXGBE_MODE_X, 217 AXGBE_MODE_SGMII_100, 218 AXGBE_MODE_SGMII_1000, 219 AXGBE_MODE_SFI, 220 AXGBE_MODE_UNKNOWN, 221 }; 222 223 enum axgbe_speedset { 224 AXGBE_SPEEDSET_1000_10000 = 0, 225 AXGBE_SPEEDSET_2500_10000, 226 }; 227 228 enum axgbe_mdio_mode { 229 AXGBE_MDIO_MODE_NONE = 0, 230 AXGBE_MDIO_MODE_CL22, 231 AXGBE_MDIO_MODE_CL45, 232 }; 233 234 struct axgbe_phy { 235 uint32_t supported; 236 uint32_t advertising; 237 uint32_t lp_advertising; 238 239 int address; 240 241 int autoneg; 242 int speed; 243 int duplex; 244 245 int link; 246 247 int pause_autoneg; 248 int tx_pause; 249 int rx_pause; 250 }; 251 252 enum axgbe_i2c_cmd { 253 AXGBE_I2C_CMD_READ = 0, 254 AXGBE_I2C_CMD_WRITE, 255 }; 256 257 struct axgbe_i2c_op { 258 enum axgbe_i2c_cmd cmd; 259 260 unsigned int target; 261 262 uint8_t *buf; 263 unsigned int len; 264 }; 265 266 struct axgbe_i2c_op_state { 267 struct axgbe_i2c_op *op; 268 269 unsigned int tx_len; 270 unsigned char *tx_buf; 271 272 unsigned int rx_len; 273 unsigned char *rx_buf; 274 275 unsigned int tx_abort_source; 276 277 int ret; 278 }; 279 280 struct axgbe_i2c { 281 unsigned int started; 282 unsigned int max_speed_mode; 283 unsigned int rx_fifo_size; 284 unsigned int tx_fifo_size; 285 286 struct axgbe_i2c_op_state op_state; 287 }; 288 289 struct axgbe_hw_if { 290 void (*config_flow_control)(struct axgbe_port *); 291 int (*config_rx_mode)(struct axgbe_port *); 292 293 int (*init)(struct axgbe_port *); 294 295 int (*read_mmd_regs)(struct axgbe_port *, int, int); 296 void (*write_mmd_regs)(struct axgbe_port *, int, int, int); 297 int (*set_speed)(struct axgbe_port *, int); 298 299 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int, 300 enum axgbe_mdio_mode); 301 int (*read_ext_mii_regs)(struct axgbe_port *, int, int); 302 int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t); 303 304 /* For FLOW ctrl */ 305 int (*config_tx_flow_control)(struct axgbe_port *); 306 int (*config_rx_flow_control)(struct axgbe_port *); 307 308 /* vlan */ 309 int (*enable_rx_vlan_stripping)(struct axgbe_port *); 310 int (*disable_rx_vlan_stripping)(struct axgbe_port *); 311 int (*enable_rx_vlan_filtering)(struct axgbe_port *); 312 int (*disable_rx_vlan_filtering)(struct axgbe_port *); 313 int (*update_vlan_hash_table)(struct axgbe_port *); 314 315 int (*exit)(struct axgbe_port *); 316 }; 317 318 /* This structure represents implementation specific routines for an 319 * implementation of a PHY. All routines are required unless noted below. 320 * Optional routines: 321 * kr_training_pre, kr_training_post 322 */ 323 struct axgbe_phy_impl_if { 324 /* Perform Setup/teardown actions */ 325 int (*init)(struct axgbe_port *); 326 void (*exit)(struct axgbe_port *); 327 328 /* Perform start/stop specific actions */ 329 int (*reset)(struct axgbe_port *); 330 int (*start)(struct axgbe_port *); 331 void (*stop)(struct axgbe_port *); 332 333 /* Return the link status */ 334 int (*link_status)(struct axgbe_port *, int *); 335 336 /* Indicate if a particular speed is valid */ 337 int (*valid_speed)(struct axgbe_port *, int); 338 339 /* Check if the specified mode can/should be used */ 340 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode); 341 /* Switch the PHY into various modes */ 342 void (*set_mode)(struct axgbe_port *, enum axgbe_mode); 343 /* Retrieve mode needed for a specific speed */ 344 enum axgbe_mode (*get_mode)(struct axgbe_port *, int); 345 /* Retrieve new/next mode when trying to auto-negotiate */ 346 enum axgbe_mode (*switch_mode)(struct axgbe_port *); 347 /* Retrieve current mode */ 348 enum axgbe_mode (*cur_mode)(struct axgbe_port *); 349 350 /* Retrieve current auto-negotiation mode */ 351 enum axgbe_an_mode (*an_mode)(struct axgbe_port *); 352 353 /* Configure auto-negotiation settings */ 354 int (*an_config)(struct axgbe_port *); 355 356 /* Set/override auto-negotiation advertisement settings */ 357 unsigned int (*an_advertising)(struct axgbe_port *port); 358 359 /* Process results of auto-negotiation */ 360 enum axgbe_mode (*an_outcome)(struct axgbe_port *); 361 362 /* Pre/Post auto-negotiation support */ 363 void (*an_pre)(struct axgbe_port *port); 364 void (*an_post)(struct axgbe_port *port); 365 366 /* Pre/Post KR training enablement support */ 367 void (*kr_training_pre)(struct axgbe_port *); 368 void (*kr_training_post)(struct axgbe_port *); 369 }; 370 371 struct axgbe_phy_if { 372 /* For PHY setup/teardown */ 373 int (*phy_init)(struct axgbe_port *); 374 void (*phy_exit)(struct axgbe_port *); 375 376 /* For PHY support when setting device up/down */ 377 int (*phy_reset)(struct axgbe_port *); 378 int (*phy_start)(struct axgbe_port *); 379 void (*phy_stop)(struct axgbe_port *); 380 381 /* For PHY support while device is up */ 382 void (*phy_status)(struct axgbe_port *); 383 int (*phy_config_aneg)(struct axgbe_port *); 384 385 /* For PHY settings validation */ 386 int (*phy_valid_speed)(struct axgbe_port *, int); 387 /* For single interrupt support */ 388 void (*an_isr)(struct axgbe_port *); 389 /* PHY implementation specific services */ 390 struct axgbe_phy_impl_if phy_impl; 391 }; 392 393 struct axgbe_i2c_if { 394 /* For initial I2C setup */ 395 int (*i2c_init)(struct axgbe_port *); 396 397 /* For I2C support when setting device up/down */ 398 int (*i2c_start)(struct axgbe_port *); 399 void (*i2c_stop)(struct axgbe_port *); 400 401 /* For performing I2C operations */ 402 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *); 403 }; 404 405 /* This structure contains flags that indicate what hardware features 406 * or configurations are present in the device. 407 */ 408 struct axgbe_hw_features { 409 /* HW Version */ 410 unsigned int version; 411 412 /* HW Feature Register0 */ 413 unsigned int gmii; /* 1000 Mbps support */ 414 unsigned int vlhash; /* VLAN Hash Filter */ 415 unsigned int sma; /* SMA(MDIO) Interface */ 416 unsigned int rwk; /* PMT remote wake-up packet */ 417 unsigned int mgk; /* PMT magic packet */ 418 unsigned int mmc; /* RMON module */ 419 unsigned int aoe; /* ARP Offload */ 420 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 421 unsigned int eee; /* Energy Efficient Ethernet */ 422 unsigned int tx_coe; /* Tx Checksum Offload */ 423 unsigned int rx_coe; /* Rx Checksum Offload */ 424 unsigned int addn_mac; /* Additional MAC Addresses */ 425 unsigned int ts_src; /* Timestamp Source */ 426 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 427 428 /* HW Feature Register1 */ 429 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 430 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 431 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 432 unsigned int dma_width; /* DMA width */ 433 unsigned int dcb; /* DCB Feature */ 434 unsigned int sph; /* Split Header Feature */ 435 unsigned int tso; /* TCP Segmentation Offload */ 436 unsigned int dma_debug; /* DMA Debug Registers */ 437 unsigned int rss; /* Receive Side Scaling */ 438 unsigned int tc_cnt; /* Number of Traffic Classes */ 439 unsigned int hash_table_size; /* Hash Table Size */ 440 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 441 442 /* HW Feature Register2 */ 443 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 444 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 445 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 446 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 447 unsigned int pps_out_num; /* Number of PPS outputs */ 448 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 449 450 /* HW Feature Register3 */ 451 unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */ 452 /* insertion on Tx Enable */ 453 unsigned int no_of_vlan_extn; /* Number of Extended VLAN Tag */ 454 /* Filters Enabled */ 455 }; 456 457 struct axgbe_version_data { 458 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *); 459 enum axgbe_xpcs_access xpcs_access; 460 unsigned int mmc_64bit; 461 unsigned int tx_max_fifo_size; 462 unsigned int rx_max_fifo_size; 463 unsigned int tx_tstamp_workaround; 464 unsigned int ecc_support; 465 unsigned int i2c_support; 466 unsigned int an_cdr_workaround; 467 }; 468 469 struct axgbe_mmc_stats { 470 /* Tx Stats */ 471 uint64_t txoctetcount_gb; 472 uint64_t txframecount_gb; 473 uint64_t txbroadcastframes_g; 474 uint64_t txmulticastframes_g; 475 uint64_t tx64octets_gb; 476 uint64_t tx65to127octets_gb; 477 uint64_t tx128to255octets_gb; 478 uint64_t tx256to511octets_gb; 479 uint64_t tx512to1023octets_gb; 480 uint64_t tx1024tomaxoctets_gb; 481 uint64_t txunicastframes_gb; 482 uint64_t txmulticastframes_gb; 483 uint64_t txbroadcastframes_gb; 484 uint64_t txunderflowerror; 485 uint64_t txoctetcount_g; 486 uint64_t txframecount_g; 487 uint64_t txpauseframes; 488 uint64_t txvlanframes_g; 489 490 /* Rx Stats */ 491 uint64_t rxframecount_gb; 492 uint64_t rxoctetcount_gb; 493 uint64_t rxoctetcount_g; 494 uint64_t rxbroadcastframes_g; 495 uint64_t rxmulticastframes_g; 496 uint64_t rxcrcerror; 497 uint64_t rxrunterror; 498 uint64_t rxjabbererror; 499 uint64_t rxundersize_g; 500 uint64_t rxoversize_g; 501 uint64_t rx64octets_gb; 502 uint64_t rx65to127octets_gb; 503 uint64_t rx128to255octets_gb; 504 uint64_t rx256to511octets_gb; 505 uint64_t rx512to1023octets_gb; 506 uint64_t rx1024tomaxoctets_gb; 507 uint64_t rxunicastframes_g; 508 uint64_t rxlengtherror; 509 uint64_t rxoutofrangetype; 510 uint64_t rxpauseframes; 511 uint64_t rxfifooverflow; 512 uint64_t rxvlanframes_gb; 513 uint64_t rxwatchdogerror; 514 }; 515 516 /* Flow control parameters */ 517 struct xgbe_fc_info { 518 uint32_t high_water[AXGBE_PRIORITY_QUEUES]; 519 uint32_t low_water[AXGBE_PRIORITY_QUEUES]; 520 uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; 521 uint16_t send_xon; 522 enum rte_eth_fc_mode mode; 523 uint8_t autoneg; 524 }; 525 526 /* 527 * Structure to store private data for each port. 528 */ 529 struct axgbe_port { 530 /* Ethdev where port belongs*/ 531 struct rte_eth_dev *eth_dev; 532 /* Pci dev info */ 533 const struct rte_pci_device *pci_dev; 534 /* Version related data */ 535 struct axgbe_version_data *vdata; 536 537 /* AXGMAC/XPCS related mmio registers */ 538 void *xgmac_regs; /* AXGMAC CSRs */ 539 void *xpcs_regs; /* XPCS MMD registers */ 540 void *xprop_regs; /* AXGBE property registers */ 541 void *xi2c_regs; /* AXGBE I2C CSRs */ 542 543 bool cdr_track_early; 544 /* XPCS indirect addressing lock */ 545 unsigned int xpcs_window_def_reg; 546 unsigned int xpcs_window_sel_reg; 547 unsigned int xpcs_window; 548 unsigned int xpcs_window_size; 549 unsigned int xpcs_window_mask; 550 551 /* Flags representing axgbe_state */ 552 uint32_t dev_state; 553 554 struct axgbe_hw_if hw_if; 555 struct axgbe_phy_if phy_if; 556 struct axgbe_i2c_if i2c_if; 557 558 /* AXI DMA settings */ 559 unsigned int coherent; 560 unsigned int axdomain; 561 unsigned int arcache; 562 unsigned int awcache; 563 564 unsigned int tx_max_channel_count; 565 unsigned int rx_max_channel_count; 566 unsigned int channel_count; 567 unsigned int tx_ring_count; 568 unsigned int tx_desc_count; 569 unsigned int rx_ring_count; 570 unsigned int rx_desc_count; 571 572 unsigned int tx_max_q_count; 573 unsigned int rx_max_q_count; 574 unsigned int tx_q_count; 575 unsigned int rx_q_count; 576 577 /* Tx/Rx common settings */ 578 unsigned int pblx8; 579 580 /* Tx settings */ 581 unsigned int tx_sf_mode; 582 unsigned int tx_threshold; 583 unsigned int tx_pbl; 584 unsigned int tx_osp_mode; 585 unsigned int tx_max_fifo_size; 586 587 /* Rx settings */ 588 unsigned int rx_sf_mode; 589 unsigned int rx_threshold; 590 unsigned int rx_pbl; 591 unsigned int rx_max_fifo_size; 592 unsigned int rx_buf_size; 593 594 /* Device clocks */ 595 unsigned long sysclk_rate; 596 unsigned long ptpclk_rate; 597 598 /* Keeps track of power mode */ 599 unsigned int power_down; 600 601 /* Current PHY settings */ 602 int phy_link; 603 int phy_speed; 604 605 pthread_mutex_t xpcs_mutex; 606 pthread_mutex_t i2c_mutex; 607 pthread_mutex_t an_mutex; 608 pthread_mutex_t phy_mutex; 609 610 /* Flow control settings */ 611 unsigned int pause_autoneg; 612 unsigned int tx_pause; 613 unsigned int rx_pause; 614 unsigned int rx_rfa[AXGBE_MAX_QUEUES]; 615 unsigned int rx_rfd[AXGBE_MAX_QUEUES]; 616 unsigned int fifo; 617 unsigned int pfc_map[AXGBE_MAX_QUEUES]; 618 619 /* Receive Side Scaling settings */ 620 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; 621 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; 622 uint32_t rss_options; 623 int rss_enable; 624 uint64_t rss_hf; 625 626 /* Hardware features of the device */ 627 struct axgbe_hw_features hw_feat; 628 629 struct rte_ether_addr mac_addr; 630 631 /* Software Tx/Rx structure pointers*/ 632 void **rx_queues; 633 void **tx_queues; 634 635 /* MDIO/PHY related settings */ 636 unsigned int phy_started; 637 void *phy_data; 638 struct axgbe_phy phy; 639 int mdio_mmd; 640 unsigned long link_check; 641 volatile int mdio_completion; 642 643 unsigned int kr_redrv; 644 645 /* Auto-negotiation atate machine support */ 646 unsigned int an_int; 647 unsigned int an_status; 648 enum axgbe_an an_result; 649 enum axgbe_an an_state; 650 enum axgbe_rx kr_state; 651 enum axgbe_rx kx_state; 652 unsigned int an_supported; 653 unsigned int parallel_detect; 654 unsigned int fec_ability; 655 unsigned long an_start; 656 enum axgbe_an_mode an_mode; 657 658 /* I2C support */ 659 struct axgbe_i2c i2c; 660 volatile int i2c_complete; 661 662 /* CRC stripping by H/w for Rx packet*/ 663 int crc_strip_enable; 664 /* csum enable to hardware */ 665 uint32_t rx_csum_enable; 666 667 struct axgbe_mmc_stats mmc_stats; 668 struct xgbe_fc_info fc; 669 670 /* Hash filtering */ 671 unsigned int hash_table_shift; 672 unsigned int hash_table_count; 673 unsigned int uc_hash_mac_addr; 674 unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; 675 676 /* Filtering support */ 677 unsigned long active_vlans[VLAN_TABLE_SIZE]; 678 679 /* For IEEE1588 PTP */ 680 struct rte_timecounter systime_tc; 681 struct rte_timecounter tx_tstamp; 682 unsigned int tstamp_addend; 683 684 }; 685 686 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); 687 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if); 688 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); 689 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); 690 void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, 691 uint32_t index); 692 void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); 693 int axgbe_write_rss_lookup_table(struct axgbe_port *pdata); 694 int axgbe_write_rss_hash_key(struct axgbe_port *pdata); 695 696 #endif /* RTE_ETH_AXGBE_H_ */ 697