1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef RTE_ETH_AXGBE_H_ 7 #define RTE_ETH_AXGBE_H_ 8 9 #include <rte_mempool.h> 10 #include <rte_lcore.h> 11 #include "axgbe_common.h" 12 #include "rte_time.h" 13 14 #define IRQ 0xff 15 16 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 17 #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 18 #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + RTE_VLAN_HLEN) 19 #define AXGBE_MAX_MAC_ADDRS 32 20 #define AXGBE_MAX_HASH_MAC_ADDRS 256 21 22 #define AXGBE_RX_BUF_ALIGN 64 23 24 #define AXGBE_MAX_DMA_CHANNELS 16 25 #define AXGBE_MAX_QUEUES 16 26 #define AXGBE_PRIORITY_QUEUES 8 27 #define AXGBE_DMA_STOP_TIMEOUT 1 28 29 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 30 #define AXGBE_DMA_OS_AXDOMAIN 0x2 31 #define AXGBE_DMA_OS_ARCACHE 0xb 32 #define AXGBE_DMA_OS_AWCACHE 0xf 33 34 /* DMA cache settings - System, no caches used */ 35 #define AXGBE_DMA_SYS_AXDOMAIN 0x3 36 #define AXGBE_DMA_SYS_ARCACHE 0x0 37 #define AXGBE_DMA_SYS_AWCACHE 0x0 38 39 /* DMA channel interrupt modes */ 40 #define AXGBE_IRQ_MODE_EDGE 0 41 #define AXGBE_IRQ_MODE_LEVEL 1 42 43 #define AXGBE_DMA_INTERRUPT_MASK 0x31c7 44 45 #define AXGMAC_MIN_PACKET 60 46 #define AXGMAC_STD_PACKET_MTU 1500 47 #define AXGMAC_MAX_STD_PACKET 1518 48 #define AXGMAC_JUMBO_PACKET_MTU 9000 49 #define AXGMAC_MAX_JUMBO_PACKET 9018 50 /* Inter-frame gap + preamble */ 51 #define AXGMAC_ETH_PREAMBLE (12 + 8) 52 53 #define AXGMAC_PFC_DATA_LEN 46 54 #define AXGMAC_PFC_DELAYS 14000 55 56 /* PCI BAR mapping */ 57 #define AXGBE_AXGMAC_BAR 0 58 #define AXGBE_XPCS_BAR 1 59 #define AXGBE_MAC_PROP_OFFSET 0x1d000 60 #define AXGBE_I2C_CTRL_OFFSET 0x1e000 61 62 /* PCI clock frequencies */ 63 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000 64 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000 65 66 /* Timestamp support - values based on 50MHz PTP clock 67 * 50MHz => 20 nsec 68 */ 69 #define AXGBE_TSTAMP_SSINC 20 70 #define AXGBE_TSTAMP_SNSINC 0 71 #define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 72 73 #define AXGMAC_FIFO_MIN_ALLOC 2048 74 #define AXGMAC_FIFO_UNIT 256 75 #define AXGMAC_FIFO_ALIGN(_x) \ 76 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 77 #define AXGMAC_FIFO_FC_OFF 2048 78 #define AXGMAC_FIFO_FC_MIN 4096 79 80 #define AXGBE_TC_MIN_QUANTUM 10 81 82 /* Flow control queue count */ 83 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8 84 85 /* Flow control threshold units */ 86 #define AXGMAC_FLOW_CONTROL_UNIT 512 87 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \ 88 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \ 89 ~(AXGMAC_FLOW_CONTROL_UNIT - 1)) 90 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \ 91 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) 92 #define AXGMAC_FLOW_CONTROL_MAX 33280 93 94 /* Maximum MAC address hash table size (256 bits = 8 dword) */ 95 #define AXGBE_MAC_HASH_TABLE_SIZE 8 96 97 /* Receive Side Scaling */ 98 #define AXGBE_RSS_OFFLOAD ( \ 99 RTE_ETH_RSS_IPV4 | \ 100 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 101 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 102 RTE_ETH_RSS_IPV6 | \ 103 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 104 RTE_ETH_RSS_NONFRAG_IPV6_UDP) 105 106 #define AXGBE_RSS_HASH_KEY_SIZE 40 107 #define AXGBE_RSS_MAX_TABLE_SIZE 256 108 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0 109 #define AXGBE_RSS_HASH_KEY_TYPE 1 110 111 /* Auto-negotiation */ 112 #define AXGBE_AN_MS_TIMEOUT 500 113 #define AXGBE_LINK_TIMEOUT 5 114 #define AXGBE_KR_TRAINING_WAIT_ITER 50 115 116 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1) 117 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 118 #define AXGBE_SGMII_AN_LINK_SPEED_10 0x00 119 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04 120 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08 121 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4) 122 123 /* ECC correctable error notification window (seconds) */ 124 #define AXGBE_ECC_LIMIT 60 125 126 /* MDIO port types */ 127 #define AXGMAC_MAX_C22_PORT 3 128 129 /* The max frame size with default MTU */ 130 #define AXGBE_ETH_MAX_LEN ( \ 131 RTE_ETHER_MTU + \ 132 RTE_ETHER_HDR_LEN + \ 133 RTE_ETHER_CRC_LEN) 134 135 /* Helper macro for descriptor handling 136 * Always use AXGBE_GET_DESC_DATA to access the descriptor data 137 * since the index is free-running and needs to be and-ed 138 * with the descriptor count value of the ring to index to 139 * the proper descriptor data. 140 */ 141 #define AXGBE_GET_DESC_DATA(_ring, _idx) \ 142 ((_ring)->rdata + \ 143 ((_idx) & ((_ring)->rdesc_count - 1))) 144 145 struct axgbe_port; 146 147 enum axgbe_state { 148 AXGBE_DOWN, 149 AXGBE_LINK_INIT, 150 AXGBE_LINK_ERR, 151 AXGBE_STOPPED, 152 }; 153 154 enum axgbe_int { 155 AXGMAC_INT_DMA_CH_SR_TI, 156 AXGMAC_INT_DMA_CH_SR_TPS, 157 AXGMAC_INT_DMA_CH_SR_TBU, 158 AXGMAC_INT_DMA_CH_SR_RI, 159 AXGMAC_INT_DMA_CH_SR_RBU, 160 AXGMAC_INT_DMA_CH_SR_RPS, 161 AXGMAC_INT_DMA_CH_SR_TI_RI, 162 AXGMAC_INT_DMA_CH_SR_FBE, 163 AXGMAC_INT_DMA_ALL, 164 }; 165 166 enum axgbe_int_state { 167 AXGMAC_INT_STATE_SAVE, 168 AXGMAC_INT_STATE_RESTORE, 169 }; 170 171 enum axgbe_ecc_sec { 172 AXGBE_ECC_SEC_TX, 173 AXGBE_ECC_SEC_RX, 174 AXGBE_ECC_SEC_DESC, 175 }; 176 177 enum axgbe_speed { 178 AXGBE_SPEED_1000 = 0, 179 AXGBE_SPEED_2500, 180 AXGBE_SPEED_10000, 181 AXGBE_SPEEDS, 182 }; 183 184 enum axgbe_xpcs_access { 185 AXGBE_XPCS_ACCESS_V1 = 0, 186 AXGBE_XPCS_ACCESS_V2, 187 }; 188 189 enum axgbe_an_mode { 190 AXGBE_AN_MODE_CL73 = 0, 191 AXGBE_AN_MODE_CL73_REDRV, 192 AXGBE_AN_MODE_CL37, 193 AXGBE_AN_MODE_CL37_SGMII, 194 AXGBE_AN_MODE_NONE, 195 }; 196 197 enum axgbe_an { 198 AXGBE_AN_READY = 0, 199 AXGBE_AN_PAGE_RECEIVED, 200 AXGBE_AN_INCOMPAT_LINK, 201 AXGBE_AN_COMPLETE, 202 AXGBE_AN_NO_LINK, 203 AXGBE_AN_ERROR, 204 }; 205 206 enum axgbe_rx { 207 AXGBE_RX_BPA = 0, 208 AXGBE_RX_XNP, 209 AXGBE_RX_COMPLETE, 210 AXGBE_RX_ERROR, 211 }; 212 213 enum axgbe_mode { 214 AXGBE_MODE_KX_1000 = 0, 215 AXGBE_MODE_KX_2500, 216 AXGBE_MODE_KR, 217 AXGBE_MODE_X, 218 AXGBE_MODE_SGMII_10, 219 AXGBE_MODE_SGMII_100, 220 AXGBE_MODE_SGMII_1000, 221 AXGBE_MODE_SFI, 222 AXGBE_MODE_UNKNOWN, 223 }; 224 225 enum axgbe_speedset { 226 AXGBE_SPEEDSET_1000_10000 = 0, 227 AXGBE_SPEEDSET_2500_10000, 228 }; 229 230 enum axgbe_mdio_mode { 231 AXGBE_MDIO_MODE_NONE = 0, 232 AXGBE_MDIO_MODE_CL22, 233 AXGBE_MDIO_MODE_CL45, 234 }; 235 236 enum axgbe_mb_cmd { 237 AXGBE_MB_CMD_POWER_OFF = 0, 238 AXGBE_MB_CMD_SET_1G, 239 AXGBE_MB_CMD_SET_2_5G, 240 AXGBE_MB_CMD_SET_10G_SFI, 241 AXGBE_MB_CMD_SET_10G_KR, 242 AXGBE_MB_CMD_RRC 243 }; 244 245 enum axgbe_mb_subcmd { 246 AXGBE_MB_SUBCMD_NONE = 0, 247 248 /* 10GbE SFP subcommands */ 249 AXGBE_MB_SUBCMD_ACTIVE = 0, 250 AXGBE_MB_SUBCMD_PASSIVE_1M, 251 AXGBE_MB_SUBCMD_PASSIVE_3M, 252 AXGBE_MB_SUBCMD_PASSIVE_OTHER, 253 254 /* 1GbE Mode subcommands */ 255 AXGBE_MB_SUBCMD_10MBITS = 0, 256 AXGBE_MB_SUBCMD_100MBITS, 257 AXGBE_MB_SUBCMD_1G_SGMII, 258 AXGBE_MB_SUBCMD_1G_KX 259 }; 260 261 struct axgbe_phy { 262 uint32_t supported; 263 uint32_t advertising; 264 uint32_t lp_advertising; 265 266 int address; 267 268 int autoneg; 269 int speed; 270 int duplex; 271 272 int link; 273 274 int pause_autoneg; 275 int tx_pause; 276 int rx_pause; 277 }; 278 279 enum axgbe_i2c_cmd { 280 AXGBE_I2C_CMD_READ = 0, 281 AXGBE_I2C_CMD_WRITE, 282 }; 283 284 struct axgbe_i2c_op { 285 enum axgbe_i2c_cmd cmd; 286 287 unsigned int target; 288 289 uint8_t *buf; 290 unsigned int len; 291 }; 292 293 struct axgbe_i2c_op_state { 294 struct axgbe_i2c_op *op; 295 296 unsigned int tx_len; 297 unsigned char *tx_buf; 298 299 unsigned int rx_len; 300 unsigned char *rx_buf; 301 302 unsigned int tx_abort_source; 303 304 int ret; 305 }; 306 307 struct axgbe_i2c { 308 unsigned int started; 309 unsigned int max_speed_mode; 310 unsigned int rx_fifo_size; 311 unsigned int tx_fifo_size; 312 313 struct axgbe_i2c_op_state op_state; 314 }; 315 316 struct axgbe_hw_if { 317 void (*config_flow_control)(struct axgbe_port *); 318 int (*config_rx_mode)(struct axgbe_port *); 319 320 int (*init)(struct axgbe_port *); 321 322 int (*read_mmd_regs)(struct axgbe_port *, int, int); 323 void (*write_mmd_regs)(struct axgbe_port *, int, int, int); 324 int (*set_speed)(struct axgbe_port *, int); 325 326 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int, 327 enum axgbe_mdio_mode); 328 int (*read_ext_mii_regs)(struct axgbe_port *, int, int); 329 int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t); 330 331 /* For FLOW ctrl */ 332 int (*config_tx_flow_control)(struct axgbe_port *); 333 int (*config_rx_flow_control)(struct axgbe_port *); 334 335 /* vlan */ 336 int (*enable_rx_vlan_stripping)(struct axgbe_port *); 337 int (*disable_rx_vlan_stripping)(struct axgbe_port *); 338 int (*enable_rx_vlan_filtering)(struct axgbe_port *); 339 int (*disable_rx_vlan_filtering)(struct axgbe_port *); 340 int (*update_vlan_hash_table)(struct axgbe_port *); 341 342 int (*exit)(struct axgbe_port *); 343 }; 344 345 /* This structure represents implementation specific routines for an 346 * implementation of a PHY. All routines are required unless noted below. 347 * Optional routines: 348 * kr_training_pre, kr_training_post 349 */ 350 struct axgbe_phy_impl_if { 351 /* Perform Setup/teardown actions */ 352 int (*init)(struct axgbe_port *); 353 void (*exit)(struct axgbe_port *); 354 355 /* Perform start/stop specific actions */ 356 int (*reset)(struct axgbe_port *); 357 int (*start)(struct axgbe_port *); 358 void (*stop)(struct axgbe_port *); 359 360 /* Return the link status */ 361 int (*link_status)(struct axgbe_port *, int *); 362 363 /* Indicate if a particular speed is valid */ 364 int (*valid_speed)(struct axgbe_port *, int); 365 366 /* Check if the specified mode can/should be used */ 367 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode); 368 /* Switch the PHY into various modes */ 369 void (*set_mode)(struct axgbe_port *, enum axgbe_mode); 370 /* Retrieve mode needed for a specific speed */ 371 enum axgbe_mode (*get_mode)(struct axgbe_port *, int); 372 /* Retrieve new/next mode when trying to auto-negotiate */ 373 enum axgbe_mode (*switch_mode)(struct axgbe_port *); 374 /* Retrieve current mode */ 375 enum axgbe_mode (*cur_mode)(struct axgbe_port *); 376 377 /* Retrieve current auto-negotiation mode */ 378 enum axgbe_an_mode (*an_mode)(struct axgbe_port *); 379 380 /* Configure auto-negotiation settings */ 381 int (*an_config)(struct axgbe_port *); 382 383 /* Set/override auto-negotiation advertisement settings */ 384 unsigned int (*an_advertising)(struct axgbe_port *port); 385 386 /* Process results of auto-negotiation */ 387 enum axgbe_mode (*an_outcome)(struct axgbe_port *); 388 389 /* Pre/Post auto-negotiation support */ 390 void (*an_pre)(struct axgbe_port *port); 391 void (*an_post)(struct axgbe_port *port); 392 393 /* Pre/Post KR training enablement support */ 394 void (*kr_training_pre)(struct axgbe_port *); 395 void (*kr_training_post)(struct axgbe_port *); 396 }; 397 398 struct axgbe_phy_if { 399 /* For PHY setup/teardown */ 400 int (*phy_init)(struct axgbe_port *); 401 void (*phy_exit)(struct axgbe_port *); 402 403 /* For PHY support when setting device up/down */ 404 int (*phy_reset)(struct axgbe_port *); 405 int (*phy_start)(struct axgbe_port *); 406 void (*phy_stop)(struct axgbe_port *); 407 408 /* For PHY support while device is up */ 409 void (*phy_status)(struct axgbe_port *); 410 int (*phy_config_aneg)(struct axgbe_port *); 411 412 /* For PHY settings validation */ 413 int (*phy_valid_speed)(struct axgbe_port *, int); 414 /* For single interrupt support */ 415 void (*an_isr)(struct axgbe_port *); 416 /* PHY implementation specific services */ 417 struct axgbe_phy_impl_if phy_impl; 418 }; 419 420 struct axgbe_i2c_if { 421 /* For initial I2C setup */ 422 int (*i2c_init)(struct axgbe_port *); 423 424 /* For I2C support when setting device up/down */ 425 int (*i2c_start)(struct axgbe_port *); 426 void (*i2c_stop)(struct axgbe_port *); 427 428 /* For performing I2C operations */ 429 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *); 430 }; 431 432 /* This structure contains flags that indicate what hardware features 433 * or configurations are present in the device. 434 */ 435 struct axgbe_hw_features { 436 /* HW Version */ 437 unsigned int version; 438 439 /* HW Feature Register0 */ 440 unsigned int gmii; /* 1000 Mbps support */ 441 unsigned int vlhash; /* VLAN Hash Filter */ 442 unsigned int sma; /* SMA(MDIO) Interface */ 443 unsigned int rwk; /* PMT remote wake-up packet */ 444 unsigned int mgk; /* PMT magic packet */ 445 unsigned int mmc; /* RMON module */ 446 unsigned int aoe; /* ARP Offload */ 447 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 448 unsigned int eee; /* Energy Efficient Ethernet */ 449 unsigned int tx_coe; /* Tx Checksum Offload */ 450 unsigned int rx_coe; /* Rx Checksum Offload */ 451 unsigned int addn_mac; /* Additional MAC Addresses */ 452 unsigned int ts_src; /* Timestamp Source */ 453 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 454 455 /* HW Feature Register1 */ 456 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 457 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 458 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 459 unsigned int dma_width; /* DMA width */ 460 unsigned int dcb; /* DCB Feature */ 461 unsigned int sph; /* Split Header Feature */ 462 unsigned int tso; /* TCP Segmentation Offload */ 463 unsigned int dma_debug; /* DMA Debug Registers */ 464 unsigned int rss; /* Receive Side Scaling */ 465 unsigned int tc_cnt; /* Number of Traffic Classes */ 466 unsigned int hash_table_size; /* Hash Table Size */ 467 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 468 469 /* HW Feature Register2 */ 470 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 471 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 472 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 473 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 474 unsigned int pps_out_num; /* Number of PPS outputs */ 475 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 476 477 /* HW Feature Register3 */ 478 unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */ 479 /* insertion on Tx Enable */ 480 unsigned int no_of_vlan_extn; /* Number of Extended VLAN Tag */ 481 /* Filters Enabled */ 482 }; 483 484 struct axgbe_version_data { 485 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *); 486 enum axgbe_xpcs_access xpcs_access; 487 unsigned int mmc_64bit; 488 unsigned int tx_max_fifo_size; 489 unsigned int rx_max_fifo_size; 490 unsigned int tx_tstamp_workaround; 491 unsigned int ecc_support; 492 unsigned int i2c_support; 493 unsigned int an_cdr_workaround; 494 unsigned int enable_rrc; 495 }; 496 497 struct axgbe_mmc_stats { 498 /* Tx Stats */ 499 uint64_t txoctetcount_gb; 500 uint64_t txframecount_gb; 501 uint64_t txbroadcastframes_g; 502 uint64_t txmulticastframes_g; 503 uint64_t tx64octets_gb; 504 uint64_t tx65to127octets_gb; 505 uint64_t tx128to255octets_gb; 506 uint64_t tx256to511octets_gb; 507 uint64_t tx512to1023octets_gb; 508 uint64_t tx1024tomaxoctets_gb; 509 uint64_t txunicastframes_gb; 510 uint64_t txmulticastframes_gb; 511 uint64_t txbroadcastframes_gb; 512 uint64_t txunderflowerror; 513 uint64_t txoctetcount_g; 514 uint64_t txframecount_g; 515 uint64_t txpauseframes; 516 uint64_t txvlanframes_g; 517 518 /* Rx Stats */ 519 uint64_t rxframecount_gb; 520 uint64_t rxoctetcount_gb; 521 uint64_t rxoctetcount_g; 522 uint64_t rxbroadcastframes_g; 523 uint64_t rxmulticastframes_g; 524 uint64_t rxcrcerror; 525 uint64_t rxrunterror; 526 uint64_t rxjabbererror; 527 uint64_t rxundersize_g; 528 uint64_t rxoversize_g; 529 uint64_t rx64octets_gb; 530 uint64_t rx65to127octets_gb; 531 uint64_t rx128to255octets_gb; 532 uint64_t rx256to511octets_gb; 533 uint64_t rx512to1023octets_gb; 534 uint64_t rx1024tomaxoctets_gb; 535 uint64_t rxunicastframes_g; 536 uint64_t rxlengtherror; 537 uint64_t rxoutofrangetype; 538 uint64_t rxpauseframes; 539 uint64_t rxfifooverflow; 540 uint64_t rxvlanframes_gb; 541 uint64_t rxwatchdogerror; 542 }; 543 544 /* Flow control parameters */ 545 struct xgbe_fc_info { 546 uint32_t high_water[AXGBE_PRIORITY_QUEUES]; 547 uint32_t low_water[AXGBE_PRIORITY_QUEUES]; 548 uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; 549 uint16_t send_xon; 550 enum rte_eth_fc_mode mode; 551 uint8_t autoneg; 552 }; 553 554 /* 555 * Structure to store private data for each port. 556 */ 557 struct axgbe_port { 558 /* Ethdev where port belongs*/ 559 struct rte_eth_dev *eth_dev; 560 /* Pci dev info */ 561 const struct rte_pci_device *pci_dev; 562 /* Version related data */ 563 struct axgbe_version_data *vdata; 564 565 /* AXGMAC/XPCS related mmio registers */ 566 void *xgmac_regs; /* AXGMAC CSRs */ 567 void *xpcs_regs; /* XPCS MMD registers */ 568 void *xprop_regs; /* AXGBE property registers */ 569 void *xi2c_regs; /* AXGBE I2C CSRs */ 570 571 /* Port property registers */ 572 unsigned int pp0; 573 unsigned int pp1; 574 unsigned int pp2; 575 unsigned int pp3; 576 unsigned int pp4; 577 578 bool cdr_track_early; 579 /* XPCS indirect addressing lock */ 580 unsigned int xpcs_window_def_reg; 581 unsigned int xpcs_window_sel_reg; 582 unsigned int xpcs_window; 583 unsigned int xpcs_window_size; 584 unsigned int xpcs_window_mask; 585 586 /* Flags representing axgbe_state */ 587 uint32_t dev_state; 588 589 struct axgbe_hw_if hw_if; 590 struct axgbe_phy_if phy_if; 591 struct axgbe_i2c_if i2c_if; 592 593 /* AXI DMA settings */ 594 unsigned int coherent; 595 unsigned int axdomain; 596 unsigned int arcache; 597 unsigned int awcache; 598 599 unsigned int tx_max_channel_count; 600 unsigned int rx_max_channel_count; 601 unsigned int channel_count; 602 unsigned int tx_ring_count; 603 unsigned int tx_desc_count; 604 unsigned int rx_ring_count; 605 unsigned int rx_desc_count; 606 607 unsigned int tx_max_q_count; 608 unsigned int rx_max_q_count; 609 unsigned int tx_q_count; 610 unsigned int rx_q_count; 611 612 /* Tx/Rx common settings */ 613 unsigned int pblx8; 614 615 /* Tx settings */ 616 unsigned int tx_sf_mode; 617 unsigned int tx_threshold; 618 unsigned int tx_pbl; 619 unsigned int tx_osp_mode; 620 unsigned int tx_max_fifo_size; 621 unsigned int multi_segs_tx; 622 623 /* Rx settings */ 624 unsigned int rx_sf_mode; 625 unsigned int rx_threshold; 626 unsigned int rx_pbl; 627 unsigned int rx_max_fifo_size; 628 unsigned int rx_buf_size; 629 630 /* Device clocks */ 631 unsigned long sysclk_rate; 632 unsigned long ptpclk_rate; 633 634 /* Keeps track of power mode */ 635 unsigned int power_down; 636 637 /* Current PHY settings */ 638 int phy_link; 639 int phy_speed; 640 641 pthread_mutex_t xpcs_mutex; 642 pthread_mutex_t i2c_mutex; 643 pthread_mutex_t an_mutex; 644 pthread_mutex_t phy_mutex; 645 646 /* Flow control settings */ 647 unsigned int pause_autoneg; 648 unsigned int tx_pause; 649 unsigned int rx_pause; 650 unsigned int rx_rfa[AXGBE_MAX_QUEUES]; 651 unsigned int rx_rfd[AXGBE_MAX_QUEUES]; 652 unsigned int fifo; 653 unsigned int pfc_map[AXGBE_MAX_QUEUES]; 654 655 /* Receive Side Scaling settings */ 656 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; 657 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; 658 uint32_t rss_options; 659 int rss_enable; 660 uint64_t rss_hf; 661 662 /* Hardware features of the device */ 663 struct axgbe_hw_features hw_feat; 664 665 struct rte_ether_addr mac_addr; 666 667 /* Software Tx/Rx structure pointers*/ 668 void **rx_queues; 669 void **tx_queues; 670 671 /* MDIO/PHY related settings */ 672 unsigned int phy_started; 673 void *phy_data; 674 struct axgbe_phy phy; 675 int mdio_mmd; 676 unsigned long link_check; 677 volatile int mdio_completion; 678 679 unsigned int kr_redrv; 680 681 /* Auto-negotiation state machine support */ 682 unsigned int an_int; 683 unsigned int an_status; 684 enum axgbe_an an_result; 685 enum axgbe_an an_state; 686 enum axgbe_rx kr_state; 687 enum axgbe_rx kx_state; 688 unsigned int an_again; 689 unsigned int an_supported; 690 unsigned int parallel_detect; 691 unsigned int fec_ability; 692 unsigned long an_start; 693 unsigned long kr_start_time; 694 enum axgbe_an_mode an_mode; 695 696 /* I2C support */ 697 struct axgbe_i2c i2c; 698 volatile int i2c_complete; 699 700 /* CRC stripping by H/w for Rx packet*/ 701 int crc_strip_enable; 702 /* csum enable to hardware */ 703 uint32_t rx_csum_enable; 704 705 struct axgbe_mmc_stats mmc_stats; 706 struct xgbe_fc_info fc; 707 708 /* Hash filtering */ 709 unsigned int hash_table_shift; 710 unsigned int hash_table_count; 711 unsigned int uc_hash_mac_addr; 712 unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; 713 714 /* Filtering support */ 715 unsigned long active_vlans[VLAN_TABLE_SIZE]; 716 717 /* For IEEE1588 PTP */ 718 struct rte_timecounter systime_tc; 719 struct rte_timecounter tx_tstamp; 720 unsigned int tstamp_addend; 721 722 }; 723 724 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); 725 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if); 726 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); 727 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); 728 void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, 729 uint32_t index); 730 void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); 731 int axgbe_write_rss_lookup_table(struct axgbe_port *pdata); 732 int axgbe_write_rss_hash_key(struct axgbe_port *pdata); 733 734 #endif /* RTE_ETH_AXGBE_H_ */ 735