1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2017 Intel Corporation 3 */ 4 5 #include <inttypes.h> 6 #include <stdlib.h> 7 #include <string.h> 8 9 #include <bus_vdev_driver.h> 10 #include <rte_kvargs.h> 11 #include <rte_ring.h> 12 #include <rte_errno.h> 13 #include <rte_event_ring.h> 14 #include <rte_service_component.h> 15 16 #include "sw_evdev.h" 17 #include "iq_chunk.h" 18 #include "event_ring.h" 19 20 #define EVENTDEV_NAME_SW_PMD event_sw 21 #define NUMA_NODE_ARG "numa_node" 22 #define SCHED_QUANTA_ARG "sched_quanta" 23 #define CREDIT_QUANTA_ARG "credit_quanta" 24 #define MIN_BURST_SIZE_ARG "min_burst" 25 #define DEQ_BURST_SIZE_ARG "deq_burst" 26 #define REFIL_ONCE_ARG "refill_once" 27 28 static void 29 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info); 30 31 static int 32 sw_port_link(struct rte_eventdev *dev, void *port, const uint8_t queues[], 33 const uint8_t priorities[], uint16_t num) 34 { 35 struct sw_port *p = port; 36 struct sw_evdev *sw = sw_pmd_priv(dev); 37 int i; 38 39 RTE_SET_USED(priorities); 40 for (i = 0; i < num; i++) { 41 struct sw_qid *q = &sw->qids[queues[i]]; 42 unsigned int j; 43 44 /* check for qid map overflow */ 45 if (q->cq_num_mapped_cqs >= RTE_DIM(q->cq_map)) { 46 rte_errno = EDQUOT; 47 break; 48 } 49 50 if (p->is_directed && p->num_qids_mapped > 0) { 51 rte_errno = EDQUOT; 52 break; 53 } 54 55 for (j = 0; j < q->cq_num_mapped_cqs; j++) { 56 if (q->cq_map[j] == p->id) 57 break; 58 } 59 60 /* check if port is already linked */ 61 if (j < q->cq_num_mapped_cqs) 62 continue; 63 64 if (q->type == SW_SCHED_TYPE_DIRECT) { 65 /* check directed qids only map to one port */ 66 if (p->num_qids_mapped > 0) { 67 rte_errno = EDQUOT; 68 break; 69 } 70 /* check port only takes a directed flow */ 71 if (num > 1) { 72 rte_errno = EDQUOT; 73 break; 74 } 75 76 p->is_directed = 1; 77 p->num_qids_mapped = 1; 78 } else if (q->type == RTE_SCHED_TYPE_ORDERED) { 79 p->num_ordered_qids++; 80 p->num_qids_mapped++; 81 } else if (q->type == RTE_SCHED_TYPE_ATOMIC || 82 q->type == RTE_SCHED_TYPE_PARALLEL) { 83 p->num_qids_mapped++; 84 } 85 86 q->cq_map[q->cq_num_mapped_cqs] = p->id; 87 rte_smp_wmb(); 88 q->cq_num_mapped_cqs++; 89 } 90 return i; 91 } 92 93 static int 94 sw_port_unlink(struct rte_eventdev *dev, void *port, uint8_t queues[], 95 uint16_t nb_unlinks) 96 { 97 struct sw_port *p = port; 98 struct sw_evdev *sw = sw_pmd_priv(dev); 99 unsigned int i, j; 100 101 int unlinked = 0; 102 for (i = 0; i < nb_unlinks; i++) { 103 struct sw_qid *q = &sw->qids[queues[i]]; 104 for (j = 0; j < q->cq_num_mapped_cqs; j++) { 105 if (q->cq_map[j] == p->id) { 106 q->cq_map[j] = 107 q->cq_map[q->cq_num_mapped_cqs - 1]; 108 rte_smp_wmb(); 109 q->cq_num_mapped_cqs--; 110 unlinked++; 111 112 p->num_qids_mapped--; 113 114 if (q->type == RTE_SCHED_TYPE_ORDERED) 115 p->num_ordered_qids--; 116 117 continue; 118 } 119 } 120 } 121 122 p->unlinks_in_progress += unlinked; 123 rte_smp_mb(); 124 125 return unlinked; 126 } 127 128 static int 129 sw_port_unlinks_in_progress(struct rte_eventdev *dev, void *port) 130 { 131 RTE_SET_USED(dev); 132 struct sw_port *p = port; 133 return p->unlinks_in_progress; 134 } 135 136 static int 137 sw_port_setup(struct rte_eventdev *dev, uint8_t port_id, 138 const struct rte_event_port_conf *conf) 139 { 140 struct sw_evdev *sw = sw_pmd_priv(dev); 141 struct sw_port *p = &sw->ports[port_id]; 142 char buf[RTE_RING_NAMESIZE]; 143 unsigned int i; 144 145 struct rte_event_dev_info info; 146 sw_info_get(dev, &info); 147 148 /* detect re-configuring and return credits to instance if needed */ 149 if (p->initialized) { 150 /* taking credits from pool is done one quanta at a time, and 151 * credits may be spend (counted in p->inflights) or still 152 * available in the port (p->inflight_credits). We must return 153 * the sum to no leak credits 154 */ 155 int possible_inflights = p->inflight_credits + p->inflights; 156 rte_atomic32_sub(&sw->inflights, possible_inflights); 157 } 158 159 *p = (struct sw_port){0}; /* zero entire structure */ 160 p->id = port_id; 161 p->sw = sw; 162 163 /* check to see if rings exists - port_setup() can be called multiple 164 * times legally (assuming device is stopped). If ring exists, free it 165 * to so it gets re-created with the correct size 166 */ 167 snprintf(buf, sizeof(buf), "sw%d_p%u_%s", dev->data->dev_id, 168 port_id, "rx_worker_ring"); 169 struct rte_event_ring *existing_ring = rte_event_ring_lookup(buf); 170 rte_event_ring_free(existing_ring); 171 172 p->rx_worker_ring = rte_event_ring_create(buf, MAX_SW_PROD_Q_DEPTH, 173 dev->data->socket_id, 174 RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ); 175 if (p->rx_worker_ring == NULL) { 176 SW_LOG_ERR("Error creating RX worker ring for port %d\n", 177 port_id); 178 return -1; 179 } 180 181 p->inflight_max = conf->new_event_threshold; 182 p->implicit_release = !(conf->event_port_cfg & 183 RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL); 184 185 /* check if ring exists, same as rx_worker above */ 186 snprintf(buf, sizeof(buf), "sw%d_p%u, %s", dev->data->dev_id, 187 port_id, "cq_worker_ring"); 188 existing_ring = rte_event_ring_lookup(buf); 189 rte_event_ring_free(existing_ring); 190 191 p->cq_worker_ring = rte_event_ring_create(buf, conf->dequeue_depth, 192 dev->data->socket_id, 193 RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ); 194 if (p->cq_worker_ring == NULL) { 195 rte_event_ring_free(p->rx_worker_ring); 196 SW_LOG_ERR("Error creating CQ worker ring for port %d\n", 197 port_id); 198 return -1; 199 } 200 sw->cq_ring_space[port_id] = conf->dequeue_depth; 201 202 /* set hist list contents to empty */ 203 for (i = 0; i < SW_PORT_HIST_LIST; i++) { 204 p->hist_list[i].fid = -1; 205 p->hist_list[i].qid = -1; 206 } 207 dev->data->ports[port_id] = p; 208 209 rte_smp_wmb(); 210 p->initialized = 1; 211 return 0; 212 } 213 214 static void 215 sw_port_release(void *port) 216 { 217 struct sw_port *p = (void *)port; 218 if (p == NULL) 219 return; 220 221 rte_event_ring_free(p->rx_worker_ring); 222 rte_event_ring_free(p->cq_worker_ring); 223 memset(p, 0, sizeof(*p)); 224 } 225 226 static int32_t 227 qid_init(struct sw_evdev *sw, unsigned int idx, int type, 228 const struct rte_event_queue_conf *queue_conf) 229 { 230 unsigned int i; 231 int dev_id = sw->data->dev_id; 232 int socket_id = sw->data->socket_id; 233 char buf[IQ_ROB_NAMESIZE]; 234 struct sw_qid *qid = &sw->qids[idx]; 235 236 /* Initialize the FID structures to no pinning (-1), and zero packets */ 237 const struct sw_fid_t fid = {.cq = -1, .pcount = 0}; 238 for (i = 0; i < RTE_DIM(qid->fids); i++) 239 qid->fids[i] = fid; 240 241 qid->id = idx; 242 qid->type = type; 243 qid->priority = queue_conf->priority; 244 245 if (qid->type == RTE_SCHED_TYPE_ORDERED) { 246 uint32_t window_size; 247 248 /* rte_ring and window_size_mask require window_size to 249 * be a power-of-2. 250 */ 251 window_size = rte_align32pow2( 252 queue_conf->nb_atomic_order_sequences); 253 254 qid->window_size = window_size - 1; 255 256 if (!window_size) { 257 SW_LOG_DBG( 258 "invalid reorder_window_size for ordered queue\n" 259 ); 260 goto cleanup; 261 } 262 263 snprintf(buf, sizeof(buf), "sw%d_iq_%d_rob", dev_id, i); 264 qid->reorder_buffer = rte_zmalloc_socket(buf, 265 window_size * sizeof(qid->reorder_buffer[0]), 266 0, socket_id); 267 if (!qid->reorder_buffer) { 268 SW_LOG_DBG("reorder_buffer malloc failed\n"); 269 goto cleanup; 270 } 271 272 memset(&qid->reorder_buffer[0], 273 0, 274 window_size * sizeof(qid->reorder_buffer[0])); 275 276 qid->reorder_buffer_freelist = rob_ring_create(window_size, 277 socket_id); 278 if (!qid->reorder_buffer_freelist) { 279 SW_LOG_DBG("freelist ring create failed"); 280 goto cleanup; 281 } 282 283 /* Populate the freelist with reorder buffer entries. Enqueue 284 * 'window_size - 1' entries because the rte_ring holds only 285 * that many. 286 */ 287 for (i = 0; i < window_size - 1; i++) { 288 if (rob_ring_enqueue(qid->reorder_buffer_freelist, 289 &qid->reorder_buffer[i]) != 1) 290 goto cleanup; 291 } 292 293 qid->reorder_buffer_index = 0; 294 qid->cq_next_tx = 0; 295 } 296 297 qid->initialized = 1; 298 299 return 0; 300 301 cleanup: 302 if (qid->reorder_buffer) { 303 rte_free(qid->reorder_buffer); 304 qid->reorder_buffer = NULL; 305 } 306 307 if (qid->reorder_buffer_freelist) { 308 rob_ring_free(qid->reorder_buffer_freelist); 309 qid->reorder_buffer_freelist = NULL; 310 } 311 312 return -EINVAL; 313 } 314 315 static void 316 sw_queue_release(struct rte_eventdev *dev, uint8_t id) 317 { 318 struct sw_evdev *sw = sw_pmd_priv(dev); 319 struct sw_qid *qid = &sw->qids[id]; 320 321 if (qid->type == RTE_SCHED_TYPE_ORDERED) { 322 rte_free(qid->reorder_buffer); 323 rob_ring_free(qid->reorder_buffer_freelist); 324 } 325 memset(qid, 0, sizeof(*qid)); 326 } 327 328 static int 329 sw_queue_setup(struct rte_eventdev *dev, uint8_t queue_id, 330 const struct rte_event_queue_conf *conf) 331 { 332 int type; 333 334 type = conf->schedule_type; 335 336 if (RTE_EVENT_QUEUE_CFG_SINGLE_LINK & conf->event_queue_cfg) { 337 type = SW_SCHED_TYPE_DIRECT; 338 } else if (RTE_EVENT_QUEUE_CFG_ALL_TYPES 339 & conf->event_queue_cfg) { 340 SW_LOG_ERR("QUEUE_CFG_ALL_TYPES not supported\n"); 341 return -ENOTSUP; 342 } 343 344 struct sw_evdev *sw = sw_pmd_priv(dev); 345 346 if (sw->qids[queue_id].initialized) 347 sw_queue_release(dev, queue_id); 348 349 return qid_init(sw, queue_id, type, conf); 350 } 351 352 static void 353 sw_init_qid_iqs(struct sw_evdev *sw) 354 { 355 int i, j; 356 357 /* Initialize the IQ memory of all configured qids */ 358 for (i = 0; i < RTE_EVENT_MAX_QUEUES_PER_DEV; i++) { 359 struct sw_qid *qid = &sw->qids[i]; 360 361 if (!qid->initialized) 362 continue; 363 364 for (j = 0; j < SW_IQS_MAX; j++) 365 iq_init(sw, &qid->iq[j]); 366 } 367 } 368 369 static int 370 sw_qids_empty(struct sw_evdev *sw) 371 { 372 unsigned int i, j; 373 374 for (i = 0; i < sw->qid_count; i++) { 375 for (j = 0; j < SW_IQS_MAX; j++) { 376 if (iq_count(&sw->qids[i].iq[j])) 377 return 0; 378 } 379 } 380 381 return 1; 382 } 383 384 static int 385 sw_ports_empty(struct sw_evdev *sw) 386 { 387 unsigned int i; 388 389 for (i = 0; i < sw->port_count; i++) { 390 if ((rte_event_ring_count(sw->ports[i].rx_worker_ring)) || 391 rte_event_ring_count(sw->ports[i].cq_worker_ring)) 392 return 0; 393 } 394 395 return 1; 396 } 397 398 static void 399 sw_drain_ports(struct rte_eventdev *dev) 400 { 401 struct sw_evdev *sw = sw_pmd_priv(dev); 402 eventdev_stop_flush_t flush; 403 unsigned int i; 404 uint8_t dev_id; 405 void *arg; 406 407 flush = dev->dev_ops->dev_stop_flush; 408 dev_id = dev->data->dev_id; 409 arg = dev->data->dev_stop_flush_arg; 410 411 for (i = 0; i < sw->port_count; i++) { 412 struct rte_event ev; 413 414 while (rte_event_dequeue_burst(dev_id, i, &ev, 1, 0)) { 415 if (flush) 416 flush(dev_id, ev, arg); 417 418 ev.op = RTE_EVENT_OP_RELEASE; 419 rte_event_enqueue_burst(dev_id, i, &ev, 1); 420 } 421 } 422 } 423 424 static void 425 sw_drain_queue(struct rte_eventdev *dev, struct sw_iq *iq) 426 { 427 struct sw_evdev *sw = sw_pmd_priv(dev); 428 eventdev_stop_flush_t flush; 429 uint8_t dev_id; 430 void *arg; 431 432 flush = dev->dev_ops->dev_stop_flush; 433 dev_id = dev->data->dev_id; 434 arg = dev->data->dev_stop_flush_arg; 435 436 while (iq_count(iq) > 0) { 437 struct rte_event ev; 438 439 iq_dequeue_burst(sw, iq, &ev, 1); 440 441 if (flush) 442 flush(dev_id, ev, arg); 443 } 444 } 445 446 static void 447 sw_drain_queues(struct rte_eventdev *dev) 448 { 449 struct sw_evdev *sw = sw_pmd_priv(dev); 450 unsigned int i, j; 451 452 for (i = 0; i < sw->qid_count; i++) { 453 for (j = 0; j < SW_IQS_MAX; j++) 454 sw_drain_queue(dev, &sw->qids[i].iq[j]); 455 } 456 } 457 458 static void 459 sw_clean_qid_iqs(struct rte_eventdev *dev) 460 { 461 struct sw_evdev *sw = sw_pmd_priv(dev); 462 int i, j; 463 464 /* Release the IQ memory of all configured qids */ 465 for (i = 0; i < RTE_EVENT_MAX_QUEUES_PER_DEV; i++) { 466 struct sw_qid *qid = &sw->qids[i]; 467 468 for (j = 0; j < SW_IQS_MAX; j++) { 469 if (!qid->iq[j].head) 470 continue; 471 iq_free_chunk_list(sw, qid->iq[j].head); 472 qid->iq[j].head = NULL; 473 } 474 } 475 } 476 477 static void 478 sw_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id, 479 struct rte_event_queue_conf *conf) 480 { 481 RTE_SET_USED(dev); 482 RTE_SET_USED(queue_id); 483 484 static const struct rte_event_queue_conf default_conf = { 485 .nb_atomic_flows = 4096, 486 .nb_atomic_order_sequences = 1, 487 .schedule_type = RTE_SCHED_TYPE_ATOMIC, 488 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 489 }; 490 491 *conf = default_conf; 492 } 493 494 static void 495 sw_port_def_conf(struct rte_eventdev *dev, uint8_t port_id, 496 struct rte_event_port_conf *port_conf) 497 { 498 RTE_SET_USED(dev); 499 RTE_SET_USED(port_id); 500 501 port_conf->new_event_threshold = 1024; 502 port_conf->dequeue_depth = 16; 503 port_conf->enqueue_depth = 16; 504 port_conf->event_port_cfg = 0; 505 } 506 507 static int 508 sw_dev_configure(const struct rte_eventdev *dev) 509 { 510 struct sw_evdev *sw = sw_pmd_priv(dev); 511 const struct rte_eventdev_data *data = dev->data; 512 const struct rte_event_dev_config *conf = &data->dev_conf; 513 int num_chunks, i; 514 515 sw->qid_count = conf->nb_event_queues; 516 sw->port_count = conf->nb_event_ports; 517 sw->nb_events_limit = conf->nb_events_limit; 518 rte_atomic32_set(&sw->inflights, 0); 519 520 /* Number of chunks sized for worst-case spread of events across IQs */ 521 num_chunks = ((SW_INFLIGHT_EVENTS_TOTAL/SW_EVS_PER_Q_CHUNK)+1) + 522 sw->qid_count*SW_IQS_MAX*2; 523 524 /* If this is a reconfiguration, free the previous IQ allocation. All 525 * IQ chunk references were cleaned out of the QIDs in sw_stop(), and 526 * will be reinitialized in sw_start(). 527 */ 528 rte_free(sw->chunks); 529 530 sw->chunks = rte_malloc_socket(NULL, 531 sizeof(struct sw_queue_chunk) * 532 num_chunks, 533 0, 534 sw->data->socket_id); 535 if (!sw->chunks) 536 return -ENOMEM; 537 538 sw->chunk_list_head = NULL; 539 for (i = 0; i < num_chunks; i++) 540 iq_free_chunk(sw, &sw->chunks[i]); 541 542 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) 543 return -ENOTSUP; 544 545 return 0; 546 } 547 548 struct rte_eth_dev; 549 550 static int 551 sw_eth_rx_adapter_caps_get(const struct rte_eventdev *dev, 552 const struct rte_eth_dev *eth_dev, 553 uint32_t *caps) 554 { 555 RTE_SET_USED(dev); 556 RTE_SET_USED(eth_dev); 557 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP; 558 return 0; 559 } 560 561 static int 562 sw_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags, 563 uint32_t *caps, 564 const struct event_timer_adapter_ops **ops) 565 { 566 RTE_SET_USED(dev); 567 RTE_SET_USED(flags); 568 *caps = RTE_EVENT_TIMER_ADAPTER_SW_CAP; 569 570 /* Use default SW ops */ 571 *ops = NULL; 572 573 return 0; 574 } 575 576 static int 577 sw_crypto_adapter_caps_get(const struct rte_eventdev *dev, 578 const struct rte_cryptodev *cdev, 579 uint32_t *caps) 580 { 581 RTE_SET_USED(dev); 582 RTE_SET_USED(cdev); 583 *caps = RTE_EVENT_CRYPTO_ADAPTER_SW_CAP; 584 return 0; 585 } 586 587 static void 588 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info) 589 { 590 RTE_SET_USED(dev); 591 592 static const struct rte_event_dev_info evdev_sw_info = { 593 .driver_name = SW_PMD_NAME, 594 .max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV, 595 .max_event_queue_flows = SW_QID_NUM_FIDS, 596 .max_event_queue_priority_levels = SW_Q_PRIORITY_MAX, 597 .max_event_priority_levels = SW_IQS_MAX, 598 .max_event_ports = SW_PORTS_MAX, 599 .max_event_port_dequeue_depth = MAX_SW_CONS_Q_DEPTH, 600 .max_event_port_enqueue_depth = MAX_SW_PROD_Q_DEPTH, 601 .max_num_events = SW_INFLIGHT_EVENTS_TOTAL, 602 .event_dev_cap = ( 603 RTE_EVENT_DEV_CAP_ATOMIC | 604 RTE_EVENT_DEV_CAP_ORDERED | 605 RTE_EVENT_DEV_CAP_PARALLEL | 606 RTE_EVENT_DEV_CAP_QUEUE_QOS | 607 RTE_EVENT_DEV_CAP_BURST_MODE | 608 RTE_EVENT_DEV_CAP_EVENT_QOS | 609 RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE| 610 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK | 611 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT | 612 RTE_EVENT_DEV_CAP_NONSEQ_MODE | 613 RTE_EVENT_DEV_CAP_CARRY_FLOW_ID | 614 RTE_EVENT_DEV_CAP_MAINTENANCE_FREE), 615 .max_profiles_per_port = 1, 616 }; 617 618 *info = evdev_sw_info; 619 } 620 621 static void 622 sw_dump(struct rte_eventdev *dev, FILE *f) 623 { 624 const struct sw_evdev *sw = sw_pmd_priv(dev); 625 626 static const char * const q_type_strings[] = { 627 "Ordered", "Atomic", "Parallel", "Directed" 628 }; 629 uint32_t i; 630 fprintf(f, "EventDev %s: ports %d, qids %d\n", 631 dev->data->name, sw->port_count, sw->qid_count); 632 633 fprintf(f, "\trx %"PRIu64"\n\tdrop %"PRIu64"\n\ttx %"PRIu64"\n", 634 sw->stats.rx_pkts, sw->stats.rx_dropped, sw->stats.tx_pkts); 635 fprintf(f, "\tsched calls: %"PRIu64"\n", sw->sched_called); 636 fprintf(f, "\tsched cq/qid call: %"PRIu64"\n", sw->sched_cq_qid_called); 637 fprintf(f, "\tsched no IQ enq: %"PRIu64"\n", sw->sched_no_iq_enqueues); 638 fprintf(f, "\tsched no CQ enq: %"PRIu64"\n", sw->sched_no_cq_enqueues); 639 uint32_t inflights = rte_atomic32_read(&sw->inflights); 640 uint32_t credits = sw->nb_events_limit - inflights; 641 fprintf(f, "\tinflight %d, credits: %d\n", inflights, credits); 642 643 #define COL_RED "\x1b[31m" 644 #define COL_RESET "\x1b[0m" 645 646 for (i = 0; i < sw->port_count; i++) { 647 int max, j; 648 const struct sw_port *p = &sw->ports[i]; 649 if (!p->initialized) { 650 fprintf(f, " %sPort %d not initialized.%s\n", 651 COL_RED, i, COL_RESET); 652 continue; 653 } 654 fprintf(f, " Port %d %s\n", i, 655 p->is_directed ? " (SingleCons)" : ""); 656 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64 657 "\t%sinflight %d%s\n", sw->ports[i].stats.rx_pkts, 658 sw->ports[i].stats.rx_dropped, 659 sw->ports[i].stats.tx_pkts, 660 (p->inflights == p->inflight_max) ? 661 COL_RED : COL_RESET, 662 sw->ports[i].inflights, COL_RESET); 663 664 fprintf(f, "\tMax New: %u" 665 "\tAvg cycles PP: %"PRIu64"\tCredits: %u\n", 666 sw->ports[i].inflight_max, 667 sw->ports[i].avg_pkt_ticks, 668 sw->ports[i].inflight_credits); 669 fprintf(f, "\tReceive burst distribution:\n"); 670 float zp_percent = p->zero_polls * 100.0 / p->total_polls; 671 fprintf(f, zp_percent < 10 ? "\t\t0:%.02f%% " : "\t\t0:%.0f%% ", 672 zp_percent); 673 for (max = (int)RTE_DIM(p->poll_buckets); max-- > 0;) 674 if (p->poll_buckets[max] != 0) 675 break; 676 for (j = 0; j <= max; j++) { 677 if (p->poll_buckets[j] != 0) { 678 float poll_pc = p->poll_buckets[j] * 100.0 / 679 p->total_polls; 680 fprintf(f, "%u-%u:%.02f%% ", 681 ((j << SW_DEQ_STAT_BUCKET_SHIFT) + 1), 682 ((j+1) << SW_DEQ_STAT_BUCKET_SHIFT), 683 poll_pc); 684 } 685 } 686 fprintf(f, "\n"); 687 688 if (p->rx_worker_ring) { 689 uint64_t used = rte_event_ring_count(p->rx_worker_ring); 690 uint64_t space = rte_event_ring_free_count( 691 p->rx_worker_ring); 692 const char *col = (space == 0) ? COL_RED : COL_RESET; 693 fprintf(f, "\t%srx ring used: %4"PRIu64"\tfree: %4" 694 PRIu64 COL_RESET"\n", col, used, space); 695 } else 696 fprintf(f, "\trx ring not initialized.\n"); 697 698 if (p->cq_worker_ring) { 699 uint64_t used = rte_event_ring_count(p->cq_worker_ring); 700 uint64_t space = rte_event_ring_free_count( 701 p->cq_worker_ring); 702 const char *col = (space == 0) ? COL_RED : COL_RESET; 703 fprintf(f, "\t%scq ring used: %4"PRIu64"\tfree: %4" 704 PRIu64 COL_RESET"\n", col, used, space); 705 } else 706 fprintf(f, "\tcq ring not initialized.\n"); 707 } 708 709 for (i = 0; i < sw->qid_count; i++) { 710 const struct sw_qid *qid = &sw->qids[i]; 711 if (!qid->initialized) { 712 fprintf(f, " %sQueue %d not initialized.%s\n", 713 COL_RED, i, COL_RESET); 714 continue; 715 } 716 int affinities_per_port[SW_PORTS_MAX] = {0}; 717 718 fprintf(f, " Queue %d (%s)\n", i, q_type_strings[qid->type]); 719 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64"\n", 720 qid->stats.rx_pkts, qid->stats.rx_dropped, 721 qid->stats.tx_pkts); 722 if (qid->type == RTE_SCHED_TYPE_ORDERED) { 723 struct rob_ring *rob_buf_free = 724 qid->reorder_buffer_freelist; 725 if (rob_buf_free) 726 fprintf(f, "\tReorder entries in use: %u\n", 727 rob_ring_free_count(rob_buf_free)); 728 else 729 fprintf(f, 730 "\tReorder buffer not initialized\n"); 731 } 732 733 uint32_t flow; 734 for (flow = 0; flow < RTE_DIM(qid->fids); flow++) 735 if (qid->fids[flow].cq != -1) { 736 affinities_per_port[qid->fids[flow].cq]++; 737 } 738 739 uint32_t port; 740 fprintf(f, "\tPer Port Stats:\n"); 741 for (port = 0; port < sw->port_count; port++) { 742 fprintf(f, "\t Port %d: Pkts: %"PRIu64, port, 743 qid->to_port[port]); 744 fprintf(f, "\tFlows: %d\n", affinities_per_port[port]); 745 } 746 747 uint32_t iq; 748 uint32_t iq_printed = 0; 749 for (iq = 0; iq < SW_IQS_MAX; iq++) { 750 if (!qid->iq[iq].head) { 751 fprintf(f, "\tiq %d is not initialized.\n", iq); 752 iq_printed = 1; 753 continue; 754 } 755 uint32_t used = iq_count(&qid->iq[iq]); 756 const char *col = COL_RESET; 757 if (used > 0) { 758 fprintf(f, "\t%siq %d: Used %d" 759 COL_RESET"\n", col, iq, used); 760 iq_printed = 1; 761 } 762 } 763 if (iq_printed == 0) 764 fprintf(f, "\t-- iqs empty --\n"); 765 } 766 } 767 768 static int 769 sw_start(struct rte_eventdev *dev) 770 { 771 unsigned int i, j; 772 struct sw_evdev *sw = sw_pmd_priv(dev); 773 774 rte_service_component_runstate_set(sw->service_id, 1); 775 776 /* check a service core is mapped to this service */ 777 if (!rte_service_runstate_get(sw->service_id)) { 778 SW_LOG_ERR("Warning: No Service core enabled on service %s\n", 779 sw->service_name); 780 return -ENOENT; 781 } 782 783 /* check all ports are set up */ 784 for (i = 0; i < sw->port_count; i++) 785 if (sw->ports[i].rx_worker_ring == NULL) { 786 SW_LOG_ERR("Port %d not configured\n", i); 787 return -ESTALE; 788 } 789 790 /* check all queues are configured and mapped to ports*/ 791 for (i = 0; i < sw->qid_count; i++) 792 if (!sw->qids[i].initialized || 793 sw->qids[i].cq_num_mapped_cqs == 0) { 794 SW_LOG_ERR("Queue %d not configured\n", i); 795 return -ENOLINK; 796 } 797 798 /* build up our prioritized array of qids */ 799 /* We don't use qsort here, as if all/multiple entries have the same 800 * priority, the result is non-deterministic. From "man 3 qsort": 801 * "If two members compare as equal, their order in the sorted 802 * array is undefined." 803 */ 804 uint32_t qidx = 0; 805 for (j = 0; j <= RTE_EVENT_DEV_PRIORITY_LOWEST; j++) { 806 for (i = 0; i < sw->qid_count; i++) { 807 if (sw->qids[i].priority == j) { 808 sw->qids_prioritized[qidx] = &sw->qids[i]; 809 qidx++; 810 } 811 } 812 } 813 814 sw_init_qid_iqs(sw); 815 816 if (sw_xstats_init(sw) < 0) 817 return -EINVAL; 818 819 rte_smp_wmb(); 820 sw->started = 1; 821 822 return 0; 823 } 824 825 static void 826 sw_stop(struct rte_eventdev *dev) 827 { 828 struct sw_evdev *sw = sw_pmd_priv(dev); 829 int32_t runstate; 830 831 /* Stop the scheduler if it's running */ 832 runstate = rte_service_runstate_get(sw->service_id); 833 if (runstate == 1) 834 rte_service_runstate_set(sw->service_id, 0); 835 836 while (rte_service_may_be_active(sw->service_id)) 837 rte_pause(); 838 839 /* Flush all events out of the device */ 840 while (!(sw_qids_empty(sw) && sw_ports_empty(sw))) { 841 sw_event_schedule(dev); 842 sw_drain_ports(dev); 843 sw_drain_queues(dev); 844 } 845 846 sw_clean_qid_iqs(dev); 847 sw_xstats_uninit(sw); 848 sw->started = 0; 849 rte_smp_wmb(); 850 851 if (runstate == 1) 852 rte_service_runstate_set(sw->service_id, 1); 853 } 854 855 static int 856 sw_close(struct rte_eventdev *dev) 857 { 858 struct sw_evdev *sw = sw_pmd_priv(dev); 859 uint32_t i; 860 861 for (i = 0; i < sw->qid_count; i++) 862 sw_queue_release(dev, i); 863 sw->qid_count = 0; 864 865 for (i = 0; i < sw->port_count; i++) 866 sw_port_release(&sw->ports[i]); 867 sw->port_count = 0; 868 869 memset(&sw->stats, 0, sizeof(sw->stats)); 870 sw->sched_called = 0; 871 sw->sched_no_iq_enqueues = 0; 872 sw->sched_no_cq_enqueues = 0; 873 sw->sched_cq_qid_called = 0; 874 875 return 0; 876 } 877 878 static int 879 assign_numa_node(const char *key __rte_unused, const char *value, void *opaque) 880 { 881 int *socket_id = opaque; 882 *socket_id = atoi(value); 883 if (*socket_id >= RTE_MAX_NUMA_NODES) 884 return -1; 885 return 0; 886 } 887 888 static int 889 set_sched_quanta(const char *key __rte_unused, const char *value, void *opaque) 890 { 891 int *quanta = opaque; 892 *quanta = atoi(value); 893 if (*quanta < 0 || *quanta >= 4096) 894 return -1; 895 return 0; 896 } 897 898 static int 899 set_credit_quanta(const char *key __rte_unused, const char *value, void *opaque) 900 { 901 int *credit = opaque; 902 *credit = atoi(value); 903 if (*credit < 0 || *credit >= 128) 904 return -1; 905 return 0; 906 } 907 908 static int 909 set_deq_burst_sz(const char *key __rte_unused, const char *value, void *opaque) 910 { 911 int *deq_burst_sz = opaque; 912 *deq_burst_sz = atoi(value); 913 if (*deq_burst_sz < 0 || *deq_burst_sz > SCHED_DEQUEUE_MAX_BURST_SIZE) 914 return -1; 915 return 0; 916 } 917 918 static int 919 set_min_burst_sz(const char *key __rte_unused, const char *value, void *opaque) 920 { 921 int *min_burst_sz = opaque; 922 *min_burst_sz = atoi(value); 923 if (*min_burst_sz < 0 || *min_burst_sz > SCHED_DEQUEUE_MAX_BURST_SIZE) 924 return -1; 925 return 0; 926 } 927 928 static int 929 set_refill_once(const char *key __rte_unused, const char *value, void *opaque) 930 { 931 int *refill_once_per_call = opaque; 932 *refill_once_per_call = atoi(value); 933 if (*refill_once_per_call < 0 || *refill_once_per_call > 1) 934 return -1; 935 return 0; 936 } 937 938 static int32_t sw_sched_service_func(void *args) 939 { 940 struct rte_eventdev *dev = args; 941 return sw_event_schedule(dev); 942 } 943 944 static int 945 sw_probe(struct rte_vdev_device *vdev) 946 { 947 static struct eventdev_ops evdev_sw_ops = { 948 .dev_configure = sw_dev_configure, 949 .dev_infos_get = sw_info_get, 950 .dev_close = sw_close, 951 .dev_start = sw_start, 952 .dev_stop = sw_stop, 953 .dump = sw_dump, 954 955 .queue_def_conf = sw_queue_def_conf, 956 .queue_setup = sw_queue_setup, 957 .queue_release = sw_queue_release, 958 .port_def_conf = sw_port_def_conf, 959 .port_setup = sw_port_setup, 960 .port_release = sw_port_release, 961 .port_link = sw_port_link, 962 .port_unlink = sw_port_unlink, 963 .port_unlinks_in_progress = sw_port_unlinks_in_progress, 964 965 .eth_rx_adapter_caps_get = sw_eth_rx_adapter_caps_get, 966 967 .timer_adapter_caps_get = sw_timer_adapter_caps_get, 968 969 .crypto_adapter_caps_get = sw_crypto_adapter_caps_get, 970 971 .xstats_get = sw_xstats_get, 972 .xstats_get_names = sw_xstats_get_names, 973 .xstats_get_by_name = sw_xstats_get_by_name, 974 .xstats_reset = sw_xstats_reset, 975 976 .dev_selftest = test_sw_eventdev, 977 }; 978 979 static const char *const args[] = { 980 NUMA_NODE_ARG, 981 SCHED_QUANTA_ARG, 982 CREDIT_QUANTA_ARG, 983 MIN_BURST_SIZE_ARG, 984 DEQ_BURST_SIZE_ARG, 985 REFIL_ONCE_ARG, 986 NULL 987 }; 988 const char *name; 989 const char *params; 990 struct rte_eventdev *dev; 991 struct sw_evdev *sw; 992 int socket_id = rte_socket_id(); 993 int sched_quanta = SW_DEFAULT_SCHED_QUANTA; 994 int credit_quanta = SW_DEFAULT_CREDIT_QUANTA; 995 int min_burst_size = 1; 996 int deq_burst_size = SCHED_DEQUEUE_DEFAULT_BURST_SIZE; 997 int refill_once = 0; 998 999 name = rte_vdev_device_name(vdev); 1000 params = rte_vdev_device_args(vdev); 1001 if (params != NULL && params[0] != '\0') { 1002 struct rte_kvargs *kvlist = rte_kvargs_parse(params, args); 1003 1004 if (!kvlist) { 1005 SW_LOG_INFO( 1006 "Ignoring unsupported parameters when creating device '%s'\n", 1007 name); 1008 } else { 1009 int ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG, 1010 assign_numa_node, &socket_id); 1011 if (ret != 0) { 1012 SW_LOG_ERR( 1013 "%s: Error parsing numa node parameter", 1014 name); 1015 rte_kvargs_free(kvlist); 1016 return ret; 1017 } 1018 1019 ret = rte_kvargs_process(kvlist, SCHED_QUANTA_ARG, 1020 set_sched_quanta, &sched_quanta); 1021 if (ret != 0) { 1022 SW_LOG_ERR( 1023 "%s: Error parsing sched quanta parameter", 1024 name); 1025 rte_kvargs_free(kvlist); 1026 return ret; 1027 } 1028 1029 ret = rte_kvargs_process(kvlist, CREDIT_QUANTA_ARG, 1030 set_credit_quanta, &credit_quanta); 1031 if (ret != 0) { 1032 SW_LOG_ERR( 1033 "%s: Error parsing credit quanta parameter", 1034 name); 1035 rte_kvargs_free(kvlist); 1036 return ret; 1037 } 1038 1039 ret = rte_kvargs_process(kvlist, MIN_BURST_SIZE_ARG, 1040 set_min_burst_sz, &min_burst_size); 1041 if (ret != 0) { 1042 SW_LOG_ERR( 1043 "%s: Error parsing minimum burst size parameter", 1044 name); 1045 rte_kvargs_free(kvlist); 1046 return ret; 1047 } 1048 1049 ret = rte_kvargs_process(kvlist, DEQ_BURST_SIZE_ARG, 1050 set_deq_burst_sz, &deq_burst_size); 1051 if (ret != 0) { 1052 SW_LOG_ERR( 1053 "%s: Error parsing dequeue burst size parameter", 1054 name); 1055 rte_kvargs_free(kvlist); 1056 return ret; 1057 } 1058 1059 ret = rte_kvargs_process(kvlist, REFIL_ONCE_ARG, 1060 set_refill_once, &refill_once); 1061 if (ret != 0) { 1062 SW_LOG_ERR( 1063 "%s: Error parsing refill once per call switch", 1064 name); 1065 rte_kvargs_free(kvlist); 1066 return ret; 1067 } 1068 1069 rte_kvargs_free(kvlist); 1070 } 1071 } 1072 1073 SW_LOG_INFO( 1074 "Creating eventdev sw device %s, numa_node=%d, " 1075 "sched_quanta=%d, credit_quanta=%d " 1076 "min_burst=%d, deq_burst=%d, refill_once=%d\n", 1077 name, socket_id, sched_quanta, credit_quanta, 1078 min_burst_size, deq_burst_size, refill_once); 1079 1080 dev = rte_event_pmd_vdev_init(name, 1081 sizeof(struct sw_evdev), socket_id, vdev); 1082 if (dev == NULL) { 1083 SW_LOG_ERR("eventdev vdev init() failed"); 1084 return -EFAULT; 1085 } 1086 dev->dev_ops = &evdev_sw_ops; 1087 dev->enqueue = sw_event_enqueue; 1088 dev->enqueue_burst = sw_event_enqueue_burst; 1089 dev->enqueue_new_burst = sw_event_enqueue_burst; 1090 dev->enqueue_forward_burst = sw_event_enqueue_burst; 1091 dev->dequeue = sw_event_dequeue; 1092 dev->dequeue_burst = sw_event_dequeue_burst; 1093 1094 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1095 return 0; 1096 1097 sw = dev->data->dev_private; 1098 sw->data = dev->data; 1099 1100 /* copy values passed from vdev command line to instance */ 1101 sw->credit_update_quanta = credit_quanta; 1102 sw->sched_quanta = sched_quanta; 1103 sw->sched_min_burst_size = min_burst_size; 1104 sw->sched_deq_burst_size = deq_burst_size; 1105 sw->refill_once_per_iter = refill_once; 1106 1107 /* register service with EAL */ 1108 struct rte_service_spec service; 1109 memset(&service, 0, sizeof(struct rte_service_spec)); 1110 snprintf(service.name, sizeof(service.name), "%s_service", name); 1111 snprintf(sw->service_name, sizeof(sw->service_name), "%s_service", 1112 name); 1113 service.socket_id = socket_id; 1114 service.callback = sw_sched_service_func; 1115 service.callback_userdata = (void *)dev; 1116 1117 int32_t ret = rte_service_component_register(&service, &sw->service_id); 1118 if (ret) { 1119 SW_LOG_ERR("service register() failed"); 1120 return -ENOEXEC; 1121 } 1122 1123 dev->data->service_inited = 1; 1124 dev->data->service_id = sw->service_id; 1125 1126 event_dev_probing_finish(dev); 1127 1128 return 0; 1129 } 1130 1131 static int 1132 sw_remove(struct rte_vdev_device *vdev) 1133 { 1134 const char *name; 1135 1136 name = rte_vdev_device_name(vdev); 1137 if (name == NULL) 1138 return -EINVAL; 1139 1140 SW_LOG_INFO("Closing eventdev sw device %s\n", name); 1141 1142 return rte_event_pmd_vdev_uninit(name); 1143 } 1144 1145 static struct rte_vdev_driver evdev_sw_pmd_drv = { 1146 .probe = sw_probe, 1147 .remove = sw_remove 1148 }; 1149 1150 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_SW_PMD, evdev_sw_pmd_drv); 1151 RTE_PMD_REGISTER_PARAM_STRING(event_sw, NUMA_NODE_ARG "=<int> " 1152 SCHED_QUANTA_ARG "=<int>" CREDIT_QUANTA_ARG "=<int>" 1153 MIN_BURST_SIZE_ARG "=<int>" DEQ_BURST_SIZE_ARG "=<int>" 1154 REFIL_ONCE_ARG "=<int>"); 1155 RTE_LOG_REGISTER_DEFAULT(eventdev_sw_log_level, NOTICE); 1156