xref: /dpdk/drivers/event/opdl/opdl_evdev.h (revision 27595cd83053b2d39634a159d6709b3ce3cdf3b0)
1e07a3ed7SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
2e07a3ed7SBruce Richardson  * Copyright(c) 2017 Intel Corporation
33c7f3dcfSLiang Ma  */
43c7f3dcfSLiang Ma 
53c7f3dcfSLiang Ma #ifndef _OPDL_EVDEV_H_
63c7f3dcfSLiang Ma #define _OPDL_EVDEV_H_
73c7f3dcfSLiang Ma 
83c7f3dcfSLiang Ma #include <rte_eventdev.h>
925187042SBruce Richardson #include <eventdev_pmd_vdev.h>
103c7f3dcfSLiang Ma #include <rte_atomic.h>
113c7f3dcfSLiang Ma #include "opdl_ring.h"
123c7f3dcfSLiang Ma 
133c7f3dcfSLiang Ma #define OPDL_QID_NUM_FIDS 1024
143c7f3dcfSLiang Ma #define OPDL_IQS_MAX 1
153c7f3dcfSLiang Ma #define OPDL_Q_PRIORITY_MAX 1
163c7f3dcfSLiang Ma #define OPDL_PORTS_MAX 64
173c7f3dcfSLiang Ma #define MAX_OPDL_CONS_Q_DEPTH 128
183c7f3dcfSLiang Ma /* OPDL size */
193c7f3dcfSLiang Ma #define OPDL_INFLIGHT_EVENTS_TOTAL 4096
203c7f3dcfSLiang Ma /* allow for lots of over-provisioning */
213c7f3dcfSLiang Ma #define OPDL_FRAGMENTS_MAX 1
223c7f3dcfSLiang Ma 
233c7f3dcfSLiang Ma /* report dequeue burst sizes in buckets */
243c7f3dcfSLiang Ma #define OPDL_DEQ_STAT_BUCKET_SHIFT 2
253c7f3dcfSLiang Ma /* how many packets pulled from port by sched */
263c7f3dcfSLiang Ma #define SCHED_DEQUEUE_BURST_SIZE 32
273c7f3dcfSLiang Ma 
283c7f3dcfSLiang Ma /* size of our history list */
293c7f3dcfSLiang Ma #define OPDL_PORT_HIST_LIST (MAX_OPDL_PROD_Q_DEPTH)
303c7f3dcfSLiang Ma 
313c7f3dcfSLiang Ma /* how many data points use for average stats */
323c7f3dcfSLiang Ma #define NUM_SAMPLES 64
333c7f3dcfSLiang Ma 
343c7f3dcfSLiang Ma #define EVENTDEV_NAME_OPDL_PMD event_opdl
353c7f3dcfSLiang Ma #define OPDL_PMD_NAME RTE_STR(event_opdl)
363c7f3dcfSLiang Ma #define OPDL_PMD_NAME_MAX 64
373c7f3dcfSLiang Ma 
383c7f3dcfSLiang Ma #define OPDL_INVALID_QID 255
393c7f3dcfSLiang Ma 
403c7f3dcfSLiang Ma #define OPDL_SCHED_TYPE_DIRECT (RTE_SCHED_TYPE_PARALLEL + 1)
413c7f3dcfSLiang Ma 
423c7f3dcfSLiang Ma #define OPDL_NUM_POLL_BUCKETS  \
433c7f3dcfSLiang Ma 	(MAX_OPDL_CONS_Q_DEPTH >> OPDL_DEQ_STAT_BUCKET_SHIFT)
443c7f3dcfSLiang Ma 
453c7f3dcfSLiang Ma enum {
463c7f3dcfSLiang Ma 	QE_FLAG_VALID_SHIFT = 0,
473c7f3dcfSLiang Ma 	QE_FLAG_COMPLETE_SHIFT,
483c7f3dcfSLiang Ma 	QE_FLAG_NOT_EOP_SHIFT,
493c7f3dcfSLiang Ma 	_QE_FLAG_COUNT
503c7f3dcfSLiang Ma };
513c7f3dcfSLiang Ma 
523c7f3dcfSLiang Ma enum port_type {
533c7f3dcfSLiang Ma 	OPDL_INVALID_PORT = 0,
543c7f3dcfSLiang Ma 	OPDL_REGULAR_PORT = 1,
553c7f3dcfSLiang Ma 	OPDL_PURE_RX_PORT,
563c7f3dcfSLiang Ma 	OPDL_PURE_TX_PORT,
573c7f3dcfSLiang Ma 	OPDL_ASYNC_PORT
583c7f3dcfSLiang Ma };
593c7f3dcfSLiang Ma 
603c7f3dcfSLiang Ma enum queue_type {
613c7f3dcfSLiang Ma 	OPDL_Q_TYPE_INVALID = 0,
623c7f3dcfSLiang Ma 	OPDL_Q_TYPE_SINGLE_LINK = 1,
633c7f3dcfSLiang Ma 	OPDL_Q_TYPE_ATOMIC,
643c7f3dcfSLiang Ma 	OPDL_Q_TYPE_ORDERED
653c7f3dcfSLiang Ma };
663c7f3dcfSLiang Ma 
673c7f3dcfSLiang Ma enum queue_pos {
683c7f3dcfSLiang Ma 	OPDL_Q_POS_START = 0,
693c7f3dcfSLiang Ma 	OPDL_Q_POS_MIDDLE,
703c7f3dcfSLiang Ma 	OPDL_Q_POS_END
713c7f3dcfSLiang Ma };
723c7f3dcfSLiang Ma 
733c7f3dcfSLiang Ma #define QE_FLAG_VALID    (1 << QE_FLAG_VALID_SHIFT)    /* for NEW FWD, FRAG */
743c7f3dcfSLiang Ma #define QE_FLAG_COMPLETE (1 << QE_FLAG_COMPLETE_SHIFT) /* set for FWD, DROP  */
753c7f3dcfSLiang Ma #define QE_FLAG_NOT_EOP  (1 << QE_FLAG_NOT_EOP_SHIFT)  /* set for FRAG only  */
763c7f3dcfSLiang Ma 
773c7f3dcfSLiang Ma static const uint8_t opdl_qe_flag_map[] = {
783c7f3dcfSLiang Ma 	QE_FLAG_VALID /* NEW Event */,
793c7f3dcfSLiang Ma 	QE_FLAG_VALID | QE_FLAG_COMPLETE /* FWD Event */,
803c7f3dcfSLiang Ma 	QE_FLAG_COMPLETE /* RELEASE Event */,
813c7f3dcfSLiang Ma 
823c7f3dcfSLiang Ma 	/* Values which can be used for future support for partial
833c7f3dcfSLiang Ma 	 * events, i.e. where one event comes back to the scheduler
843c7f3dcfSLiang Ma 	 * as multiple which need to be tracked together
853c7f3dcfSLiang Ma 	 */
863c7f3dcfSLiang Ma 	QE_FLAG_VALID | QE_FLAG_COMPLETE | QE_FLAG_NOT_EOP,
873c7f3dcfSLiang Ma };
883c7f3dcfSLiang Ma 
893c7f3dcfSLiang Ma 
903c7f3dcfSLiang Ma enum port_xstat_name {
913c7f3dcfSLiang Ma 	claim_pkts_requested = 0,
923c7f3dcfSLiang Ma 	claim_pkts_granted,
933c7f3dcfSLiang Ma 	claim_non_empty,
943c7f3dcfSLiang Ma 	claim_empty,
953c7f3dcfSLiang Ma 	total_cycles,
963c7f3dcfSLiang Ma 	max_num_port_xstat
973c7f3dcfSLiang Ma };
983c7f3dcfSLiang Ma 
993c7f3dcfSLiang Ma #define OPDL_MAX_PORT_XSTAT_NUM (OPDL_PORTS_MAX * max_num_port_xstat)
1003c7f3dcfSLiang Ma 
1013c7f3dcfSLiang Ma struct opdl_port;
1023c7f3dcfSLiang Ma 
1033c7f3dcfSLiang Ma typedef uint16_t (*opdl_enq_operation)(struct opdl_port *port,
1043c7f3dcfSLiang Ma 		const struct rte_event ev[],
1053c7f3dcfSLiang Ma 		uint16_t num);
1063c7f3dcfSLiang Ma 
1073c7f3dcfSLiang Ma typedef uint16_t (*opdl_deq_operation)(struct opdl_port *port,
1083c7f3dcfSLiang Ma 		struct rte_event ev[],
1093c7f3dcfSLiang Ma 		uint16_t num);
1103c7f3dcfSLiang Ma 
1113c7f3dcfSLiang Ma struct opdl_evdev;
1123c7f3dcfSLiang Ma 
1133c7f3dcfSLiang Ma struct opdl_stage_meta_data {
1143c7f3dcfSLiang Ma 	uint32_t num_claimed;	/* number of entries claimed by this stage */
1153c7f3dcfSLiang Ma 	uint32_t burst_sz;	/* Port claim burst size */
1163c7f3dcfSLiang Ma };
1173c7f3dcfSLiang Ma 
1183c7f3dcfSLiang Ma struct opdl_port {
1193c7f3dcfSLiang Ma 
1203c7f3dcfSLiang Ma 	/* back pointer */
1213c7f3dcfSLiang Ma 	struct opdl_evdev *opdl;
1223c7f3dcfSLiang Ma 
1233c7f3dcfSLiang Ma 	/* enq handler & stage instance */
1243c7f3dcfSLiang Ma 	opdl_enq_operation enq;
1253c7f3dcfSLiang Ma 	struct opdl_stage *enq_stage_inst;
1263c7f3dcfSLiang Ma 
1273c7f3dcfSLiang Ma 	/* deq handler & stage instance */
1283c7f3dcfSLiang Ma 	opdl_deq_operation deq;
1293c7f3dcfSLiang Ma 	struct opdl_stage *deq_stage_inst;
1303c7f3dcfSLiang Ma 
1313c7f3dcfSLiang Ma 	/* port id has correctly been set */
1323c7f3dcfSLiang Ma 	uint8_t configured;
1333c7f3dcfSLiang Ma 
1343c7f3dcfSLiang Ma 	/* set when the port is initialized */
1353c7f3dcfSLiang Ma 	uint8_t initialized;
1363c7f3dcfSLiang Ma 
1373c7f3dcfSLiang Ma 	/* A numeric ID for the port */
1383c7f3dcfSLiang Ma 	uint8_t id;
1393c7f3dcfSLiang Ma 
1403c7f3dcfSLiang Ma 	/* Space for claimed entries */
1413c7f3dcfSLiang Ma 	struct rte_event *entries[MAX_OPDL_CONS_Q_DEPTH];
1423c7f3dcfSLiang Ma 
1433c7f3dcfSLiang Ma 	/* RX/REGULAR/TX/ASYNC - determined on position in queue */
1443c7f3dcfSLiang Ma 	enum port_type p_type;
1453c7f3dcfSLiang Ma 
1463c7f3dcfSLiang Ma 	/* if the claim is static atomic type  */
1473c7f3dcfSLiang Ma 	bool atomic_claim;
1483c7f3dcfSLiang Ma 
1493c7f3dcfSLiang Ma 	/* Queue linked to this port - internal queue id*/
1503c7f3dcfSLiang Ma 	uint8_t queue_id;
1513c7f3dcfSLiang Ma 
1523c7f3dcfSLiang Ma 	/* Queue linked to this port - external queue id*/
1533c7f3dcfSLiang Ma 	uint8_t external_qid;
1543c7f3dcfSLiang Ma 
1553c7f3dcfSLiang Ma 	/* Next queue linked to this port - external queue id*/
1563c7f3dcfSLiang Ma 	uint8_t next_external_qid;
1573c7f3dcfSLiang Ma 
1583c7f3dcfSLiang Ma 	/* number of instances of this stage */
1593c7f3dcfSLiang Ma 	uint32_t num_instance;
1603c7f3dcfSLiang Ma 
1613c7f3dcfSLiang Ma 	/* instance ID of this stage*/
1623c7f3dcfSLiang Ma 	uint32_t instance_id;
1633c7f3dcfSLiang Ma 
1643c7f3dcfSLiang Ma 	/* track packets in and out of this port */
1653c7f3dcfSLiang Ma 	uint64_t port_stat[max_num_port_xstat];
1663c7f3dcfSLiang Ma 	uint64_t start_cycles;
1673c7f3dcfSLiang Ma };
1683c7f3dcfSLiang Ma 
1693c7f3dcfSLiang Ma struct opdl_queue_meta_data {
1703c7f3dcfSLiang Ma 	uint8_t         ext_id;
1713c7f3dcfSLiang Ma 	enum queue_type type;
1723c7f3dcfSLiang Ma 	int8_t          setup;
1733c7f3dcfSLiang Ma };
1743c7f3dcfSLiang Ma 
1753c7f3dcfSLiang Ma struct opdl_xstats_entry {
1763c7f3dcfSLiang Ma 	struct rte_event_dev_xstats_name stat;
1773c7f3dcfSLiang Ma 	unsigned int id;
1783c7f3dcfSLiang Ma 	uint64_t *value;
1793c7f3dcfSLiang Ma };
1803c7f3dcfSLiang Ma 
1813c7f3dcfSLiang Ma struct opdl_queue {
1823c7f3dcfSLiang Ma 
1833c7f3dcfSLiang Ma 	/* Opdl ring this queue is associated with */
1843c7f3dcfSLiang Ma 	uint32_t opdl_id;
1853c7f3dcfSLiang Ma 
1863c7f3dcfSLiang Ma 	/* type and position have correctly been set */
1873c7f3dcfSLiang Ma 	uint8_t configured;
1883c7f3dcfSLiang Ma 
1893c7f3dcfSLiang Ma 	/* port number and associated ports have been associated */
1903c7f3dcfSLiang Ma 	uint8_t initialized;
1913c7f3dcfSLiang Ma 
1923c7f3dcfSLiang Ma 	/* type of this queue (Atomic, Ordered, Parallel, Direct)*/
1933c7f3dcfSLiang Ma 	enum queue_type q_type;
1943c7f3dcfSLiang Ma 
1953c7f3dcfSLiang Ma 	/* position of queue (START, MIDDLE, END) */
1963c7f3dcfSLiang Ma 	enum queue_pos q_pos;
1973c7f3dcfSLiang Ma 
1983c7f3dcfSLiang Ma 	/* external queue id. It is mapped to the queue position */
1993c7f3dcfSLiang Ma 	uint8_t external_qid;
2003c7f3dcfSLiang Ma 
2013c7f3dcfSLiang Ma 	struct opdl_port *ports[OPDL_PORTS_MAX];
2023c7f3dcfSLiang Ma 	uint32_t nb_ports;
2033c7f3dcfSLiang Ma 
2043c7f3dcfSLiang Ma 	/* priority, reserved for future */
2053c7f3dcfSLiang Ma 	uint8_t priority;
2063c7f3dcfSLiang Ma };
2073c7f3dcfSLiang Ma 
2083c7f3dcfSLiang Ma 
2093c7f3dcfSLiang Ma #define OPDL_TUR_PER_DEV 12
2103c7f3dcfSLiang Ma 
2113c7f3dcfSLiang Ma /* PMD needs an extra queue per Opdl  */
2123c7f3dcfSLiang Ma #define OPDL_MAX_QUEUES (RTE_EVENT_MAX_QUEUES_PER_DEV - OPDL_TUR_PER_DEV)
2133c7f3dcfSLiang Ma 
2143c7f3dcfSLiang Ma 
2153c7f3dcfSLiang Ma struct opdl_evdev {
2163c7f3dcfSLiang Ma 	struct rte_eventdev_data *data;
2173c7f3dcfSLiang Ma 
2183c7f3dcfSLiang Ma 	uint8_t started;
2193c7f3dcfSLiang Ma 
2203c7f3dcfSLiang Ma 	/* Max number of ports and queues*/
2213c7f3dcfSLiang Ma 	uint32_t max_port_nb;
2223c7f3dcfSLiang Ma 	uint32_t max_queue_nb;
2233c7f3dcfSLiang Ma 
2243c7f3dcfSLiang Ma 	/* slots in the opdl ring */
2253c7f3dcfSLiang Ma 	uint32_t nb_events_limit;
2263c7f3dcfSLiang Ma 
2273c7f3dcfSLiang Ma 	/*
2283c7f3dcfSLiang Ma 	 * Array holding all opdl for this device
2293c7f3dcfSLiang Ma 	 */
2303c7f3dcfSLiang Ma 	struct opdl_ring *opdl[OPDL_TUR_PER_DEV];
2313c7f3dcfSLiang Ma 	uint32_t nb_opdls;
2323c7f3dcfSLiang Ma 
2333c7f3dcfSLiang Ma 	struct opdl_queue_meta_data q_md[OPDL_MAX_QUEUES];
2343c7f3dcfSLiang Ma 	uint32_t nb_q_md;
2353c7f3dcfSLiang Ma 
2363c7f3dcfSLiang Ma 	/* Internal queues - one per logical queue */
237*27595cd8STyler Retzlaff 	alignas(RTE_CACHE_LINE_SIZE) struct opdl_queue
238*27595cd8STyler Retzlaff 		queue[RTE_EVENT_MAX_QUEUES_PER_DEV];
2393c7f3dcfSLiang Ma 
2403c7f3dcfSLiang Ma 	uint32_t nb_queues;
2413c7f3dcfSLiang Ma 
2423c7f3dcfSLiang Ma 	struct opdl_stage_meta_data s_md[OPDL_PORTS_MAX];
2433c7f3dcfSLiang Ma 
2443c7f3dcfSLiang Ma 	/* Contains all ports - load balanced and directed */
245*27595cd8STyler Retzlaff 	alignas(RTE_CACHE_LINE_SIZE) struct opdl_port ports[OPDL_PORTS_MAX];
2463c7f3dcfSLiang Ma 	uint32_t nb_ports;
2473c7f3dcfSLiang Ma 
2483c7f3dcfSLiang Ma 	uint8_t q_map_ex_to_in[OPDL_INVALID_QID];
2493c7f3dcfSLiang Ma 
2503c7f3dcfSLiang Ma 	/* Stats */
2513c7f3dcfSLiang Ma 	struct opdl_xstats_entry port_xstat[OPDL_MAX_PORT_XSTAT_NUM];
2523c7f3dcfSLiang Ma 
2533c7f3dcfSLiang Ma 	char service_name[OPDL_PMD_NAME_MAX];
2543c7f3dcfSLiang Ma 	int socket;
2553c7f3dcfSLiang Ma 	int do_validation;
2563c7f3dcfSLiang Ma 	int do_test;
2573c7f3dcfSLiang Ma };
2583c7f3dcfSLiang Ma 
2593c7f3dcfSLiang Ma 
2603c7f3dcfSLiang Ma static inline struct opdl_evdev *
opdl_pmd_priv(const struct rte_eventdev * eventdev)2613c7f3dcfSLiang Ma opdl_pmd_priv(const struct rte_eventdev *eventdev)
2623c7f3dcfSLiang Ma {
2633c7f3dcfSLiang Ma 	return eventdev->data->dev_private;
2643c7f3dcfSLiang Ma }
2653c7f3dcfSLiang Ma 
2663c7f3dcfSLiang Ma static inline uint8_t
opdl_pmd_dev_id(const struct opdl_evdev * opdl)2673c7f3dcfSLiang Ma opdl_pmd_dev_id(const struct opdl_evdev *opdl)
2683c7f3dcfSLiang Ma {
2693c7f3dcfSLiang Ma 	return opdl->data->dev_id;
2703c7f3dcfSLiang Ma }
2713c7f3dcfSLiang Ma 
2723c7f3dcfSLiang Ma static inline const struct opdl_evdev *
opdl_pmd_priv_const(const struct rte_eventdev * eventdev)2733c7f3dcfSLiang Ma opdl_pmd_priv_const(const struct rte_eventdev *eventdev)
2743c7f3dcfSLiang Ma {
2753c7f3dcfSLiang Ma 	return eventdev->data->dev_private;
2763c7f3dcfSLiang Ma }
2773c7f3dcfSLiang Ma 
2783c7f3dcfSLiang Ma uint16_t opdl_event_enqueue(void *port, const struct rte_event *ev);
2793c7f3dcfSLiang Ma uint16_t opdl_event_enqueue_burst(void *port, const struct rte_event ev[],
2803c7f3dcfSLiang Ma 		uint16_t num);
2813c7f3dcfSLiang Ma 
2823c7f3dcfSLiang Ma uint16_t opdl_event_dequeue(void *port, struct rte_event *ev, uint64_t wait);
2833c7f3dcfSLiang Ma uint16_t opdl_event_dequeue_burst(void *port, struct rte_event *ev,
2843c7f3dcfSLiang Ma 		uint16_t num, uint64_t wait);
2853c7f3dcfSLiang Ma void opdl_event_schedule(struct rte_eventdev *dev);
2863c7f3dcfSLiang Ma 
2873c7f3dcfSLiang Ma void opdl_xstats_init(struct rte_eventdev *dev);
2883c7f3dcfSLiang Ma int opdl_xstats_uninit(struct rte_eventdev *dev);
2893c7f3dcfSLiang Ma int opdl_xstats_get_names(const struct rte_eventdev *dev,
2903c7f3dcfSLiang Ma 		enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
2913c7f3dcfSLiang Ma 		struct rte_event_dev_xstats_name *xstats_names,
2921bdfe4d7SPavan Nikhilesh 		uint64_t *ids, unsigned int size);
2933c7f3dcfSLiang Ma int opdl_xstats_get(const struct rte_eventdev *dev,
2943c7f3dcfSLiang Ma 		enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
2951bdfe4d7SPavan Nikhilesh 		const uint64_t ids[], uint64_t values[], unsigned int n);
2963c7f3dcfSLiang Ma uint64_t opdl_xstats_get_by_name(const struct rte_eventdev *dev,
2971bdfe4d7SPavan Nikhilesh 		const char *name, uint64_t *id);
2983c7f3dcfSLiang Ma int opdl_xstats_reset(struct rte_eventdev *dev,
2993c7f3dcfSLiang Ma 		enum rte_event_dev_xstats_mode mode,
3003c7f3dcfSLiang Ma 		int16_t queue_port_id,
3011bdfe4d7SPavan Nikhilesh 		const uint64_t ids[],
3023c7f3dcfSLiang Ma 		uint32_t nb_ids);
3033c7f3dcfSLiang Ma 
3043c7f3dcfSLiang Ma int opdl_add_event_handlers(struct rte_eventdev *dev);
3053c7f3dcfSLiang Ma int build_all_dependencies(struct rte_eventdev *dev);
3063c7f3dcfSLiang Ma int check_queues_linked(struct rte_eventdev *dev);
3073c7f3dcfSLiang Ma int create_queues_and_rings(struct rte_eventdev *dev);
3083c7f3dcfSLiang Ma int initialise_all_other_ports(struct rte_eventdev *dev);
3093c7f3dcfSLiang Ma int initialise_queue_zero_ports(struct rte_eventdev *dev);
3103c7f3dcfSLiang Ma int assign_internal_queue_ids(struct rte_eventdev *dev);
3113c7f3dcfSLiang Ma void destroy_queues_and_rings(struct rte_eventdev *dev);
312d548ef51SLiang Ma int opdl_selftest(void);
3133c7f3dcfSLiang Ma 
3143c7f3dcfSLiang Ma #endif /* _OPDL_EVDEV_H_ */
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