1 /* 2 * BSD LICENSE 3 * 4 * Copyright (C) Cavium, Inc. 2017. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Cavium, Inc nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef __SSOVF_EVDEV_H__ 34 #define __SSOVF_EVDEV_H__ 35 36 #include <rte_config.h> 37 #include <rte_eventdev_pmd_vdev.h> 38 #include <rte_io.h> 39 40 #include <octeontx_mbox.h> 41 #include <octeontx_ethdev.h> 42 43 #define EVENTDEV_NAME_OCTEONTX_PMD event_octeontx 44 45 #ifdef RTE_LIBRTE_PMD_OCTEONTX_SSOVF_DEBUG 46 #define ssovf_log_info(fmt, args...) \ 47 RTE_LOG(INFO, EVENTDEV, "[%s] %s() " fmt "\n", \ 48 RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args) 49 #define ssovf_log_dbg(fmt, args...) \ 50 RTE_LOG(DEBUG, EVENTDEV, "[%s] %s() " fmt "\n", \ 51 RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args) 52 #else 53 #define ssovf_log_info(fmt, args...) 54 #define ssovf_log_dbg(fmt, args...) 55 #endif 56 57 #define ssovf_func_trace ssovf_log_dbg 58 #define ssovf_log_err(fmt, args...) \ 59 RTE_LOG(ERR, EVENTDEV, "[%s] %s() " fmt "\n", \ 60 RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args) 61 62 #define SSO_MAX_VHGRP (64) 63 #define SSO_MAX_VHWS (32) 64 65 /* SSO VF register offsets */ 66 #define SSO_VHGRP_QCTL (0x010ULL) 67 #define SSO_VHGRP_INT (0x100ULL) 68 #define SSO_VHGRP_INT_W1S (0x108ULL) 69 #define SSO_VHGRP_INT_ENA_W1S (0x110ULL) 70 #define SSO_VHGRP_INT_ENA_W1C (0x118ULL) 71 #define SSO_VHGRP_INT_THR (0x140ULL) 72 #define SSO_VHGRP_INT_CNT (0x180ULL) 73 #define SSO_VHGRP_XAQ_CNT (0x1B0ULL) 74 #define SSO_VHGRP_AQ_CNT (0x1C0ULL) 75 #define SSO_VHGRP_AQ_THR (0x1E0ULL) 76 77 /* BAR2 */ 78 #define SSO_VHGRP_OP_ADD_WORK0 (0x00ULL) 79 #define SSO_VHGRP_OP_ADD_WORK1 (0x08ULL) 80 81 /* SSOW VF register offsets (BAR0) */ 82 #define SSOW_VHWS_GRPMSK_CHGX(x) (0x080ULL | ((x) << 3)) 83 #define SSOW_VHWS_TAG (0x300ULL) 84 #define SSOW_VHWS_WQP (0x308ULL) 85 #define SSOW_VHWS_LINKS (0x310ULL) 86 #define SSOW_VHWS_PENDTAG (0x340ULL) 87 #define SSOW_VHWS_PENDWQP (0x348ULL) 88 #define SSOW_VHWS_SWTP (0x400ULL) 89 #define SSOW_VHWS_OP_ALLOC_WE (0x410ULL) 90 #define SSOW_VHWS_OP_UPD_WQP_GRP0 (0x440ULL) 91 #define SSOW_VHWS_OP_UPD_WQP_GRP1 (0x448ULL) 92 #define SSOW_VHWS_OP_SWTAG_UNTAG (0x490ULL) 93 #define SSOW_VHWS_OP_SWTAG_CLR (0x820ULL) 94 #define SSOW_VHWS_OP_DESCHED (0x860ULL) 95 #define SSOW_VHWS_OP_DESCHED_NOSCH (0x870ULL) 96 #define SSOW_VHWS_OP_SWTAG_DESCHED (0x8C0ULL) 97 #define SSOW_VHWS_OP_SWTAG_NOSCHED (0x8D0ULL) 98 #define SSOW_VHWS_OP_SWTP_SET (0xC20ULL) 99 #define SSOW_VHWS_OP_SWTAG_NORM (0xC80ULL) 100 #define SSOW_VHWS_OP_SWTAG_FULL0 (0xCA0UL) 101 #define SSOW_VHWS_OP_SWTAG_FULL1 (0xCA8ULL) 102 #define SSOW_VHWS_OP_CLR_NSCHED (0x10000ULL) 103 #define SSOW_VHWS_OP_GET_WORK0 (0x80000ULL) 104 #define SSOW_VHWS_OP_GET_WORK1 (0x80008ULL) 105 106 /* Mailbox message constants */ 107 #define SSO_COPROC 0x2 108 109 #define SSO_GETDOMAINCFG 0x1 110 #define SSO_IDENTIFY 0x2 111 #define SSO_GET_DEV_INFO 0x3 112 #define SSO_GET_GETWORK_WAIT 0x4 113 #define SSO_SET_GETWORK_WAIT 0x5 114 #define SSO_CONVERT_NS_GETWORK_ITER 0x6 115 #define SSO_GRP_GET_PRIORITY 0x7 116 #define SSO_GRP_SET_PRIORITY 0x8 117 118 /* 119 * In Cavium OcteonTX SoC, all accesses to the device registers are 120 * implictly strongly ordered. So, The relaxed version of IO operation is 121 * safe to use with out any IO memory barriers. 122 */ 123 #define ssovf_read64 rte_read64_relaxed 124 #define ssovf_write64 rte_write64_relaxed 125 126 /* ARM64 specific functions */ 127 #if defined(RTE_ARCH_ARM64) 128 #define ssovf_load_pair(val0, val1, addr) ({ \ 129 asm volatile( \ 130 "ldp %x[x0], %x[x1], [%x[p1]]" \ 131 :[x0]"=r"(val0), [x1]"=r"(val1) \ 132 :[p1]"r"(addr) \ 133 ); }) 134 135 #define ssovf_store_pair(val0, val1, addr) ({ \ 136 asm volatile( \ 137 "stp %x[x0], %x[x1], [%x[p1]]" \ 138 ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \ 139 ); }) 140 #else /* Un optimized functions for building on non arm64 arch */ 141 142 #define ssovf_load_pair(val0, val1, addr) \ 143 do { \ 144 val0 = rte_read64(addr); \ 145 val1 = rte_read64(((uint8_t *)addr) + 8); \ 146 } while (0) 147 148 #define ssovf_store_pair(val0, val1, addr) \ 149 do { \ 150 rte_write64(val0, addr); \ 151 rte_write64(val1, (((uint8_t *)addr) + 8)); \ 152 } while (0) 153 #endif 154 155 156 struct ssovf_evdev { 157 uint8_t max_event_queues; 158 uint8_t max_event_ports; 159 uint8_t is_timeout_deq; 160 uint8_t nb_event_queues; 161 uint8_t nb_event_ports; 162 uint32_t min_deq_timeout_ns; 163 uint32_t max_deq_timeout_ns; 164 int32_t max_num_events; 165 } __rte_cache_aligned; 166 167 /* Event port aka HWS */ 168 struct ssows { 169 uint8_t cur_tt; 170 uint8_t cur_grp; 171 uint8_t swtag_req; 172 uint8_t *base; 173 uint8_t *getwork; 174 uint8_t *grps[SSO_MAX_VHGRP]; 175 uint8_t port; 176 } __rte_cache_aligned; 177 178 static inline struct ssovf_evdev * 179 ssovf_pmd_priv(const struct rte_eventdev *eventdev) 180 { 181 return eventdev->data->dev_private; 182 } 183 184 uint16_t ssows_enq(void *port, const struct rte_event *ev); 185 uint16_t ssows_enq_burst(void *port, 186 const struct rte_event ev[], uint16_t nb_events); 187 uint16_t ssows_enq_new_burst(void *port, 188 const struct rte_event ev[], uint16_t nb_events); 189 uint16_t ssows_enq_fwd_burst(void *port, 190 const struct rte_event ev[], uint16_t nb_events); 191 uint16_t ssows_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks); 192 uint16_t ssows_deq_burst(void *port, struct rte_event ev[], 193 uint16_t nb_events, uint64_t timeout_ticks); 194 uint16_t ssows_deq_timeout(void *port, struct rte_event *ev, 195 uint64_t timeout_ticks); 196 uint16_t ssows_deq_timeout_burst(void *port, struct rte_event ev[], 197 uint16_t nb_events, uint64_t timeout_ticks); 198 void ssows_flush_events(struct ssows *ws, uint8_t queue_id); 199 void ssows_reset(struct ssows *ws); 200 201 #endif /* __SSOVF_EVDEV_H__ */ 202