1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef __SSOVF_EVDEV_H__ 6 #define __SSOVF_EVDEV_H__ 7 8 #include <rte_event_eth_tx_adapter.h> 9 #include <rte_eventdev_pmd_vdev.h> 10 #include <rte_io.h> 11 12 #include <octeontx_mbox.h> 13 #include <octeontx_ethdev.h> 14 15 #include "octeontx_rxtx.h" 16 17 #define EVENTDEV_NAME_OCTEONTX_PMD event_octeontx 18 19 #define SSOVF_LOG(level, fmt, args...) \ 20 rte_log(RTE_LOG_ ## level, otx_logtype_ssovf, \ 21 "[%s] %s() " fmt "\n", \ 22 RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args) 23 24 #define ssovf_log_info(fmt, ...) SSOVF_LOG(INFO, fmt, ##__VA_ARGS__) 25 #define ssovf_log_dbg(fmt, ...) SSOVF_LOG(DEBUG, fmt, ##__VA_ARGS__) 26 #define ssovf_log_err(fmt, ...) SSOVF_LOG(ERR, fmt, ##__VA_ARGS__) 27 #define ssovf_func_trace ssovf_log_dbg 28 #define ssovf_log_selftest ssovf_log_info 29 30 #define SSO_MAX_VHGRP (64) 31 #define SSO_MAX_VHWS (32) 32 33 /* SSO VF register offsets */ 34 #define SSO_VHGRP_QCTL (0x010ULL) 35 #define SSO_VHGRP_INT (0x100ULL) 36 #define SSO_VHGRP_INT_W1S (0x108ULL) 37 #define SSO_VHGRP_INT_ENA_W1S (0x110ULL) 38 #define SSO_VHGRP_INT_ENA_W1C (0x118ULL) 39 #define SSO_VHGRP_INT_THR (0x140ULL) 40 #define SSO_VHGRP_INT_CNT (0x180ULL) 41 #define SSO_VHGRP_XAQ_CNT (0x1B0ULL) 42 #define SSO_VHGRP_AQ_CNT (0x1C0ULL) 43 #define SSO_VHGRP_AQ_THR (0x1E0ULL) 44 45 /* BAR2 */ 46 #define SSO_VHGRP_OP_ADD_WORK0 (0x00ULL) 47 #define SSO_VHGRP_OP_ADD_WORK1 (0x08ULL) 48 49 /* SSOW VF register offsets (BAR0) */ 50 #define SSOW_VHWS_GRPMSK_CHGX(x) (0x080ULL | ((x) << 3)) 51 #define SSOW_VHWS_TAG (0x300ULL) 52 #define SSOW_VHWS_WQP (0x308ULL) 53 #define SSOW_VHWS_LINKS (0x310ULL) 54 #define SSOW_VHWS_PENDTAG (0x340ULL) 55 #define SSOW_VHWS_PENDWQP (0x348ULL) 56 #define SSOW_VHWS_SWTP (0x400ULL) 57 #define SSOW_VHWS_OP_ALLOC_WE (0x410ULL) 58 #define SSOW_VHWS_OP_UPD_WQP_GRP0 (0x440ULL) 59 #define SSOW_VHWS_OP_UPD_WQP_GRP1 (0x448ULL) 60 #define SSOW_VHWS_OP_SWTAG_UNTAG (0x490ULL) 61 #define SSOW_VHWS_OP_SWTAG_CLR (0x820ULL) 62 #define SSOW_VHWS_OP_DESCHED (0x860ULL) 63 #define SSOW_VHWS_OP_DESCHED_NOSCH (0x870ULL) 64 #define SSOW_VHWS_OP_SWTAG_DESCHED (0x8C0ULL) 65 #define SSOW_VHWS_OP_SWTAG_NOSCHED (0x8D0ULL) 66 #define SSOW_VHWS_OP_SWTP_SET (0xC20ULL) 67 #define SSOW_VHWS_OP_SWTAG_NORM (0xC80ULL) 68 #define SSOW_VHWS_OP_SWTAG_FULL0 (0xCA0UL) 69 #define SSOW_VHWS_OP_SWTAG_FULL1 (0xCA8ULL) 70 #define SSOW_VHWS_OP_CLR_NSCHED (0x10000ULL) 71 #define SSOW_VHWS_OP_GET_WORK0 (0x80000ULL) 72 #define SSOW_VHWS_OP_GET_WORK1 (0x80008ULL) 73 74 /* Mailbox message constants */ 75 #define SSO_COPROC 0x2 76 77 #define SSO_GETDOMAINCFG 0x1 78 #define SSO_IDENTIFY 0x2 79 #define SSO_GET_DEV_INFO 0x3 80 #define SSO_GET_GETWORK_WAIT 0x4 81 #define SSO_SET_GETWORK_WAIT 0x5 82 #define SSO_CONVERT_NS_GETWORK_ITER 0x6 83 #define SSO_GRP_GET_PRIORITY 0x7 84 #define SSO_GRP_SET_PRIORITY 0x8 85 86 #define SSOVF_SELFTEST_ARG ("selftest") 87 88 /* 89 * In Cavium OCTEON TX SoC, all accesses to the device registers are 90 * implictly strongly ordered. So, The relaxed version of IO operation is 91 * safe to use with out any IO memory barriers. 92 */ 93 #define ssovf_read64 rte_read64_relaxed 94 #define ssovf_write64 rte_write64_relaxed 95 96 /* ARM64 specific functions */ 97 #if defined(RTE_ARCH_ARM64) 98 #define ssovf_load_pair(val0, val1, addr) ({ \ 99 asm volatile( \ 100 "ldp %x[x0], %x[x1], [%x[p1]]" \ 101 :[x0]"=r"(val0), [x1]"=r"(val1) \ 102 :[p1]"r"(addr) \ 103 ); }) 104 105 #define ssovf_store_pair(val0, val1, addr) ({ \ 106 asm volatile( \ 107 "stp %x[x0], %x[x1], [%x[p1]]" \ 108 ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \ 109 ); }) 110 #else /* Un optimized functions for building on non arm64 arch */ 111 112 #define ssovf_load_pair(val0, val1, addr) \ 113 do { \ 114 val0 = rte_read64(addr); \ 115 val1 = rte_read64(((uint8_t *)addr) + 8); \ 116 } while (0) 117 118 #define ssovf_store_pair(val0, val1, addr) \ 119 do { \ 120 rte_write64(val0, addr); \ 121 rte_write64(val1, (((uint8_t *)addr) + 8)); \ 122 } while (0) 123 #endif 124 125 struct ssovf_info { 126 uint16_t domain; /* Domain id */ 127 uint8_t total_ssovfs; /* Total sso groups available in domain */ 128 uint8_t total_ssowvfs;/* Total sso hws available in domain */ 129 }; 130 131 enum ssovf_type { 132 OCTEONTX_SSO_GROUP, /* SSO group vf */ 133 OCTEONTX_SSO_HWS, /* SSO hardware workslot vf */ 134 }; 135 136 struct ssovf_evdev { 137 OFFLOAD_FLAGS; /*Sequence should not be changed */ 138 uint8_t max_event_queues; 139 uint8_t max_event_ports; 140 uint8_t is_timeout_deq; 141 uint8_t nb_event_queues; 142 uint8_t nb_event_ports; 143 uint32_t min_deq_timeout_ns; 144 uint32_t max_deq_timeout_ns; 145 int32_t max_num_events; 146 } __rte_cache_aligned; 147 148 /* Event port aka HWS */ 149 struct ssows { 150 uint8_t cur_tt; 151 uint8_t cur_grp; 152 uint8_t swtag_req; 153 uint8_t *base; 154 uint8_t *getwork; 155 uint8_t *grps[SSO_MAX_VHGRP]; 156 uint8_t port; 157 } __rte_cache_aligned; 158 159 static inline struct ssovf_evdev * 160 ssovf_pmd_priv(const struct rte_eventdev *eventdev) 161 { 162 return eventdev->data->dev_private; 163 } 164 165 extern int otx_logtype_ssovf; 166 167 uint16_t ssows_enq(void *port, const struct rte_event *ev); 168 uint16_t ssows_enq_burst(void *port, 169 const struct rte_event ev[], uint16_t nb_events); 170 uint16_t ssows_enq_new_burst(void *port, 171 const struct rte_event ev[], uint16_t nb_events); 172 uint16_t ssows_enq_fwd_burst(void *port, 173 const struct rte_event ev[], uint16_t nb_events); 174 uint16_t ssows_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks); 175 uint16_t ssows_deq_burst(void *port, struct rte_event ev[], 176 uint16_t nb_events, uint64_t timeout_ticks); 177 uint16_t ssows_deq_timeout(void *port, struct rte_event *ev, 178 uint64_t timeout_ticks); 179 uint16_t ssows_deq_timeout_burst(void *port, struct rte_event ev[], 180 uint16_t nb_events, uint64_t timeout_ticks); 181 uint16_t ssows_deq_mseg(void *port, struct rte_event *ev, 182 uint64_t timeout_ticks); 183 uint16_t ssows_deq_burst_mseg(void *port, struct rte_event ev[], 184 uint16_t nb_events, uint64_t timeout_ticks); 185 uint16_t ssows_deq_timeout_mseg(void *port, struct rte_event *ev, 186 uint64_t timeout_ticks); 187 uint16_t ssows_deq_timeout_burst_mseg(void *port, struct rte_event ev[], 188 uint16_t nb_events, uint64_t timeout_ticks); 189 190 typedef void (*ssows_handle_event_t)(void *arg, struct rte_event ev); 191 void ssows_flush_events(struct ssows *ws, uint8_t queue_id, 192 ssows_handle_event_t fn, void *arg); 193 void ssows_reset(struct ssows *ws); 194 uint16_t sso_event_tx_adapter_enqueue(void *port, 195 struct rte_event ev[], uint16_t nb_events); 196 uint16_t sso_event_tx_adapter_enqueue_mseg(void *port, 197 struct rte_event ev[], uint16_t nb_events); 198 int ssovf_info(struct ssovf_info *info); 199 void *ssovf_bar(enum ssovf_type, uint8_t id, uint8_t bar); 200 int test_eventdev_octeontx(void); 201 202 #endif /* __SSOVF_EVDEV_H__ */ 203