1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 NXP 3 */ 4 5 #ifndef __DPAA2_EVENTDEV_H__ 6 #define __DPAA2_EVENTDEV_H__ 7 8 #include <eventdev_pmd.h> 9 #include <eventdev_pmd_vdev.h> 10 #include <rte_atomic.h> 11 #include <mc/fsl_dpcon.h> 12 #include <mc/fsl_mc_sys.h> 13 14 #define EVENTDEV_NAME_DPAA2_PMD event_dpaa2 15 16 #define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0 17 18 #define DPAA2_EVENT_MAX_QUEUES 16 19 #define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT 1 20 #define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT (UINT32_MAX - 1) 21 #define DPAA2_EVENT_PORT_DEQUEUE_TIMEOUT_NS 100UL 22 #define DPAA2_EVENT_MAX_QUEUE_FLOWS 2048 23 #define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS 8 24 #define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS 0 25 #define DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH 8 26 #define DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH 8 27 #define DPAA2_EVENT_MAX_NUM_EVENTS (INT32_MAX - 1) 28 29 #define DPAA2_EVENT_QUEUE_ATOMIC_FLOWS 2048 30 #define DPAA2_EVENT_QUEUE_ORDER_SEQUENCES 2048 31 32 enum { 33 DPAA2_EVENT_DPCI_PARALLEL_QUEUE, 34 DPAA2_EVENT_DPCI_ATOMIC_QUEUE, 35 DPAA2_EVENT_DPCI_MAX_QUEUES 36 }; 37 38 #define RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP \ 39 (RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \ 40 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \ 41 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID | \ 42 RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT) 43 44 /**< Crypto Rx adapter cap to return If the packet transfers from 45 * the cryptodev to eventdev with DPAA2 devices. 46 */ 47 #define RTE_EVENT_CRYPTO_ADAPTER_DPAA2_CAP \ 48 (RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW | \ 49 RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | \ 50 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA) 51 52 /**< Ethernet Rx adapter cap to return If the packet transfers from 53 * the ethdev to eventdev with DPAA2 devices. 54 */ 55 56 struct dpaa2_eventq { 57 /* DPcon device */ 58 struct dpaa2_dpcon_dev *dpcon; 59 /* Attached DPCI device */ 60 struct dpaa2_dpci_dev *dpci; 61 /* Mapped event port */ 62 struct dpaa2_io_portal_t *event_port; 63 /* Configuration provided by the user */ 64 uint32_t event_queue_cfg; 65 uint32_t event_queue_id; 66 }; 67 68 struct dpaa2_port { 69 struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES]; 70 uint8_t num_linked_evq; 71 uint8_t is_port_linked; 72 uint64_t timeout_us; 73 }; 74 75 struct dpaa2_eventdev { 76 struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES]; 77 uint32_t dequeue_timeout_ns; 78 uint8_t max_event_queues; 79 uint8_t nb_event_queues; 80 uint8_t nb_event_ports; 81 uint8_t resvd_1; 82 uint32_t nb_event_queue_flows; 83 uint32_t nb_event_port_dequeue_depth; 84 uint32_t nb_event_port_enqueue_depth; 85 uint32_t event_dev_cfg; 86 }; 87 88 struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void); 89 void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon); 90 91 int test_eventdev_dpaa2(void); 92 93 #endif /* __DPAA2_EVENTDEV_H__ */ 94