1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017-2019 NXP 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/epoll.h> 12 13 #include <rte_atomic.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_debug.h> 17 #include <rte_dev.h> 18 #include <rte_eal.h> 19 #include <rte_lcore.h> 20 #include <rte_log.h> 21 #include <rte_malloc.h> 22 #include <rte_memcpy.h> 23 #include <rte_memory.h> 24 #include <rte_memzone.h> 25 #include <rte_pci.h> 26 #include <rte_eventdev.h> 27 #include <eventdev_pmd_vdev.h> 28 #include <rte_ethdev.h> 29 #include <rte_event_eth_rx_adapter.h> 30 #include <rte_event_eth_tx_adapter.h> 31 #include <cryptodev_pmd.h> 32 #include <rte_dpaa_bus.h> 33 #include <rte_dpaa_logs.h> 34 #include <rte_cycles.h> 35 #include <rte_kvargs.h> 36 37 #include <dpaa_ethdev.h> 38 #include <dpaa_sec_event.h> 39 #include "dpaa_eventdev.h" 40 #include <dpaa_mempool.h> 41 42 /* 43 * Clarifications 44 * Evendev = Virtual Instance for SoC 45 * Eventport = Portal Instance 46 * Eventqueue = Channel Instance 47 * 1 Eventdev can have N Eventqueue 48 */ 49 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_eventdev, NOTICE); 50 51 #define DISABLE_INTR_MODE "disable_intr" 52 53 static int 54 dpaa_event_dequeue_timeout_ticks(struct rte_eventdev *dev, uint64_t ns, 55 uint64_t *timeout_ticks) 56 { 57 EVENTDEV_INIT_FUNC_TRACE(); 58 59 RTE_SET_USED(dev); 60 61 uint64_t cycles_per_second; 62 63 cycles_per_second = rte_get_timer_hz(); 64 *timeout_ticks = (ns * cycles_per_second) / NS_PER_S; 65 66 return 0; 67 } 68 69 static int 70 dpaa_event_dequeue_timeout_ticks_intr(struct rte_eventdev *dev, uint64_t ns, 71 uint64_t *timeout_ticks) 72 { 73 RTE_SET_USED(dev); 74 75 *timeout_ticks = ns/1000; 76 return 0; 77 } 78 79 static void 80 dpaa_eventq_portal_add(u16 ch_id) 81 { 82 uint32_t sdqcr; 83 84 sdqcr = QM_SDQCR_CHANNELS_POOL_CONV(ch_id); 85 qman_static_dequeue_add(sdqcr, NULL); 86 } 87 88 static uint16_t 89 dpaa_event_enqueue_burst(void *port, const struct rte_event ev[], 90 uint16_t nb_events) 91 { 92 uint16_t i; 93 struct rte_mbuf *mbuf; 94 95 RTE_SET_USED(port); 96 /*Release all the contexts saved previously*/ 97 for (i = 0; i < nb_events; i++) { 98 switch (ev[i].op) { 99 case RTE_EVENT_OP_RELEASE: 100 qman_dca_index(ev[i].impl_opaque, 0); 101 mbuf = DPAA_PER_LCORE_DQRR_MBUF(i); 102 *dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN; 103 DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i); 104 DPAA_PER_LCORE_DQRR_SIZE--; 105 break; 106 default: 107 break; 108 } 109 } 110 111 return nb_events; 112 } 113 114 static uint16_t 115 dpaa_event_enqueue(void *port, const struct rte_event *ev) 116 { 117 return dpaa_event_enqueue_burst(port, ev, 1); 118 } 119 120 static void drain_4_bytes(int fd, fd_set *fdset) 121 { 122 if (FD_ISSET(fd, fdset)) { 123 /* drain 4 bytes */ 124 uint32_t junk; 125 ssize_t sjunk = read(qman_thread_fd(), &junk, sizeof(junk)); 126 if (sjunk != sizeof(junk)) 127 DPAA_EVENTDEV_ERR("UIO irq read error"); 128 } 129 } 130 131 static inline int 132 dpaa_event_dequeue_wait(uint64_t timeout_ticks) 133 { 134 int fd_qman, nfds; 135 int ret; 136 fd_set readset; 137 138 /* Go into (and back out of) IRQ mode for each select, 139 * it simplifies exit-path considerations and other 140 * potential nastiness. 141 */ 142 struct timeval tv = { 143 .tv_sec = timeout_ticks / 1000000, 144 .tv_usec = timeout_ticks % 1000000 145 }; 146 147 fd_qman = qman_thread_fd(); 148 nfds = fd_qman + 1; 149 FD_ZERO(&readset); 150 FD_SET(fd_qman, &readset); 151 152 qman_irqsource_add(QM_PIRQ_DQRI); 153 154 ret = select(nfds, &readset, NULL, NULL, &tv); 155 if (ret < 0) 156 return ret; 157 /* Calling irqsource_remove() prior to thread_irq() 158 * means thread_irq() will not process whatever caused 159 * the interrupts, however it does ensure that, once 160 * thread_irq() re-enables interrupts, they won't fire 161 * again immediately. 162 */ 163 qman_irqsource_remove(~0); 164 drain_4_bytes(fd_qman, &readset); 165 qman_thread_irq(); 166 167 return ret; 168 } 169 170 static uint16_t 171 dpaa_event_dequeue_burst(void *port, struct rte_event ev[], 172 uint16_t nb_events, uint64_t timeout_ticks) 173 { 174 int ret; 175 u16 ch_id; 176 void *buffers[8]; 177 u32 num_frames, i; 178 uint64_t cur_ticks = 0, wait_time_ticks = 0; 179 struct dpaa_port *portal = (struct dpaa_port *)port; 180 struct rte_mbuf *mbuf; 181 182 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 183 /* Affine current thread context to a qman portal */ 184 ret = rte_dpaa_portal_init((void *)0); 185 if (ret) { 186 DPAA_EVENTDEV_ERR("Unable to initialize portal"); 187 return ret; 188 } 189 } 190 191 if (unlikely(!portal->is_port_linked)) { 192 /* 193 * Affine event queue for current thread context 194 * to a qman portal. 195 */ 196 for (i = 0; i < portal->num_linked_evq; i++) { 197 ch_id = portal->evq_info[i].ch_id; 198 dpaa_eventq_portal_add(ch_id); 199 } 200 portal->is_port_linked = true; 201 } 202 203 /* Check if there are atomic contexts to be released */ 204 i = 0; 205 while (DPAA_PER_LCORE_DQRR_SIZE) { 206 if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) { 207 qman_dca_index(i, 0); 208 mbuf = DPAA_PER_LCORE_DQRR_MBUF(i); 209 *dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN; 210 DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i); 211 DPAA_PER_LCORE_DQRR_SIZE--; 212 } 213 i++; 214 } 215 DPAA_PER_LCORE_DQRR_HELD = 0; 216 217 if (timeout_ticks) 218 wait_time_ticks = timeout_ticks; 219 else 220 wait_time_ticks = portal->timeout_us; 221 222 wait_time_ticks += rte_get_timer_cycles(); 223 do { 224 /* Lets dequeue the frames */ 225 num_frames = qman_portal_dequeue(ev, nb_events, buffers); 226 if (num_frames) 227 break; 228 cur_ticks = rte_get_timer_cycles(); 229 } while (cur_ticks < wait_time_ticks); 230 231 return num_frames; 232 } 233 234 static uint16_t 235 dpaa_event_dequeue(void *port, struct rte_event *ev, uint64_t timeout_ticks) 236 { 237 return dpaa_event_dequeue_burst(port, ev, 1, timeout_ticks); 238 } 239 240 static uint16_t 241 dpaa_event_dequeue_burst_intr(void *port, struct rte_event ev[], 242 uint16_t nb_events, uint64_t timeout_ticks) 243 { 244 int ret; 245 u16 ch_id; 246 void *buffers[8]; 247 u32 num_frames, i, irq = 0; 248 uint64_t cur_ticks = 0, wait_time_ticks = 0; 249 struct dpaa_port *portal = (struct dpaa_port *)port; 250 struct rte_mbuf *mbuf; 251 252 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 253 /* Affine current thread context to a qman portal */ 254 ret = rte_dpaa_portal_init((void *)0); 255 if (ret) { 256 DPAA_EVENTDEV_ERR("Unable to initialize portal"); 257 return ret; 258 } 259 } 260 261 if (unlikely(!portal->is_port_linked)) { 262 /* 263 * Affine event queue for current thread context 264 * to a qman portal. 265 */ 266 for (i = 0; i < portal->num_linked_evq; i++) { 267 ch_id = portal->evq_info[i].ch_id; 268 dpaa_eventq_portal_add(ch_id); 269 } 270 portal->is_port_linked = true; 271 } 272 273 /* Check if there are atomic contexts to be released */ 274 i = 0; 275 while (DPAA_PER_LCORE_DQRR_SIZE) { 276 if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) { 277 qman_dca_index(i, 0); 278 mbuf = DPAA_PER_LCORE_DQRR_MBUF(i); 279 *dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN; 280 DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i); 281 DPAA_PER_LCORE_DQRR_SIZE--; 282 } 283 i++; 284 } 285 DPAA_PER_LCORE_DQRR_HELD = 0; 286 287 if (timeout_ticks) 288 wait_time_ticks = timeout_ticks; 289 else 290 wait_time_ticks = portal->timeout_us; 291 292 do { 293 /* Lets dequeue the frames */ 294 num_frames = qman_portal_dequeue(ev, nb_events, buffers); 295 if (irq) 296 irq = 0; 297 if (num_frames) 298 break; 299 if (wait_time_ticks) { /* wait for time */ 300 if (dpaa_event_dequeue_wait(wait_time_ticks) > 0) { 301 irq = 1; 302 continue; 303 } 304 break; /* no event after waiting */ 305 } 306 cur_ticks = rte_get_timer_cycles(); 307 } while (cur_ticks < wait_time_ticks); 308 309 return num_frames; 310 } 311 312 static uint16_t 313 dpaa_event_dequeue_intr(void *port, 314 struct rte_event *ev, 315 uint64_t timeout_ticks) 316 { 317 return dpaa_event_dequeue_burst_intr(port, ev, 1, timeout_ticks); 318 } 319 320 static void 321 dpaa_event_dev_info_get(struct rte_eventdev *dev, 322 struct rte_event_dev_info *dev_info) 323 { 324 EVENTDEV_INIT_FUNC_TRACE(); 325 326 RTE_SET_USED(dev); 327 dev_info->driver_name = "event_dpaa1"; 328 dev_info->min_dequeue_timeout_ns = 329 DPAA_EVENT_MIN_DEQUEUE_TIMEOUT; 330 dev_info->max_dequeue_timeout_ns = 331 DPAA_EVENT_MAX_DEQUEUE_TIMEOUT; 332 dev_info->dequeue_timeout_ns = 333 DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_NS; 334 dev_info->max_event_queues = 335 DPAA_EVENT_MAX_QUEUES; 336 dev_info->max_event_queue_flows = 337 DPAA_EVENT_MAX_QUEUE_FLOWS; 338 dev_info->max_event_queue_priority_levels = 339 DPAA_EVENT_MAX_QUEUE_PRIORITY_LEVELS; 340 dev_info->max_event_priority_levels = 341 DPAA_EVENT_MAX_EVENT_PRIORITY_LEVELS; 342 dev_info->max_event_ports = 343 DPAA_EVENT_MAX_EVENT_PORT; 344 dev_info->max_event_port_dequeue_depth = 345 DPAA_EVENT_MAX_PORT_DEQUEUE_DEPTH; 346 dev_info->max_event_port_enqueue_depth = 347 DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH; 348 /* 349 * TODO: Need to find out that how to fetch this info 350 * from kernel or somewhere else. 351 */ 352 dev_info->max_num_events = 353 DPAA_EVENT_MAX_NUM_EVENTS; 354 dev_info->event_dev_cap = 355 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED | 356 RTE_EVENT_DEV_CAP_BURST_MODE | 357 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT | 358 RTE_EVENT_DEV_CAP_NONSEQ_MODE | 359 RTE_EVENT_DEV_CAP_CARRY_FLOW_ID | 360 RTE_EVENT_DEV_CAP_MAINTENANCE_FREE; 361 } 362 363 static int 364 dpaa_event_dev_configure(const struct rte_eventdev *dev) 365 { 366 struct dpaa_eventdev *priv = dev->data->dev_private; 367 struct rte_event_dev_config *conf = &dev->data->dev_conf; 368 int ret, i; 369 uint32_t *ch_id; 370 371 EVENTDEV_INIT_FUNC_TRACE(); 372 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns; 373 priv->nb_events_limit = conf->nb_events_limit; 374 priv->nb_event_queues = conf->nb_event_queues; 375 priv->nb_event_ports = conf->nb_event_ports; 376 priv->nb_event_queue_flows = conf->nb_event_queue_flows; 377 priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth; 378 priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth; 379 priv->event_dev_cfg = conf->event_dev_cfg; 380 381 ch_id = rte_malloc("dpaa-channels", 382 sizeof(uint32_t) * priv->nb_event_queues, 383 RTE_CACHE_LINE_SIZE); 384 if (ch_id == NULL) { 385 DPAA_EVENTDEV_ERR("Fail to allocate memory for dpaa channels\n"); 386 return -ENOMEM; 387 } 388 /* Create requested event queues within the given event device */ 389 ret = qman_alloc_pool_range(ch_id, priv->nb_event_queues, 1, 0); 390 if (ret < 0) { 391 DPAA_EVENTDEV_ERR("qman_alloc_pool_range %u, err =%d\n", 392 priv->nb_event_queues, ret); 393 rte_free(ch_id); 394 return ret; 395 } 396 for (i = 0; i < priv->nb_event_queues; i++) 397 priv->evq_info[i].ch_id = (u16)ch_id[i]; 398 399 /* Lets prepare event ports */ 400 memset(&priv->ports[0], 0, 401 sizeof(struct dpaa_port) * priv->nb_event_ports); 402 403 /* Check dequeue timeout method is per dequeue or global */ 404 if (priv->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) { 405 /* 406 * Use timeout value as given in dequeue operation. 407 * So invalidating this timeout value. 408 */ 409 priv->dequeue_timeout_ns = 0; 410 411 } else if (conf->dequeue_timeout_ns == 0) { 412 priv->dequeue_timeout_ns = DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_NS; 413 } else { 414 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns; 415 } 416 417 for (i = 0; i < priv->nb_event_ports; i++) { 418 if (priv->intr_mode) { 419 priv->ports[i].timeout_us = 420 priv->dequeue_timeout_ns/1000; 421 } else { 422 uint64_t cycles_per_second; 423 424 cycles_per_second = rte_get_timer_hz(); 425 priv->ports[i].timeout_us = 426 (priv->dequeue_timeout_ns * cycles_per_second) 427 / NS_PER_S; 428 } 429 } 430 431 /* 432 * TODO: Currently portals are affined with threads. Maximum threads 433 * can be created equals to number of lcore. 434 */ 435 rte_free(ch_id); 436 DPAA_EVENTDEV_INFO("Configured eventdev devid=%d", dev->data->dev_id); 437 438 return 0; 439 } 440 441 static int 442 dpaa_event_dev_start(struct rte_eventdev *dev) 443 { 444 EVENTDEV_INIT_FUNC_TRACE(); 445 RTE_SET_USED(dev); 446 447 return 0; 448 } 449 450 static void 451 dpaa_event_dev_stop(struct rte_eventdev *dev) 452 { 453 EVENTDEV_INIT_FUNC_TRACE(); 454 RTE_SET_USED(dev); 455 } 456 457 static int 458 dpaa_event_dev_close(struct rte_eventdev *dev) 459 { 460 EVENTDEV_INIT_FUNC_TRACE(); 461 RTE_SET_USED(dev); 462 463 return 0; 464 } 465 466 static void 467 dpaa_event_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id, 468 struct rte_event_queue_conf *queue_conf) 469 { 470 EVENTDEV_INIT_FUNC_TRACE(); 471 472 RTE_SET_USED(dev); 473 RTE_SET_USED(queue_id); 474 475 memset(queue_conf, 0, sizeof(struct rte_event_queue_conf)); 476 queue_conf->nb_atomic_flows = DPAA_EVENT_QUEUE_ATOMIC_FLOWS; 477 queue_conf->schedule_type = RTE_SCHED_TYPE_PARALLEL; 478 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_HIGHEST; 479 } 480 481 static int 482 dpaa_event_queue_setup(struct rte_eventdev *dev, uint8_t queue_id, 483 const struct rte_event_queue_conf *queue_conf) 484 { 485 struct dpaa_eventdev *priv = dev->data->dev_private; 486 struct dpaa_eventq *evq_info = &priv->evq_info[queue_id]; 487 488 EVENTDEV_INIT_FUNC_TRACE(); 489 490 switch (queue_conf->schedule_type) { 491 case RTE_SCHED_TYPE_PARALLEL: 492 case RTE_SCHED_TYPE_ATOMIC: 493 break; 494 case RTE_SCHED_TYPE_ORDERED: 495 DPAA_EVENTDEV_ERR("Schedule type is not supported."); 496 return -1; 497 } 498 evq_info->event_queue_cfg = queue_conf->event_queue_cfg; 499 evq_info->event_queue_id = queue_id; 500 501 return 0; 502 } 503 504 static void 505 dpaa_event_queue_release(struct rte_eventdev *dev, uint8_t queue_id) 506 { 507 EVENTDEV_INIT_FUNC_TRACE(); 508 509 RTE_SET_USED(dev); 510 RTE_SET_USED(queue_id); 511 } 512 513 static void 514 dpaa_event_port_default_conf_get(struct rte_eventdev *dev, uint8_t port_id, 515 struct rte_event_port_conf *port_conf) 516 { 517 EVENTDEV_INIT_FUNC_TRACE(); 518 519 RTE_SET_USED(dev); 520 RTE_SET_USED(port_id); 521 522 port_conf->new_event_threshold = DPAA_EVENT_MAX_NUM_EVENTS; 523 port_conf->dequeue_depth = DPAA_EVENT_MAX_PORT_DEQUEUE_DEPTH; 524 port_conf->enqueue_depth = DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH; 525 } 526 527 static int 528 dpaa_event_port_setup(struct rte_eventdev *dev, uint8_t port_id, 529 const struct rte_event_port_conf *port_conf) 530 { 531 struct dpaa_eventdev *eventdev = dev->data->dev_private; 532 533 EVENTDEV_INIT_FUNC_TRACE(); 534 535 RTE_SET_USED(port_conf); 536 dev->data->ports[port_id] = &eventdev->ports[port_id]; 537 538 return 0; 539 } 540 541 static void 542 dpaa_event_port_release(void *port) 543 { 544 EVENTDEV_INIT_FUNC_TRACE(); 545 546 RTE_SET_USED(port); 547 } 548 549 static int 550 dpaa_event_port_link(struct rte_eventdev *dev, void *port, 551 const uint8_t queues[], const uint8_t priorities[], 552 uint16_t nb_links) 553 { 554 struct dpaa_eventdev *priv = dev->data->dev_private; 555 struct dpaa_port *event_port = (struct dpaa_port *)port; 556 struct dpaa_eventq *event_queue; 557 uint8_t eventq_id; 558 int i; 559 560 RTE_SET_USED(dev); 561 RTE_SET_USED(priorities); 562 563 /* First check that input configuration are valid */ 564 for (i = 0; i < nb_links; i++) { 565 eventq_id = queues[i]; 566 event_queue = &priv->evq_info[eventq_id]; 567 if ((event_queue->event_queue_cfg 568 & RTE_EVENT_QUEUE_CFG_SINGLE_LINK) 569 && (event_queue->event_port)) { 570 return -EINVAL; 571 } 572 } 573 574 for (i = 0; i < nb_links; i++) { 575 eventq_id = queues[i]; 576 event_queue = &priv->evq_info[eventq_id]; 577 event_port->evq_info[i].event_queue_id = eventq_id; 578 event_port->evq_info[i].ch_id = event_queue->ch_id; 579 event_queue->event_port = port; 580 } 581 582 event_port->num_linked_evq = event_port->num_linked_evq + i; 583 584 return (int)i; 585 } 586 587 static int 588 dpaa_event_port_unlink(struct rte_eventdev *dev, void *port, 589 uint8_t queues[], uint16_t nb_links) 590 { 591 int i; 592 uint8_t eventq_id; 593 struct dpaa_eventq *event_queue; 594 struct dpaa_eventdev *priv = dev->data->dev_private; 595 struct dpaa_port *event_port = (struct dpaa_port *)port; 596 597 if (!event_port->num_linked_evq) 598 return nb_links; 599 600 for (i = 0; i < nb_links; i++) { 601 eventq_id = queues[i]; 602 event_port->evq_info[eventq_id].event_queue_id = -1; 603 event_port->evq_info[eventq_id].ch_id = 0; 604 event_queue = &priv->evq_info[eventq_id]; 605 event_queue->event_port = NULL; 606 } 607 608 if (event_port->num_linked_evq) 609 event_port->num_linked_evq = event_port->num_linked_evq - i; 610 611 return (int)i; 612 } 613 614 static int 615 dpaa_event_eth_rx_adapter_caps_get(const struct rte_eventdev *dev, 616 const struct rte_eth_dev *eth_dev, 617 uint32_t *caps) 618 { 619 const char *ethdev_driver = eth_dev->device->driver->name; 620 621 EVENTDEV_INIT_FUNC_TRACE(); 622 623 RTE_SET_USED(dev); 624 625 if (!strcmp(ethdev_driver, "net_dpaa")) 626 *caps = RTE_EVENT_ETH_RX_ADAPTER_DPAA_CAP; 627 else 628 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP; 629 630 return 0; 631 } 632 633 static int 634 dpaa_event_eth_rx_adapter_queue_add( 635 const struct rte_eventdev *dev, 636 const struct rte_eth_dev *eth_dev, 637 int32_t rx_queue_id, 638 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 639 { 640 struct dpaa_eventdev *eventdev = dev->data->dev_private; 641 uint8_t ev_qid = queue_conf->ev.queue_id; 642 u16 ch_id = eventdev->evq_info[ev_qid].ch_id; 643 struct dpaa_if *dpaa_intf = eth_dev->data->dev_private; 644 int ret, i; 645 646 EVENTDEV_INIT_FUNC_TRACE(); 647 648 if (rx_queue_id == -1) { 649 for (i = 0; i < dpaa_intf->nb_rx_queues; i++) { 650 ret = dpaa_eth_eventq_attach(eth_dev, i, ch_id, 651 queue_conf); 652 if (ret) { 653 DPAA_EVENTDEV_ERR( 654 "Event Queue attach failed:%d\n", ret); 655 goto detach_configured_queues; 656 } 657 } 658 return 0; 659 } 660 661 ret = dpaa_eth_eventq_attach(eth_dev, rx_queue_id, ch_id, queue_conf); 662 if (ret) 663 DPAA_EVENTDEV_ERR("dpaa_eth_eventq_attach failed:%d\n", ret); 664 return ret; 665 666 detach_configured_queues: 667 668 for (i = (i - 1); i >= 0 ; i--) 669 dpaa_eth_eventq_detach(eth_dev, i); 670 671 return ret; 672 } 673 674 static int 675 dpaa_event_eth_rx_adapter_queue_del(const struct rte_eventdev *dev, 676 const struct rte_eth_dev *eth_dev, 677 int32_t rx_queue_id) 678 { 679 int ret, i; 680 struct dpaa_if *dpaa_intf = eth_dev->data->dev_private; 681 682 EVENTDEV_INIT_FUNC_TRACE(); 683 684 RTE_SET_USED(dev); 685 if (rx_queue_id == -1) { 686 for (i = 0; i < dpaa_intf->nb_rx_queues; i++) { 687 ret = dpaa_eth_eventq_detach(eth_dev, i); 688 if (ret) 689 DPAA_EVENTDEV_ERR( 690 "Event Queue detach failed:%d\n", ret); 691 } 692 693 return 0; 694 } 695 696 ret = dpaa_eth_eventq_detach(eth_dev, rx_queue_id); 697 if (ret) 698 DPAA_EVENTDEV_ERR("dpaa_eth_eventq_detach failed:%d\n", ret); 699 return ret; 700 } 701 702 static int 703 dpaa_event_eth_rx_adapter_start(const struct rte_eventdev *dev, 704 const struct rte_eth_dev *eth_dev) 705 { 706 EVENTDEV_INIT_FUNC_TRACE(); 707 708 RTE_SET_USED(dev); 709 RTE_SET_USED(eth_dev); 710 711 return 0; 712 } 713 714 static int 715 dpaa_event_eth_rx_adapter_stop(const struct rte_eventdev *dev, 716 const struct rte_eth_dev *eth_dev) 717 { 718 EVENTDEV_INIT_FUNC_TRACE(); 719 720 RTE_SET_USED(dev); 721 RTE_SET_USED(eth_dev); 722 723 return 0; 724 } 725 726 static int 727 dpaa_eventdev_crypto_caps_get(const struct rte_eventdev *dev, 728 const struct rte_cryptodev *cdev, 729 uint32_t *caps) 730 { 731 const char *name = cdev->data->name; 732 733 EVENTDEV_INIT_FUNC_TRACE(); 734 735 RTE_SET_USED(dev); 736 737 if (!strncmp(name, "dpaa_sec-", 9)) 738 *caps = RTE_EVENT_CRYPTO_ADAPTER_DPAA_CAP; 739 else 740 return -1; 741 742 return 0; 743 } 744 745 static int 746 dpaa_eventdev_crypto_queue_add_all(const struct rte_eventdev *dev, 747 const struct rte_cryptodev *cryptodev, 748 const struct rte_event *ev) 749 { 750 struct dpaa_eventdev *priv = dev->data->dev_private; 751 uint8_t ev_qid = ev->queue_id; 752 u16 ch_id = priv->evq_info[ev_qid].ch_id; 753 int i, ret; 754 755 EVENTDEV_INIT_FUNC_TRACE(); 756 757 for (i = 0; i < cryptodev->data->nb_queue_pairs; i++) { 758 ret = dpaa_sec_eventq_attach(cryptodev, i, 759 ch_id, ev); 760 if (ret) { 761 DPAA_EVENTDEV_ERR("dpaa_sec_eventq_attach failed: ret %d\n", 762 ret); 763 goto fail; 764 } 765 } 766 return 0; 767 fail: 768 for (i = (i - 1); i >= 0 ; i--) 769 dpaa_sec_eventq_detach(cryptodev, i); 770 771 return ret; 772 } 773 774 static int 775 dpaa_eventdev_crypto_queue_add(const struct rte_eventdev *dev, 776 const struct rte_cryptodev *cryptodev, 777 int32_t rx_queue_id, 778 const struct rte_event *ev) 779 { 780 struct dpaa_eventdev *priv = dev->data->dev_private; 781 uint8_t ev_qid = ev->queue_id; 782 u16 ch_id = priv->evq_info[ev_qid].ch_id; 783 int ret; 784 785 EVENTDEV_INIT_FUNC_TRACE(); 786 787 if (rx_queue_id == -1) 788 return dpaa_eventdev_crypto_queue_add_all(dev, 789 cryptodev, ev); 790 791 ret = dpaa_sec_eventq_attach(cryptodev, rx_queue_id, 792 ch_id, ev); 793 if (ret) { 794 DPAA_EVENTDEV_ERR( 795 "dpaa_sec_eventq_attach failed: ret: %d\n", ret); 796 return ret; 797 } 798 return 0; 799 } 800 801 static int 802 dpaa_eventdev_crypto_queue_del_all(const struct rte_eventdev *dev, 803 const struct rte_cryptodev *cdev) 804 { 805 int i, ret; 806 807 EVENTDEV_INIT_FUNC_TRACE(); 808 809 RTE_SET_USED(dev); 810 811 for (i = 0; i < cdev->data->nb_queue_pairs; i++) { 812 ret = dpaa_sec_eventq_detach(cdev, i); 813 if (ret) { 814 DPAA_EVENTDEV_ERR( 815 "dpaa_sec_eventq_detach failed:ret %d\n", ret); 816 return ret; 817 } 818 } 819 820 return 0; 821 } 822 823 static int 824 dpaa_eventdev_crypto_queue_del(const struct rte_eventdev *dev, 825 const struct rte_cryptodev *cryptodev, 826 int32_t rx_queue_id) 827 { 828 int ret; 829 830 EVENTDEV_INIT_FUNC_TRACE(); 831 832 if (rx_queue_id == -1) 833 return dpaa_eventdev_crypto_queue_del_all(dev, cryptodev); 834 835 ret = dpaa_sec_eventq_detach(cryptodev, rx_queue_id); 836 if (ret) { 837 DPAA_EVENTDEV_ERR( 838 "dpaa_sec_eventq_detach failed: ret: %d\n", ret); 839 return ret; 840 } 841 842 return 0; 843 } 844 845 static int 846 dpaa_eventdev_crypto_start(const struct rte_eventdev *dev, 847 const struct rte_cryptodev *cryptodev) 848 { 849 EVENTDEV_INIT_FUNC_TRACE(); 850 851 RTE_SET_USED(dev); 852 RTE_SET_USED(cryptodev); 853 854 return 0; 855 } 856 857 static int 858 dpaa_eventdev_crypto_stop(const struct rte_eventdev *dev, 859 const struct rte_cryptodev *cryptodev) 860 { 861 EVENTDEV_INIT_FUNC_TRACE(); 862 863 RTE_SET_USED(dev); 864 RTE_SET_USED(cryptodev); 865 866 return 0; 867 } 868 869 static int 870 dpaa_eventdev_tx_adapter_create(uint8_t id, 871 const struct rte_eventdev *dev) 872 { 873 RTE_SET_USED(id); 874 RTE_SET_USED(dev); 875 876 /* Nothing to do. Simply return. */ 877 return 0; 878 } 879 880 static int 881 dpaa_eventdev_tx_adapter_caps(const struct rte_eventdev *dev, 882 const struct rte_eth_dev *eth_dev, 883 uint32_t *caps) 884 { 885 RTE_SET_USED(dev); 886 RTE_SET_USED(eth_dev); 887 888 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT; 889 return 0; 890 } 891 892 static uint16_t 893 dpaa_eventdev_txa_enqueue_same_dest(void *port, 894 struct rte_event ev[], 895 uint16_t nb_events) 896 { 897 struct rte_mbuf *m[DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH], *m0; 898 uint8_t qid, i; 899 900 RTE_SET_USED(port); 901 902 m0 = (struct rte_mbuf *)ev[0].mbuf; 903 qid = rte_event_eth_tx_adapter_txq_get(m0); 904 905 for (i = 0; i < nb_events; i++) 906 m[i] = (struct rte_mbuf *)ev[i].mbuf; 907 908 return rte_eth_tx_burst(m0->port, qid, m, nb_events); 909 } 910 911 static uint16_t 912 dpaa_eventdev_txa_enqueue(void *port, 913 struct rte_event ev[], 914 uint16_t nb_events) 915 { 916 struct rte_mbuf *m = (struct rte_mbuf *)ev[0].mbuf; 917 uint8_t qid, i; 918 919 RTE_SET_USED(port); 920 921 for (i = 0; i < nb_events; i++) { 922 qid = rte_event_eth_tx_adapter_txq_get(m); 923 rte_eth_tx_burst(m->port, qid, &m, 1); 924 } 925 926 return nb_events; 927 } 928 929 static struct eventdev_ops dpaa_eventdev_ops = { 930 .dev_infos_get = dpaa_event_dev_info_get, 931 .dev_configure = dpaa_event_dev_configure, 932 .dev_start = dpaa_event_dev_start, 933 .dev_stop = dpaa_event_dev_stop, 934 .dev_close = dpaa_event_dev_close, 935 .queue_def_conf = dpaa_event_queue_def_conf, 936 .queue_setup = dpaa_event_queue_setup, 937 .queue_release = dpaa_event_queue_release, 938 .port_def_conf = dpaa_event_port_default_conf_get, 939 .port_setup = dpaa_event_port_setup, 940 .port_release = dpaa_event_port_release, 941 .port_link = dpaa_event_port_link, 942 .port_unlink = dpaa_event_port_unlink, 943 .timeout_ticks = dpaa_event_dequeue_timeout_ticks, 944 .eth_rx_adapter_caps_get = dpaa_event_eth_rx_adapter_caps_get, 945 .eth_rx_adapter_queue_add = dpaa_event_eth_rx_adapter_queue_add, 946 .eth_rx_adapter_queue_del = dpaa_event_eth_rx_adapter_queue_del, 947 .eth_rx_adapter_start = dpaa_event_eth_rx_adapter_start, 948 .eth_rx_adapter_stop = dpaa_event_eth_rx_adapter_stop, 949 .eth_tx_adapter_caps_get = dpaa_eventdev_tx_adapter_caps, 950 .eth_tx_adapter_create = dpaa_eventdev_tx_adapter_create, 951 .crypto_adapter_caps_get = dpaa_eventdev_crypto_caps_get, 952 .crypto_adapter_queue_pair_add = dpaa_eventdev_crypto_queue_add, 953 .crypto_adapter_queue_pair_del = dpaa_eventdev_crypto_queue_del, 954 .crypto_adapter_start = dpaa_eventdev_crypto_start, 955 .crypto_adapter_stop = dpaa_eventdev_crypto_stop, 956 }; 957 958 static int flag_check_handler(__rte_unused const char *key, 959 const char *value, __rte_unused void *opaque) 960 { 961 if (strcmp(value, "1")) 962 return -1; 963 964 return 0; 965 } 966 967 static int 968 dpaa_event_check_flags(const char *params) 969 { 970 struct rte_kvargs *kvlist; 971 972 if (params == NULL || params[0] == '\0') 973 return 0; 974 975 kvlist = rte_kvargs_parse(params, NULL); 976 if (kvlist == NULL) 977 return 0; 978 979 if (!rte_kvargs_count(kvlist, DISABLE_INTR_MODE)) { 980 rte_kvargs_free(kvlist); 981 return 0; 982 } 983 /* INTR MODE is disabled when there's key-value pair: disable_intr = 1*/ 984 if (rte_kvargs_process(kvlist, DISABLE_INTR_MODE, 985 flag_check_handler, NULL) < 0) { 986 rte_kvargs_free(kvlist); 987 return 0; 988 } 989 rte_kvargs_free(kvlist); 990 991 return 1; 992 } 993 994 static int 995 dpaa_event_dev_create(const char *name, const char *params) 996 { 997 struct rte_eventdev *eventdev; 998 struct dpaa_eventdev *priv; 999 1000 eventdev = rte_event_pmd_vdev_init(name, 1001 sizeof(struct dpaa_eventdev), 1002 rte_socket_id()); 1003 if (eventdev == NULL) { 1004 DPAA_EVENTDEV_ERR("Failed to create eventdev vdev %s", name); 1005 goto fail; 1006 } 1007 priv = eventdev->data->dev_private; 1008 1009 eventdev->dev_ops = &dpaa_eventdev_ops; 1010 eventdev->enqueue = dpaa_event_enqueue; 1011 eventdev->enqueue_burst = dpaa_event_enqueue_burst; 1012 1013 if (dpaa_event_check_flags(params)) { 1014 eventdev->dequeue = dpaa_event_dequeue; 1015 eventdev->dequeue_burst = dpaa_event_dequeue_burst; 1016 } else { 1017 priv->intr_mode = 1; 1018 eventdev->dev_ops->timeout_ticks = 1019 dpaa_event_dequeue_timeout_ticks_intr; 1020 eventdev->dequeue = dpaa_event_dequeue_intr; 1021 eventdev->dequeue_burst = dpaa_event_dequeue_burst_intr; 1022 } 1023 eventdev->txa_enqueue = dpaa_eventdev_txa_enqueue; 1024 eventdev->txa_enqueue_same_dest = dpaa_eventdev_txa_enqueue_same_dest; 1025 1026 RTE_LOG(INFO, PMD, "%s eventdev added", name); 1027 1028 /* For secondary processes, the primary has done all the work */ 1029 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1030 goto done; 1031 1032 priv->max_event_queues = DPAA_EVENT_MAX_QUEUES; 1033 1034 done: 1035 event_dev_probing_finish(eventdev); 1036 return 0; 1037 fail: 1038 return -EFAULT; 1039 } 1040 1041 static int 1042 dpaa_event_dev_probe(struct rte_vdev_device *vdev) 1043 { 1044 const char *name; 1045 const char *params; 1046 1047 name = rte_vdev_device_name(vdev); 1048 DPAA_EVENTDEV_INFO("Initializing %s", name); 1049 1050 params = rte_vdev_device_args(vdev); 1051 1052 return dpaa_event_dev_create(name, params); 1053 } 1054 1055 static int 1056 dpaa_event_dev_remove(struct rte_vdev_device *vdev) 1057 { 1058 const char *name; 1059 1060 name = rte_vdev_device_name(vdev); 1061 DPAA_EVENTDEV_INFO("Closing %s", name); 1062 1063 return rte_event_pmd_vdev_uninit(name); 1064 } 1065 1066 static struct rte_vdev_driver vdev_eventdev_dpaa_pmd = { 1067 .probe = dpaa_event_dev_probe, 1068 .remove = dpaa_event_dev_remove 1069 }; 1070 1071 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA_PMD, vdev_eventdev_dpaa_pmd); 1072 RTE_PMD_REGISTER_PARAM_STRING(EVENTDEV_NAME_DPAA_PMD, 1073 DISABLE_INTR_MODE "=<int>"); 1074