1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 NXP 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/epoll.h> 12 13 #include <rte_atomic.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_debug.h> 17 #include <rte_dev.h> 18 #include <rte_eal.h> 19 #include <rte_lcore.h> 20 #include <rte_log.h> 21 #include <rte_malloc.h> 22 #include <rte_memcpy.h> 23 #include <rte_memory.h> 24 #include <rte_memzone.h> 25 #include <rte_pci.h> 26 #include <rte_eventdev.h> 27 #include <rte_eventdev_pmd_vdev.h> 28 #include <rte_ethdev.h> 29 #include <rte_event_eth_rx_adapter.h> 30 #include <rte_cryptodev.h> 31 #include <rte_dpaa_bus.h> 32 #include <rte_dpaa_logs.h> 33 #include <rte_cycles.h> 34 #include <rte_kvargs.h> 35 36 #include <dpaa_ethdev.h> 37 #include <dpaa_sec_event.h> 38 #include "dpaa_eventdev.h" 39 #include <dpaa_mempool.h> 40 41 /* 42 * Clarifications 43 * Evendev = Virtual Instance for SoC 44 * Eventport = Portal Instance 45 * Eventqueue = Channel Instance 46 * 1 Eventdev can have N Eventqueue 47 */ 48 49 #define DISABLE_INTR_MODE "disable_intr" 50 51 static int 52 dpaa_event_dequeue_timeout_ticks(struct rte_eventdev *dev, uint64_t ns, 53 uint64_t *timeout_ticks) 54 { 55 EVENTDEV_INIT_FUNC_TRACE(); 56 57 RTE_SET_USED(dev); 58 59 uint64_t cycles_per_second; 60 61 cycles_per_second = rte_get_timer_hz(); 62 *timeout_ticks = (ns * cycles_per_second) / NS_PER_S; 63 64 return 0; 65 } 66 67 static int 68 dpaa_event_dequeue_timeout_ticks_intr(struct rte_eventdev *dev, uint64_t ns, 69 uint64_t *timeout_ticks) 70 { 71 RTE_SET_USED(dev); 72 73 *timeout_ticks = ns/1000; 74 return 0; 75 } 76 77 static void 78 dpaa_eventq_portal_add(u16 ch_id) 79 { 80 uint32_t sdqcr; 81 82 sdqcr = QM_SDQCR_CHANNELS_POOL_CONV(ch_id); 83 qman_static_dequeue_add(sdqcr, NULL); 84 } 85 86 static uint16_t 87 dpaa_event_enqueue_burst(void *port, const struct rte_event ev[], 88 uint16_t nb_events) 89 { 90 uint16_t i; 91 struct rte_mbuf *mbuf; 92 93 RTE_SET_USED(port); 94 /*Release all the contexts saved previously*/ 95 for (i = 0; i < nb_events; i++) { 96 switch (ev[i].op) { 97 case RTE_EVENT_OP_RELEASE: 98 qman_dca_index(ev[i].impl_opaque, 0); 99 mbuf = DPAA_PER_LCORE_DQRR_MBUF(i); 100 mbuf->seqn = DPAA_INVALID_MBUF_SEQN; 101 DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i); 102 DPAA_PER_LCORE_DQRR_SIZE--; 103 break; 104 default: 105 break; 106 } 107 } 108 109 return nb_events; 110 } 111 112 static uint16_t 113 dpaa_event_enqueue(void *port, const struct rte_event *ev) 114 { 115 return dpaa_event_enqueue_burst(port, ev, 1); 116 } 117 118 static void drain_4_bytes(int fd, fd_set *fdset) 119 { 120 if (FD_ISSET(fd, fdset)) { 121 /* drain 4 bytes */ 122 uint32_t junk; 123 ssize_t sjunk = read(qman_thread_fd(), &junk, sizeof(junk)); 124 if (sjunk != sizeof(junk)) 125 DPAA_EVENTDEV_ERR("UIO irq read error"); 126 } 127 } 128 129 static inline int 130 dpaa_event_dequeue_wait(uint64_t timeout_ticks) 131 { 132 int fd_qman, nfds; 133 int ret; 134 fd_set readset; 135 136 /* Go into (and back out of) IRQ mode for each select, 137 * it simplifies exit-path considerations and other 138 * potential nastiness. 139 */ 140 struct timeval tv = { 141 .tv_sec = timeout_ticks / 1000000, 142 .tv_usec = timeout_ticks % 1000000 143 }; 144 145 fd_qman = qman_thread_fd(); 146 nfds = fd_qman + 1; 147 FD_ZERO(&readset); 148 FD_SET(fd_qman, &readset); 149 150 qman_irqsource_add(QM_PIRQ_DQRI); 151 152 ret = select(nfds, &readset, NULL, NULL, &tv); 153 if (ret < 0) 154 return ret; 155 /* Calling irqsource_remove() prior to thread_irq() 156 * means thread_irq() will not process whatever caused 157 * the interrupts, however it does ensure that, once 158 * thread_irq() re-enables interrupts, they won't fire 159 * again immediately. 160 */ 161 qman_irqsource_remove(~0); 162 drain_4_bytes(fd_qman, &readset); 163 qman_thread_irq(); 164 165 return ret; 166 } 167 168 static uint16_t 169 dpaa_event_dequeue_burst(void *port, struct rte_event ev[], 170 uint16_t nb_events, uint64_t timeout_ticks) 171 { 172 int ret; 173 u16 ch_id; 174 void *buffers[8]; 175 u32 num_frames, i, irq = 0; 176 uint64_t cur_ticks = 0, wait_time_ticks = 0; 177 struct dpaa_port *portal = (struct dpaa_port *)port; 178 struct rte_mbuf *mbuf; 179 180 if (unlikely(!RTE_PER_LCORE(dpaa_io))) { 181 /* Affine current thread context to a qman portal */ 182 ret = rte_dpaa_portal_init((void *)0); 183 if (ret) { 184 DPAA_EVENTDEV_ERR("Unable to initialize portal"); 185 return ret; 186 } 187 } 188 189 if (unlikely(!portal->is_port_linked)) { 190 /* 191 * Affine event queue for current thread context 192 * to a qman portal. 193 */ 194 for (i = 0; i < portal->num_linked_evq; i++) { 195 ch_id = portal->evq_info[i].ch_id; 196 dpaa_eventq_portal_add(ch_id); 197 } 198 portal->is_port_linked = true; 199 } 200 201 /* Check if there are atomic contexts to be released */ 202 i = 0; 203 while (DPAA_PER_LCORE_DQRR_SIZE) { 204 if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) { 205 qman_dca_index(i, 0); 206 mbuf = DPAA_PER_LCORE_DQRR_MBUF(i); 207 mbuf->seqn = DPAA_INVALID_MBUF_SEQN; 208 DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i); 209 DPAA_PER_LCORE_DQRR_SIZE--; 210 } 211 i++; 212 } 213 DPAA_PER_LCORE_DQRR_HELD = 0; 214 215 if (timeout_ticks) 216 wait_time_ticks = timeout_ticks; 217 else 218 wait_time_ticks = portal->timeout_us; 219 220 wait_time_ticks += rte_get_timer_cycles(); 221 do { 222 /* Lets dequeue the frames */ 223 num_frames = qman_portal_dequeue(ev, nb_events, buffers); 224 if (irq) 225 irq = 0; 226 if (num_frames) 227 break; 228 cur_ticks = rte_get_timer_cycles(); 229 } while (cur_ticks < wait_time_ticks); 230 231 return num_frames; 232 } 233 234 static uint16_t 235 dpaa_event_dequeue(void *port, struct rte_event *ev, uint64_t timeout_ticks) 236 { 237 return dpaa_event_dequeue_burst(port, ev, 1, timeout_ticks); 238 } 239 240 static uint16_t 241 dpaa_event_dequeue_burst_intr(void *port, struct rte_event ev[], 242 uint16_t nb_events, uint64_t timeout_ticks) 243 { 244 int ret; 245 u16 ch_id; 246 void *buffers[8]; 247 u32 num_frames, i, irq = 0; 248 uint64_t cur_ticks = 0, wait_time_ticks = 0; 249 struct dpaa_port *portal = (struct dpaa_port *)port; 250 struct rte_mbuf *mbuf; 251 252 if (unlikely(!RTE_PER_LCORE(dpaa_io))) { 253 /* Affine current thread context to a qman portal */ 254 ret = rte_dpaa_portal_init((void *)0); 255 if (ret) { 256 DPAA_EVENTDEV_ERR("Unable to initialize portal"); 257 return ret; 258 } 259 } 260 261 if (unlikely(!portal->is_port_linked)) { 262 /* 263 * Affine event queue for current thread context 264 * to a qman portal. 265 */ 266 for (i = 0; i < portal->num_linked_evq; i++) { 267 ch_id = portal->evq_info[i].ch_id; 268 dpaa_eventq_portal_add(ch_id); 269 } 270 portal->is_port_linked = true; 271 } 272 273 /* Check if there are atomic contexts to be released */ 274 i = 0; 275 while (DPAA_PER_LCORE_DQRR_SIZE) { 276 if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) { 277 qman_dca_index(i, 0); 278 mbuf = DPAA_PER_LCORE_DQRR_MBUF(i); 279 mbuf->seqn = DPAA_INVALID_MBUF_SEQN; 280 DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i); 281 DPAA_PER_LCORE_DQRR_SIZE--; 282 } 283 i++; 284 } 285 DPAA_PER_LCORE_DQRR_HELD = 0; 286 287 if (timeout_ticks) 288 wait_time_ticks = timeout_ticks; 289 else 290 wait_time_ticks = portal->timeout_us; 291 292 do { 293 /* Lets dequeue the frames */ 294 num_frames = qman_portal_dequeue(ev, nb_events, buffers); 295 if (irq) 296 irq = 0; 297 if (num_frames) 298 break; 299 if (wait_time_ticks) { /* wait for time */ 300 if (dpaa_event_dequeue_wait(wait_time_ticks) > 0) { 301 irq = 1; 302 continue; 303 } 304 break; /* no event after waiting */ 305 } 306 cur_ticks = rte_get_timer_cycles(); 307 } while (cur_ticks < wait_time_ticks); 308 309 return num_frames; 310 } 311 312 static uint16_t 313 dpaa_event_dequeue_intr(void *port, 314 struct rte_event *ev, 315 uint64_t timeout_ticks) 316 { 317 return dpaa_event_dequeue_burst_intr(port, ev, 1, timeout_ticks); 318 } 319 320 static void 321 dpaa_event_dev_info_get(struct rte_eventdev *dev, 322 struct rte_event_dev_info *dev_info) 323 { 324 EVENTDEV_INIT_FUNC_TRACE(); 325 326 RTE_SET_USED(dev); 327 dev_info->driver_name = "event_dpaa1"; 328 dev_info->min_dequeue_timeout_ns = 329 DPAA_EVENT_MIN_DEQUEUE_TIMEOUT; 330 dev_info->max_dequeue_timeout_ns = 331 DPAA_EVENT_MAX_DEQUEUE_TIMEOUT; 332 dev_info->dequeue_timeout_ns = 333 DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_NS; 334 dev_info->max_event_queues = 335 DPAA_EVENT_MAX_QUEUES; 336 dev_info->max_event_queue_flows = 337 DPAA_EVENT_MAX_QUEUE_FLOWS; 338 dev_info->max_event_queue_priority_levels = 339 DPAA_EVENT_MAX_QUEUE_PRIORITY_LEVELS; 340 dev_info->max_event_priority_levels = 341 DPAA_EVENT_MAX_EVENT_PRIORITY_LEVELS; 342 dev_info->max_event_ports = 343 DPAA_EVENT_MAX_EVENT_PORT; 344 dev_info->max_event_port_dequeue_depth = 345 DPAA_EVENT_MAX_PORT_DEQUEUE_DEPTH; 346 dev_info->max_event_port_enqueue_depth = 347 DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH; 348 /* 349 * TODO: Need to find out that how to fetch this info 350 * from kernel or somewhere else. 351 */ 352 dev_info->max_num_events = 353 DPAA_EVENT_MAX_NUM_EVENTS; 354 dev_info->event_dev_cap = 355 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED | 356 RTE_EVENT_DEV_CAP_BURST_MODE | 357 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT | 358 RTE_EVENT_DEV_CAP_NONSEQ_MODE; 359 } 360 361 static int 362 dpaa_event_dev_configure(const struct rte_eventdev *dev) 363 { 364 struct dpaa_eventdev *priv = dev->data->dev_private; 365 struct rte_event_dev_config *conf = &dev->data->dev_conf; 366 int ret, i; 367 uint32_t *ch_id; 368 369 EVENTDEV_INIT_FUNC_TRACE(); 370 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns; 371 priv->nb_events_limit = conf->nb_events_limit; 372 priv->nb_event_queues = conf->nb_event_queues; 373 priv->nb_event_ports = conf->nb_event_ports; 374 priv->nb_event_queue_flows = conf->nb_event_queue_flows; 375 priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth; 376 priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth; 377 priv->event_dev_cfg = conf->event_dev_cfg; 378 379 ch_id = rte_malloc("dpaa-channels", 380 sizeof(uint32_t) * priv->nb_event_queues, 381 RTE_CACHE_LINE_SIZE); 382 if (ch_id == NULL) { 383 DPAA_EVENTDEV_ERR("Fail to allocate memory for dpaa channels\n"); 384 return -ENOMEM; 385 } 386 /* Create requested event queues within the given event device */ 387 ret = qman_alloc_pool_range(ch_id, priv->nb_event_queues, 1, 0); 388 if (ret < 0) { 389 DPAA_EVENTDEV_ERR("qman_alloc_pool_range %u, err =%d\n", 390 priv->nb_event_queues, ret); 391 rte_free(ch_id); 392 return ret; 393 } 394 for (i = 0; i < priv->nb_event_queues; i++) 395 priv->evq_info[i].ch_id = (u16)ch_id[i]; 396 397 /* Lets prepare event ports */ 398 memset(&priv->ports[0], 0, 399 sizeof(struct dpaa_port) * priv->nb_event_ports); 400 401 /* Check dequeue timeout method is per dequeue or global */ 402 if (priv->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) { 403 /* 404 * Use timeout value as given in dequeue operation. 405 * So invalidating this timeout value. 406 */ 407 priv->dequeue_timeout_ns = 0; 408 409 } else if (conf->dequeue_timeout_ns == 0) { 410 priv->dequeue_timeout_ns = DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_NS; 411 } else { 412 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns; 413 } 414 415 for (i = 0; i < priv->nb_event_ports; i++) { 416 if (priv->intr_mode) { 417 priv->ports[i].timeout_us = 418 priv->dequeue_timeout_ns/1000; 419 } else { 420 uint64_t cycles_per_second; 421 422 cycles_per_second = rte_get_timer_hz(); 423 priv->ports[i].timeout_us = 424 (priv->dequeue_timeout_ns * cycles_per_second) 425 / NS_PER_S; 426 } 427 } 428 429 /* 430 * TODO: Currently portals are affined with threads. Maximum threads 431 * can be created equals to number of lcore. 432 */ 433 rte_free(ch_id); 434 DPAA_EVENTDEV_INFO("Configured eventdev devid=%d", dev->data->dev_id); 435 436 return 0; 437 } 438 439 static int 440 dpaa_event_dev_start(struct rte_eventdev *dev) 441 { 442 EVENTDEV_INIT_FUNC_TRACE(); 443 RTE_SET_USED(dev); 444 445 return 0; 446 } 447 448 static void 449 dpaa_event_dev_stop(struct rte_eventdev *dev) 450 { 451 EVENTDEV_INIT_FUNC_TRACE(); 452 RTE_SET_USED(dev); 453 } 454 455 static int 456 dpaa_event_dev_close(struct rte_eventdev *dev) 457 { 458 EVENTDEV_INIT_FUNC_TRACE(); 459 RTE_SET_USED(dev); 460 461 return 0; 462 } 463 464 static void 465 dpaa_event_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id, 466 struct rte_event_queue_conf *queue_conf) 467 { 468 EVENTDEV_INIT_FUNC_TRACE(); 469 470 RTE_SET_USED(dev); 471 RTE_SET_USED(queue_id); 472 473 memset(queue_conf, 0, sizeof(struct rte_event_queue_conf)); 474 queue_conf->schedule_type = RTE_SCHED_TYPE_PARALLEL; 475 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_HIGHEST; 476 } 477 478 static int 479 dpaa_event_queue_setup(struct rte_eventdev *dev, uint8_t queue_id, 480 const struct rte_event_queue_conf *queue_conf) 481 { 482 struct dpaa_eventdev *priv = dev->data->dev_private; 483 struct dpaa_eventq *evq_info = &priv->evq_info[queue_id]; 484 485 EVENTDEV_INIT_FUNC_TRACE(); 486 487 switch (queue_conf->schedule_type) { 488 case RTE_SCHED_TYPE_PARALLEL: 489 case RTE_SCHED_TYPE_ATOMIC: 490 break; 491 case RTE_SCHED_TYPE_ORDERED: 492 DPAA_EVENTDEV_ERR("Schedule type is not supported."); 493 return -1; 494 } 495 evq_info->event_queue_cfg = queue_conf->event_queue_cfg; 496 evq_info->event_queue_id = queue_id; 497 498 return 0; 499 } 500 501 static void 502 dpaa_event_queue_release(struct rte_eventdev *dev, uint8_t queue_id) 503 { 504 EVENTDEV_INIT_FUNC_TRACE(); 505 506 RTE_SET_USED(dev); 507 RTE_SET_USED(queue_id); 508 } 509 510 static void 511 dpaa_event_port_default_conf_get(struct rte_eventdev *dev, uint8_t port_id, 512 struct rte_event_port_conf *port_conf) 513 { 514 EVENTDEV_INIT_FUNC_TRACE(); 515 516 RTE_SET_USED(dev); 517 RTE_SET_USED(port_id); 518 519 port_conf->new_event_threshold = DPAA_EVENT_MAX_NUM_EVENTS; 520 port_conf->dequeue_depth = DPAA_EVENT_MAX_PORT_DEQUEUE_DEPTH; 521 port_conf->enqueue_depth = DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH; 522 } 523 524 static int 525 dpaa_event_port_setup(struct rte_eventdev *dev, uint8_t port_id, 526 const struct rte_event_port_conf *port_conf) 527 { 528 struct dpaa_eventdev *eventdev = dev->data->dev_private; 529 530 EVENTDEV_INIT_FUNC_TRACE(); 531 532 RTE_SET_USED(port_conf); 533 dev->data->ports[port_id] = &eventdev->ports[port_id]; 534 535 return 0; 536 } 537 538 static void 539 dpaa_event_port_release(void *port) 540 { 541 EVENTDEV_INIT_FUNC_TRACE(); 542 543 RTE_SET_USED(port); 544 } 545 546 static int 547 dpaa_event_port_link(struct rte_eventdev *dev, void *port, 548 const uint8_t queues[], const uint8_t priorities[], 549 uint16_t nb_links) 550 { 551 struct dpaa_eventdev *priv = dev->data->dev_private; 552 struct dpaa_port *event_port = (struct dpaa_port *)port; 553 struct dpaa_eventq *event_queue; 554 uint8_t eventq_id; 555 int i; 556 557 RTE_SET_USED(dev); 558 RTE_SET_USED(priorities); 559 560 /* First check that input configuration are valid */ 561 for (i = 0; i < nb_links; i++) { 562 eventq_id = queues[i]; 563 event_queue = &priv->evq_info[eventq_id]; 564 if ((event_queue->event_queue_cfg 565 & RTE_EVENT_QUEUE_CFG_SINGLE_LINK) 566 && (event_queue->event_port)) { 567 return -EINVAL; 568 } 569 } 570 571 for (i = 0; i < nb_links; i++) { 572 eventq_id = queues[i]; 573 event_queue = &priv->evq_info[eventq_id]; 574 event_port->evq_info[i].event_queue_id = eventq_id; 575 event_port->evq_info[i].ch_id = event_queue->ch_id; 576 event_queue->event_port = port; 577 } 578 579 event_port->num_linked_evq = event_port->num_linked_evq + i; 580 581 return (int)i; 582 } 583 584 static int 585 dpaa_event_port_unlink(struct rte_eventdev *dev, void *port, 586 uint8_t queues[], uint16_t nb_links) 587 { 588 int i; 589 uint8_t eventq_id; 590 struct dpaa_eventq *event_queue; 591 struct dpaa_eventdev *priv = dev->data->dev_private; 592 struct dpaa_port *event_port = (struct dpaa_port *)port; 593 594 if (!event_port->num_linked_evq) 595 return nb_links; 596 597 for (i = 0; i < nb_links; i++) { 598 eventq_id = queues[i]; 599 event_port->evq_info[eventq_id].event_queue_id = -1; 600 event_port->evq_info[eventq_id].ch_id = 0; 601 event_queue = &priv->evq_info[eventq_id]; 602 event_queue->event_port = NULL; 603 } 604 605 if (event_port->num_linked_evq) 606 event_port->num_linked_evq = event_port->num_linked_evq - i; 607 608 return (int)i; 609 } 610 611 static int 612 dpaa_event_eth_rx_adapter_caps_get(const struct rte_eventdev *dev, 613 const struct rte_eth_dev *eth_dev, 614 uint32_t *caps) 615 { 616 const char *ethdev_driver = eth_dev->device->driver->name; 617 618 EVENTDEV_INIT_FUNC_TRACE(); 619 620 RTE_SET_USED(dev); 621 622 if (!strcmp(ethdev_driver, "net_dpaa")) 623 *caps = RTE_EVENT_ETH_RX_ADAPTER_DPAA_CAP; 624 else 625 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP; 626 627 return 0; 628 } 629 630 static int 631 dpaa_event_eth_rx_adapter_queue_add( 632 const struct rte_eventdev *dev, 633 const struct rte_eth_dev *eth_dev, 634 int32_t rx_queue_id, 635 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 636 { 637 struct dpaa_eventdev *eventdev = dev->data->dev_private; 638 uint8_t ev_qid = queue_conf->ev.queue_id; 639 u16 ch_id = eventdev->evq_info[ev_qid].ch_id; 640 struct dpaa_if *dpaa_intf = eth_dev->data->dev_private; 641 int ret, i; 642 643 EVENTDEV_INIT_FUNC_TRACE(); 644 645 if (rx_queue_id == -1) { 646 for (i = 0; i < dpaa_intf->nb_rx_queues; i++) { 647 ret = dpaa_eth_eventq_attach(eth_dev, i, ch_id, 648 queue_conf); 649 if (ret) { 650 DPAA_EVENTDEV_ERR( 651 "Event Queue attach failed:%d\n", ret); 652 goto detach_configured_queues; 653 } 654 } 655 return 0; 656 } 657 658 ret = dpaa_eth_eventq_attach(eth_dev, rx_queue_id, ch_id, queue_conf); 659 if (ret) 660 DPAA_EVENTDEV_ERR("dpaa_eth_eventq_attach failed:%d\n", ret); 661 return ret; 662 663 detach_configured_queues: 664 665 for (i = (i - 1); i >= 0 ; i--) 666 dpaa_eth_eventq_detach(eth_dev, i); 667 668 return ret; 669 } 670 671 static int 672 dpaa_event_eth_rx_adapter_queue_del(const struct rte_eventdev *dev, 673 const struct rte_eth_dev *eth_dev, 674 int32_t rx_queue_id) 675 { 676 int ret, i; 677 struct dpaa_if *dpaa_intf = eth_dev->data->dev_private; 678 679 EVENTDEV_INIT_FUNC_TRACE(); 680 681 RTE_SET_USED(dev); 682 if (rx_queue_id == -1) { 683 for (i = 0; i < dpaa_intf->nb_rx_queues; i++) { 684 ret = dpaa_eth_eventq_detach(eth_dev, i); 685 if (ret) 686 DPAA_EVENTDEV_ERR( 687 "Event Queue detach failed:%d\n", ret); 688 } 689 690 return 0; 691 } 692 693 ret = dpaa_eth_eventq_detach(eth_dev, rx_queue_id); 694 if (ret) 695 DPAA_EVENTDEV_ERR("dpaa_eth_eventq_detach failed:%d\n", ret); 696 return ret; 697 } 698 699 static int 700 dpaa_event_eth_rx_adapter_start(const struct rte_eventdev *dev, 701 const struct rte_eth_dev *eth_dev) 702 { 703 EVENTDEV_INIT_FUNC_TRACE(); 704 705 RTE_SET_USED(dev); 706 RTE_SET_USED(eth_dev); 707 708 return 0; 709 } 710 711 static int 712 dpaa_event_eth_rx_adapter_stop(const struct rte_eventdev *dev, 713 const struct rte_eth_dev *eth_dev) 714 { 715 EVENTDEV_INIT_FUNC_TRACE(); 716 717 RTE_SET_USED(dev); 718 RTE_SET_USED(eth_dev); 719 720 return 0; 721 } 722 723 static int 724 dpaa_eventdev_crypto_caps_get(const struct rte_eventdev *dev, 725 const struct rte_cryptodev *cdev, 726 uint32_t *caps) 727 { 728 const char *name = cdev->data->name; 729 730 EVENTDEV_INIT_FUNC_TRACE(); 731 732 RTE_SET_USED(dev); 733 734 if (!strncmp(name, "dpaa_sec-", 9)) 735 *caps = RTE_EVENT_CRYPTO_ADAPTER_DPAA_CAP; 736 else 737 return -1; 738 739 return 0; 740 } 741 742 static int 743 dpaa_eventdev_crypto_queue_add_all(const struct rte_eventdev *dev, 744 const struct rte_cryptodev *cryptodev, 745 const struct rte_event *ev) 746 { 747 struct dpaa_eventdev *priv = dev->data->dev_private; 748 uint8_t ev_qid = ev->queue_id; 749 u16 ch_id = priv->evq_info[ev_qid].ch_id; 750 int i, ret; 751 752 EVENTDEV_INIT_FUNC_TRACE(); 753 754 for (i = 0; i < cryptodev->data->nb_queue_pairs; i++) { 755 ret = dpaa_sec_eventq_attach(cryptodev, i, 756 ch_id, ev); 757 if (ret) { 758 DPAA_EVENTDEV_ERR("dpaa_sec_eventq_attach failed: ret %d\n", 759 ret); 760 goto fail; 761 } 762 } 763 return 0; 764 fail: 765 for (i = (i - 1); i >= 0 ; i--) 766 dpaa_sec_eventq_detach(cryptodev, i); 767 768 return ret; 769 } 770 771 static int 772 dpaa_eventdev_crypto_queue_add(const struct rte_eventdev *dev, 773 const struct rte_cryptodev *cryptodev, 774 int32_t rx_queue_id, 775 const struct rte_event *ev) 776 { 777 struct dpaa_eventdev *priv = dev->data->dev_private; 778 uint8_t ev_qid = ev->queue_id; 779 u16 ch_id = priv->evq_info[ev_qid].ch_id; 780 int ret; 781 782 EVENTDEV_INIT_FUNC_TRACE(); 783 784 if (rx_queue_id == -1) 785 return dpaa_eventdev_crypto_queue_add_all(dev, 786 cryptodev, ev); 787 788 ret = dpaa_sec_eventq_attach(cryptodev, rx_queue_id, 789 ch_id, ev); 790 if (ret) { 791 DPAA_EVENTDEV_ERR( 792 "dpaa_sec_eventq_attach failed: ret: %d\n", ret); 793 return ret; 794 } 795 return 0; 796 } 797 798 static int 799 dpaa_eventdev_crypto_queue_del_all(const struct rte_eventdev *dev, 800 const struct rte_cryptodev *cdev) 801 { 802 int i, ret; 803 804 EVENTDEV_INIT_FUNC_TRACE(); 805 806 RTE_SET_USED(dev); 807 808 for (i = 0; i < cdev->data->nb_queue_pairs; i++) { 809 ret = dpaa_sec_eventq_detach(cdev, i); 810 if (ret) { 811 DPAA_EVENTDEV_ERR( 812 "dpaa_sec_eventq_detach failed:ret %d\n", ret); 813 return ret; 814 } 815 } 816 817 return 0; 818 } 819 820 static int 821 dpaa_eventdev_crypto_queue_del(const struct rte_eventdev *dev, 822 const struct rte_cryptodev *cryptodev, 823 int32_t rx_queue_id) 824 { 825 int ret; 826 827 EVENTDEV_INIT_FUNC_TRACE(); 828 829 if (rx_queue_id == -1) 830 return dpaa_eventdev_crypto_queue_del_all(dev, cryptodev); 831 832 ret = dpaa_sec_eventq_detach(cryptodev, rx_queue_id); 833 if (ret) { 834 DPAA_EVENTDEV_ERR( 835 "dpaa_sec_eventq_detach failed: ret: %d\n", ret); 836 return ret; 837 } 838 839 return 0; 840 } 841 842 static int 843 dpaa_eventdev_crypto_start(const struct rte_eventdev *dev, 844 const struct rte_cryptodev *cryptodev) 845 { 846 EVENTDEV_INIT_FUNC_TRACE(); 847 848 RTE_SET_USED(dev); 849 RTE_SET_USED(cryptodev); 850 851 return 0; 852 } 853 854 static int 855 dpaa_eventdev_crypto_stop(const struct rte_eventdev *dev, 856 const struct rte_cryptodev *cryptodev) 857 { 858 EVENTDEV_INIT_FUNC_TRACE(); 859 860 RTE_SET_USED(dev); 861 RTE_SET_USED(cryptodev); 862 863 return 0; 864 } 865 866 static struct rte_eventdev_ops dpaa_eventdev_ops = { 867 .dev_infos_get = dpaa_event_dev_info_get, 868 .dev_configure = dpaa_event_dev_configure, 869 .dev_start = dpaa_event_dev_start, 870 .dev_stop = dpaa_event_dev_stop, 871 .dev_close = dpaa_event_dev_close, 872 .queue_def_conf = dpaa_event_queue_def_conf, 873 .queue_setup = dpaa_event_queue_setup, 874 .queue_release = dpaa_event_queue_release, 875 .port_def_conf = dpaa_event_port_default_conf_get, 876 .port_setup = dpaa_event_port_setup, 877 .port_release = dpaa_event_port_release, 878 .port_link = dpaa_event_port_link, 879 .port_unlink = dpaa_event_port_unlink, 880 .timeout_ticks = dpaa_event_dequeue_timeout_ticks, 881 .eth_rx_adapter_caps_get = dpaa_event_eth_rx_adapter_caps_get, 882 .eth_rx_adapter_queue_add = dpaa_event_eth_rx_adapter_queue_add, 883 .eth_rx_adapter_queue_del = dpaa_event_eth_rx_adapter_queue_del, 884 .eth_rx_adapter_start = dpaa_event_eth_rx_adapter_start, 885 .eth_rx_adapter_stop = dpaa_event_eth_rx_adapter_stop, 886 .crypto_adapter_caps_get = dpaa_eventdev_crypto_caps_get, 887 .crypto_adapter_queue_pair_add = dpaa_eventdev_crypto_queue_add, 888 .crypto_adapter_queue_pair_del = dpaa_eventdev_crypto_queue_del, 889 .crypto_adapter_start = dpaa_eventdev_crypto_start, 890 .crypto_adapter_stop = dpaa_eventdev_crypto_stop, 891 }; 892 893 static int flag_check_handler(__rte_unused const char *key, 894 const char *value, __rte_unused void *opaque) 895 { 896 if (strcmp(value, "1")) 897 return -1; 898 899 return 0; 900 } 901 902 static int 903 dpaa_event_check_flags(const char *params) 904 { 905 struct rte_kvargs *kvlist; 906 907 if (params == NULL || params[0] == '\0') 908 return 0; 909 910 kvlist = rte_kvargs_parse(params, NULL); 911 if (kvlist == NULL) 912 return 0; 913 914 if (!rte_kvargs_count(kvlist, DISABLE_INTR_MODE)) { 915 rte_kvargs_free(kvlist); 916 return 0; 917 } 918 /* INTR MODE is disabled when there's key-value pair: disable_intr = 1*/ 919 if (rte_kvargs_process(kvlist, DISABLE_INTR_MODE, 920 flag_check_handler, NULL) < 0) { 921 rte_kvargs_free(kvlist); 922 return 0; 923 } 924 rte_kvargs_free(kvlist); 925 926 return 1; 927 } 928 929 static int 930 dpaa_event_dev_create(const char *name, const char *params) 931 { 932 struct rte_eventdev *eventdev; 933 struct dpaa_eventdev *priv; 934 935 eventdev = rte_event_pmd_vdev_init(name, 936 sizeof(struct dpaa_eventdev), 937 rte_socket_id()); 938 if (eventdev == NULL) { 939 DPAA_EVENTDEV_ERR("Failed to create eventdev vdev %s", name); 940 goto fail; 941 } 942 priv = eventdev->data->dev_private; 943 944 eventdev->dev_ops = &dpaa_eventdev_ops; 945 eventdev->enqueue = dpaa_event_enqueue; 946 eventdev->enqueue_burst = dpaa_event_enqueue_burst; 947 948 if (dpaa_event_check_flags(params)) { 949 eventdev->dequeue = dpaa_event_dequeue; 950 eventdev->dequeue_burst = dpaa_event_dequeue_burst; 951 } else { 952 priv->intr_mode = 1; 953 eventdev->dev_ops->timeout_ticks = 954 dpaa_event_dequeue_timeout_ticks_intr; 955 eventdev->dequeue = dpaa_event_dequeue_intr; 956 eventdev->dequeue_burst = dpaa_event_dequeue_burst_intr; 957 } 958 959 RTE_LOG(INFO, PMD, "%s eventdev added", name); 960 961 /* For secondary processes, the primary has done all the work */ 962 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 963 return 0; 964 965 priv->max_event_queues = DPAA_EVENT_MAX_QUEUES; 966 967 return 0; 968 fail: 969 return -EFAULT; 970 } 971 972 static int 973 dpaa_event_dev_probe(struct rte_vdev_device *vdev) 974 { 975 const char *name; 976 const char *params; 977 978 name = rte_vdev_device_name(vdev); 979 DPAA_EVENTDEV_INFO("Initializing %s", name); 980 981 params = rte_vdev_device_args(vdev); 982 983 return dpaa_event_dev_create(name, params); 984 } 985 986 static int 987 dpaa_event_dev_remove(struct rte_vdev_device *vdev) 988 { 989 const char *name; 990 991 name = rte_vdev_device_name(vdev); 992 DPAA_EVENTDEV_INFO("Closing %s", name); 993 994 return rte_event_pmd_vdev_uninit(name); 995 } 996 997 static struct rte_vdev_driver vdev_eventdev_dpaa_pmd = { 998 .probe = dpaa_event_dev_probe, 999 .remove = dpaa_event_dev_remove 1000 }; 1001 1002 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA_PMD, vdev_eventdev_dpaa_pmd); 1003 RTE_PMD_REGISTER_PARAM_STRING(EVENTDEV_NAME_DPAA_PMD, 1004 DISABLE_INTR_MODE "=<int>"); 1005