xref: /dpdk/drivers/event/cnxk/tx/cn9k/tx_all_offload.c (revision d46b9fa83f136beb0e6feedd0a7b3a228b0d8cd3)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2022 Marvell.
3  */
4 
5 #include "cn9k_worker.h"
6 
7 #if defined(CNXK_DIS_TMPLT_FUNC)
8 
9 uint16_t __rte_hot
10 cn9k_sso_hws_tx_adptr_enq_seg_all_offload(void *port, struct rte_event ev[], uint16_t nb_events)
11 {
12 	const uint32_t flags =
13 		(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
14 		 NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_MBUF_NOFF_F | NIX_TX_OFFLOAD_TSO_F |
15 		 NIX_TX_OFFLOAD_SECURITY_F | NIX_TX_MULTI_SEG_F);
16 	uint64_t cmd[8 + CNXK_NIX_TX_MSEG_SG_DWORDS - 2];
17 	struct cn9k_sso_hws *ws = port;
18 
19 	RTE_SET_USED(nb_events);
20 	return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, (uint64_t *)ws->tx_adptr_data, flags);
21 }
22 
23 uint16_t __rte_hot
24 cn9k_sso_hws_tx_adptr_enq_dual_seg_all_offload(void *port, struct rte_event ev[],
25 					       uint16_t nb_events)
26 {
27 	const uint32_t flags =
28 		(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
29 		 NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_MBUF_NOFF_F | NIX_TX_OFFLOAD_TSO_F |
30 		 NIX_TX_OFFLOAD_SECURITY_F | NIX_TX_MULTI_SEG_F);
31 	uint64_t cmd[8 + CNXK_NIX_TX_MSEG_SG_DWORDS - 2];
32 	struct cn9k_sso_hws_dual *ws = port;
33 
34 	RTE_SET_USED(nb_events);
35 	return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, (uint64_t *)ws->tx_adptr_data,
36 				     flags);
37 }
38 
39 uint16_t __rte_hot
40 cn9k_sso_hws_tx_adptr_enq_seg_all_offload_tst(void *port, struct rte_event ev[], uint16_t nb_events)
41 {
42 	const uint32_t flags =
43 		(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
44 		 NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_MBUF_NOFF_F | NIX_TX_OFFLOAD_TSO_F |
45 		 NIX_TX_OFFLOAD_TSTAMP_F | NIX_TX_OFFLOAD_SECURITY_F | NIX_TX_MULTI_SEG_F);
46 	uint64_t cmd[8 + CNXK_NIX_TX_MSEG_SG_DWORDS - 2];
47 	struct cn9k_sso_hws *ws = port;
48 
49 	RTE_SET_USED(nb_events);
50 	return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, (uint64_t *)ws->tx_adptr_data, flags);
51 }
52 
53 uint16_t __rte_hot
54 cn9k_sso_hws_tx_adptr_enq_dual_seg_all_offload_tst(void *port, struct rte_event ev[],
55 						   uint16_t nb_events)
56 {
57 	const uint32_t flags =
58 		(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
59 		 NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_MBUF_NOFF_F | NIX_TX_OFFLOAD_TSO_F |
60 		 NIX_TX_OFFLOAD_TSTAMP_F | NIX_TX_OFFLOAD_SECURITY_F | NIX_TX_MULTI_SEG_F);
61 	uint64_t cmd[8 + CNXK_NIX_TX_MSEG_SG_DWORDS - 2];
62 	struct cn9k_sso_hws_dual *ws = port;
63 
64 	RTE_SET_USED(nb_events);
65 	return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, (uint64_t *)ws->tx_adptr_data,
66 				     flags);
67 }
68 
69 #endif
70