1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017-2021 Intel Corporation 3 */ 4 5 #include <rte_cryptodev.h> 6 #include <cryptodev_pmd.h> 7 #include "qat_sym_session.h" 8 #include "qat_sym.h" 9 #include "qat_asym.h" 10 #include "qat_crypto.h" 11 #include "qat_crypto_pmd_gens.h" 12 13 static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = { 14 QAT_SYM_CIPHER_CAP(AES_CBC, 15 CAP_SET(block_size, 16), 16 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)), 17 QAT_SYM_AUTH_CAP(SHA1_HMAC, 18 CAP_SET(block_size, 64), 19 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1), 20 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 21 QAT_SYM_AUTH_CAP(SHA224_HMAC, 22 CAP_SET(block_size, 64), 23 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1), 24 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 25 QAT_SYM_AUTH_CAP(SHA256_HMAC, 26 CAP_SET(block_size, 64), 27 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1), 28 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 29 QAT_SYM_AUTH_CAP(SHA384_HMAC, 30 CAP_SET(block_size, 128), 31 CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1), 32 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 33 QAT_SYM_AUTH_CAP(SHA512_HMAC, 34 CAP_SET(block_size, 128), 35 CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1), 36 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 37 QAT_SYM_AUTH_CAP(AES_XCBC_MAC, 38 CAP_SET(block_size, 16), 39 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0), 40 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 41 QAT_SYM_AUTH_CAP(AES_CMAC, 42 CAP_SET(block_size, 16), 43 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4), 44 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 45 QAT_SYM_CIPHER_CAP(AES_DOCSISBPI, 46 CAP_SET(block_size, 16), 47 CAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)), 48 QAT_SYM_AUTH_CAP(NULL, 49 CAP_SET(block_size, 1), 50 CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size), 51 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 52 QAT_SYM_CIPHER_CAP(NULL, 53 CAP_SET(block_size, 1), 54 CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)), 55 QAT_SYM_PLAIN_AUTH_CAP(SHA1, 56 CAP_SET(block_size, 64), 57 CAP_RNG(digest_size, 1, 20, 1)), 58 QAT_SYM_AUTH_CAP(SHA224, 59 CAP_SET(block_size, 64), 60 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1), 61 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 62 QAT_SYM_AUTH_CAP(SHA256, 63 CAP_SET(block_size, 64), 64 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1), 65 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 66 QAT_SYM_AUTH_CAP(SHA384, 67 CAP_SET(block_size, 128), 68 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1), 69 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 70 QAT_SYM_AUTH_CAP(SHA512, 71 CAP_SET(block_size, 128), 72 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1), 73 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 74 QAT_SYM_CIPHER_CAP(AES_CTR, 75 CAP_SET(block_size, 16), 76 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)), 77 QAT_SYM_AEAD_CAP(AES_GCM, 78 CAP_SET(block_size, 16), 79 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4), 80 CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)), 81 QAT_SYM_AEAD_CAP(AES_CCM, 82 CAP_SET(block_size, 16), 83 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2), 84 CAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)), 85 QAT_SYM_AUTH_CAP(AES_GMAC, 86 CAP_SET(block_size, 16), 87 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4), 88 CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)), 89 QAT_SYM_AEAD_CAP(CHACHA20_POLY1305, 90 CAP_SET(block_size, 64), 91 CAP_RNG(key_size, 32, 32, 0), 92 CAP_RNG(digest_size, 16, 16, 0), 93 CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)), 94 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() 95 }; 96 97 static struct qat_capabilities_info 98 qat_sym_crypto_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused) 99 { 100 struct qat_capabilities_info capa_info; 101 capa_info.data = qat_sym_crypto_caps_gen4; 102 capa_info.size = sizeof(qat_sym_crypto_caps_gen4); 103 return capa_info; 104 } 105 106 RTE_INIT(qat_sym_crypto_gen4_init) 107 { 108 qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; 109 qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = 110 qat_sym_crypto_cap_get_gen4; 111 qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = 112 qat_sym_crypto_feature_flags_get_gen1; 113 #ifdef RTE_LIB_SECURITY 114 qat_sym_gen_dev_ops[QAT_GEN4].create_security_ctx = 115 qat_sym_create_security_gen1; 116 #endif 117 } 118 119 RTE_INIT(qat_asym_crypto_gen4_init) 120 { 121 qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = NULL; 122 qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = NULL; 123 qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = NULL; 124 } 125