1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017-2021 Intel Corporation 3 */ 4 5 #include <rte_cryptodev.h> 6 #include <cryptodev_pmd.h> 7 #include "qat_sym_session.h" 8 #include "qat_sym.h" 9 #include "qat_asym.h" 10 #include "qat_crypto.h" 11 #include "qat_crypto_pmd_gens.h" 12 13 static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = { 14 QAT_SYM_PLAIN_AUTH_CAP(SHA1, 15 CAP_SET(block_size, 64), 16 CAP_RNG(digest_size, 1, 20, 1)), 17 QAT_SYM_AEAD_CAP(AES_GCM, 18 CAP_SET(block_size, 16), 19 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4), 20 CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)), 21 QAT_SYM_AEAD_CAP(AES_CCM, 22 CAP_SET(block_size, 16), 23 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2), 24 CAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)), 25 QAT_SYM_AUTH_CAP(AES_GMAC, 26 CAP_SET(block_size, 16), 27 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4), 28 CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)), 29 QAT_SYM_AUTH_CAP(AES_CMAC, 30 CAP_SET(block_size, 16), 31 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4), 32 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 33 QAT_SYM_AUTH_CAP(SHA224, 34 CAP_SET(block_size, 64), 35 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1), 36 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 37 QAT_SYM_AUTH_CAP(SHA256, 38 CAP_SET(block_size, 64), 39 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1), 40 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 41 QAT_SYM_AUTH_CAP(SHA384, 42 CAP_SET(block_size, 128), 43 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1), 44 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 45 QAT_SYM_AUTH_CAP(SHA512, 46 CAP_SET(block_size, 128), 47 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1), 48 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 49 QAT_SYM_AUTH_CAP(SHA1_HMAC, 50 CAP_SET(block_size, 64), 51 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1), 52 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 53 QAT_SYM_AUTH_CAP(SHA224_HMAC, 54 CAP_SET(block_size, 64), 55 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1), 56 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 57 QAT_SYM_AUTH_CAP(SHA256_HMAC, 58 CAP_SET(block_size, 64), 59 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1), 60 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 61 QAT_SYM_AUTH_CAP(SHA384_HMAC, 62 CAP_SET(block_size, 128), 63 CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1), 64 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 65 QAT_SYM_AUTH_CAP(SHA512_HMAC, 66 CAP_SET(block_size, 128), 67 CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1), 68 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 69 QAT_SYM_AUTH_CAP(MD5_HMAC, 70 CAP_SET(block_size, 64), 71 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 16, 1), 72 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 73 QAT_SYM_AUTH_CAP(AES_XCBC_MAC, 74 CAP_SET(block_size, 16), 75 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0), 76 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 77 QAT_SYM_AUTH_CAP(SNOW3G_UIA2, 78 CAP_SET(block_size, 16), 79 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0), 80 CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)), 81 QAT_SYM_AUTH_CAP(KASUMI_F9, 82 CAP_SET(block_size, 8), 83 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0), 84 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 85 QAT_SYM_AUTH_CAP(NULL, 86 CAP_SET(block_size, 1), 87 CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size), 88 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 89 QAT_SYM_CIPHER_CAP(AES_CBC, 90 CAP_SET(block_size, 16), 91 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)), 92 QAT_SYM_CIPHER_CAP(AES_CTR, 93 CAP_SET(block_size, 16), 94 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)), 95 QAT_SYM_CIPHER_CAP(AES_XTS, 96 CAP_SET(block_size, 16), 97 CAP_RNG(key_size, 32, 64, 32), CAP_RNG(iv_size, 16, 16, 0)), 98 QAT_SYM_CIPHER_CAP(AES_DOCSISBPI, 99 CAP_SET(block_size, 16), 100 CAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)), 101 QAT_SYM_CIPHER_CAP(SNOW3G_UEA2, 102 CAP_SET(block_size, 16), 103 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), 104 QAT_SYM_CIPHER_CAP(KASUMI_F8, 105 CAP_SET(block_size, 8), 106 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 8, 8, 0)), 107 QAT_SYM_CIPHER_CAP(NULL, 108 CAP_SET(block_size, 1), 109 CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)), 110 QAT_SYM_CIPHER_CAP(3DES_CBC, 111 CAP_SET(block_size, 8), 112 CAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)), 113 QAT_SYM_CIPHER_CAP(3DES_CTR, 114 CAP_SET(block_size, 8), 115 CAP_RNG(key_size, 16, 24, 8), CAP_RNG(iv_size, 8, 8, 0)), 116 QAT_SYM_CIPHER_CAP(DES_CBC, 117 CAP_SET(block_size, 8), 118 CAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)), 119 QAT_SYM_CIPHER_CAP(DES_DOCSISBPI, 120 CAP_SET(block_size, 8), 121 CAP_RNG(key_size, 8, 8, 0), CAP_RNG(iv_size, 8, 8, 0)), 122 QAT_SYM_CIPHER_CAP(ZUC_EEA3, 123 CAP_SET(block_size, 16), 124 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), 125 QAT_SYM_AUTH_CAP(ZUC_EIA3, 126 CAP_SET(block_size, 16), 127 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0), 128 CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)), 129 QAT_SYM_AEAD_CAP(CHACHA20_POLY1305, 130 CAP_SET(block_size, 64), 131 CAP_RNG(key_size, 32, 32, 0), 132 CAP_RNG(digest_size, 16, 16, 0), 133 CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)), 134 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() 135 }; 136 137 static struct qat_capabilities_info 138 qat_sym_crypto_cap_get_gen3(struct qat_pci_device *qat_dev __rte_unused) 139 { 140 struct qat_capabilities_info capa_info; 141 capa_info.data = qat_sym_crypto_caps_gen3; 142 capa_info.size = sizeof(qat_sym_crypto_caps_gen3); 143 return capa_info; 144 } 145 146 RTE_INIT(qat_sym_crypto_gen3_init) 147 { 148 qat_sym_gen_dev_ops[QAT_GEN3].cryptodev_ops = &qat_sym_crypto_ops_gen1; 149 qat_sym_gen_dev_ops[QAT_GEN3].get_capabilities = 150 qat_sym_crypto_cap_get_gen3; 151 qat_sym_gen_dev_ops[QAT_GEN3].get_feature_flags = 152 qat_sym_crypto_feature_flags_get_gen1; 153 #ifdef RTE_LIB_SECURITY 154 qat_sym_gen_dev_ops[QAT_GEN3].create_security_ctx = 155 qat_sym_create_security_gen1; 156 #endif 157 } 158 159 RTE_INIT(qat_asym_crypto_gen3_init) 160 { 161 qat_asym_gen_dev_ops[QAT_GEN3].cryptodev_ops = NULL; 162 qat_asym_gen_dev_ops[QAT_GEN3].get_capabilities = NULL; 163 qat_asym_gen_dev_ops[QAT_GEN3].get_feature_flags = NULL; 164 } 165