1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017-2021 Intel Corporation 3 */ 4 5 #include <rte_cryptodev.h> 6 #include <cryptodev_pmd.h> 7 #include "qat_sym_session.h" 8 #include "qat_sym.h" 9 #include "qat_asym.h" 10 #include "qat_crypto.h" 11 #include "qat_crypto_pmd_gens.h" 12 13 #define MIXED_CRYPTO_MIN_FW_VER 0x04090000 14 15 static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen2[] = { 16 QAT_SYM_PLAIN_AUTH_CAP(SHA1, 17 CAP_SET(block_size, 64), 18 CAP_RNG(digest_size, 1, 20, 1)), 19 QAT_SYM_AEAD_CAP(AES_GCM, 20 CAP_SET(block_size, 16), 21 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4), 22 CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)), 23 QAT_SYM_AEAD_CAP(AES_CCM, 24 CAP_SET(block_size, 16), 25 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2), 26 CAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)), 27 QAT_SYM_AUTH_CAP(AES_GMAC, 28 CAP_SET(block_size, 16), 29 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4), 30 CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)), 31 QAT_SYM_AUTH_CAP(AES_CMAC, 32 CAP_SET(block_size, 16), 33 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4), 34 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 35 QAT_SYM_AUTH_CAP(SHA224, 36 CAP_SET(block_size, 64), 37 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1), 38 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 39 QAT_SYM_AUTH_CAP(SHA256, 40 CAP_SET(block_size, 64), 41 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1), 42 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 43 QAT_SYM_AUTH_CAP(SHA384, 44 CAP_SET(block_size, 128), 45 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1), 46 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 47 QAT_SYM_AUTH_CAP(SHA512, 48 CAP_SET(block_size, 128), 49 CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1), 50 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 51 QAT_SYM_AUTH_CAP(SHA1_HMAC, 52 CAP_SET(block_size, 64), 53 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1), 54 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 55 QAT_SYM_AUTH_CAP(SHA224_HMAC, 56 CAP_SET(block_size, 64), 57 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1), 58 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 59 QAT_SYM_AUTH_CAP(SHA256_HMAC, 60 CAP_SET(block_size, 64), 61 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1), 62 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 63 QAT_SYM_AUTH_CAP(SHA384_HMAC, 64 CAP_SET(block_size, 128), 65 CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1), 66 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 67 QAT_SYM_AUTH_CAP(SHA512_HMAC, 68 CAP_SET(block_size, 128), 69 CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1), 70 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 71 QAT_SYM_AUTH_CAP(MD5_HMAC, 72 CAP_SET(block_size, 64), 73 CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 16, 1), 74 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 75 QAT_SYM_AUTH_CAP(AES_XCBC_MAC, 76 CAP_SET(block_size, 16), 77 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0), 78 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 79 QAT_SYM_AUTH_CAP(SNOW3G_UIA2, 80 CAP_SET(block_size, 16), 81 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0), 82 CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)), 83 QAT_SYM_AUTH_CAP(KASUMI_F9, 84 CAP_SET(block_size, 8), 85 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0), 86 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 87 QAT_SYM_AUTH_CAP(NULL, 88 CAP_SET(block_size, 1), 89 CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size), 90 CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)), 91 QAT_SYM_CIPHER_CAP(AES_CBC, 92 CAP_SET(block_size, 16), 93 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)), 94 QAT_SYM_CIPHER_CAP(AES_CTR, 95 CAP_SET(block_size, 16), 96 CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)), 97 QAT_SYM_CIPHER_CAP(AES_XTS, 98 CAP_SET(block_size, 16), 99 CAP_RNG(key_size, 32, 64, 32), CAP_RNG(iv_size, 16, 16, 0)), 100 QAT_SYM_CIPHER_CAP(AES_DOCSISBPI, 101 CAP_SET(block_size, 16), 102 CAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)), 103 QAT_SYM_CIPHER_CAP(SNOW3G_UEA2, 104 CAP_SET(block_size, 16), 105 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), 106 QAT_SYM_CIPHER_CAP(KASUMI_F8, 107 CAP_SET(block_size, 8), 108 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 8, 8, 0)), 109 QAT_SYM_CIPHER_CAP(NULL, 110 CAP_SET(block_size, 1), 111 CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)), 112 QAT_SYM_CIPHER_CAP(3DES_CBC, 113 CAP_SET(block_size, 8), 114 CAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)), 115 QAT_SYM_CIPHER_CAP(3DES_CTR, 116 CAP_SET(block_size, 8), 117 CAP_RNG(key_size, 16, 24, 8), CAP_RNG(iv_size, 8, 8, 0)), 118 QAT_SYM_CIPHER_CAP(DES_CBC, 119 CAP_SET(block_size, 8), 120 CAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)), 121 QAT_SYM_CIPHER_CAP(DES_DOCSISBPI, 122 CAP_SET(block_size, 8), 123 CAP_RNG(key_size, 8, 8, 0), CAP_RNG(iv_size, 8, 8, 0)), 124 QAT_SYM_CIPHER_CAP(ZUC_EEA3, 125 CAP_SET(block_size, 16), 126 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), 127 QAT_SYM_AUTH_CAP(ZUC_EIA3, 128 CAP_SET(block_size, 16), 129 CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0), 130 CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)), 131 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() 132 }; 133 134 static int 135 qat_sym_crypto_qp_setup_gen2(struct rte_cryptodev *dev, uint16_t qp_id, 136 const struct rte_cryptodev_qp_conf *qp_conf, int socket_id) 137 { 138 struct qat_cryptodev_private *qat_sym_private = dev->data->dev_private; 139 struct qat_qp *qp; 140 int ret; 141 142 if (qat_cryptodev_qp_setup(dev, qp_id, qp_conf, socket_id)) { 143 QAT_LOG(DEBUG, "QAT qp setup failed"); 144 return -1; 145 } 146 147 qp = qat_sym_private->qat_dev->qps_in_use[QAT_SERVICE_SYMMETRIC][qp_id]; 148 ret = qat_cq_get_fw_version(qp); 149 if (ret < 0) { 150 qat_cryptodev_qp_release(dev, qp_id); 151 return ret; 152 } 153 154 if (ret != 0) 155 QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d", 156 (ret >> 24) & 0xff, 157 (ret >> 16) & 0xff, 158 (ret >> 8) & 0xff); 159 else 160 QAT_LOG(DEBUG, "unknown QAT firmware version"); 161 162 /* set capabilities based on the fw version */ 163 qat_sym_private->internal_capabilities = QAT_SYM_CAP_VALID | 164 ((ret >= MIXED_CRYPTO_MIN_FW_VER) ? 165 QAT_SYM_CAP_MIXED_CRYPTO : 0); 166 return 0; 167 } 168 169 struct rte_cryptodev_ops qat_sym_crypto_ops_gen2 = { 170 171 /* Device related operations */ 172 .dev_configure = qat_cryptodev_config, 173 .dev_start = qat_cryptodev_start, 174 .dev_stop = qat_cryptodev_stop, 175 .dev_close = qat_cryptodev_close, 176 .dev_infos_get = qat_cryptodev_info_get, 177 178 .stats_get = qat_cryptodev_stats_get, 179 .stats_reset = qat_cryptodev_stats_reset, 180 .queue_pair_setup = qat_sym_crypto_qp_setup_gen2, 181 .queue_pair_release = qat_cryptodev_qp_release, 182 183 /* Crypto related operations */ 184 .sym_session_get_size = qat_sym_session_get_private_size, 185 .sym_session_configure = qat_sym_session_configure, 186 .sym_session_clear = qat_sym_session_clear, 187 188 /* Raw data-path API related operations */ 189 .sym_get_raw_dp_ctx_size = qat_sym_get_dp_ctx_size, 190 .sym_configure_raw_dp_ctx = qat_sym_configure_dp_ctx, 191 }; 192 193 static struct qat_capabilities_info 194 qat_sym_crypto_cap_get_gen2(struct qat_pci_device *qat_dev __rte_unused) 195 { 196 struct qat_capabilities_info capa_info; 197 capa_info.data = qat_sym_crypto_caps_gen2; 198 capa_info.size = sizeof(qat_sym_crypto_caps_gen2); 199 return capa_info; 200 } 201 202 RTE_INIT(qat_sym_crypto_gen2_init) 203 { 204 qat_sym_gen_dev_ops[QAT_GEN2].cryptodev_ops = &qat_sym_crypto_ops_gen2; 205 qat_sym_gen_dev_ops[QAT_GEN2].get_capabilities = 206 qat_sym_crypto_cap_get_gen2; 207 qat_sym_gen_dev_ops[QAT_GEN2].get_feature_flags = 208 qat_sym_crypto_feature_flags_get_gen1; 209 210 #ifdef RTE_LIB_SECURITY 211 qat_sym_gen_dev_ops[QAT_GEN2].create_security_ctx = 212 qat_sym_create_security_gen1; 213 #endif 214 } 215 216 RTE_INIT(qat_asym_crypto_gen2_init) 217 { 218 qat_asym_gen_dev_ops[QAT_GEN2].cryptodev_ops = 219 &qat_asym_crypto_ops_gen1; 220 qat_asym_gen_dev_ops[QAT_GEN2].get_capabilities = 221 qat_asym_crypto_cap_get_gen1; 222 qat_asym_gen_dev_ops[QAT_GEN2].get_feature_flags = 223 qat_asym_crypto_feature_flags_get_gen1; 224 } 225