xref: /dpdk/drivers/crypto/mlx5/mlx5_crypto.h (revision 03ab51eafda992874a48c392ca66ffb577fe2b71)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright (c) 2021 NVIDIA Corporation & Affiliates
3  */
4 
5 #ifndef MLX5_CRYPTO_H_
6 #define MLX5_CRYPTO_H_
7 
8 #include <stdbool.h>
9 
10 #include <rte_cryptodev.h>
11 #include <cryptodev_pmd.h>
12 
13 #include <mlx5_common_utils.h>
14 #include <mlx5_common_devx.h>
15 #include <mlx5_common_mr.h>
16 
17 #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)
18 #define MLX5_CRYPTO_KEY_LENGTH 80
19 
20 struct mlx5_crypto_priv {
21 	TAILQ_ENTRY(mlx5_crypto_priv) next;
22 	struct ibv_context *ctx; /* Device context. */
23 	struct rte_cryptodev *crypto_dev;
24 	void *uar; /* User Access Region. */
25 	volatile uint64_t *uar_addr;
26 	uint32_t pdn; /* Protection Domain number. */
27 	uint32_t max_segs_num; /* Maximum supported data segs. */
28 	uint8_t qp_ts_format; /* Whether QP supports timestamp formats. */
29 	struct ibv_pd *pd;
30 	struct mlx5_hlist *dek_hlist; /* Dek hash list. */
31 	struct rte_cryptodev_config dev_config;
32 	struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
33 	struct mlx5_devx_obj *login_obj;
34 	uint64_t keytag;
35 	uint16_t wqe_set_size;
36 	uint16_t umr_wqe_size;
37 	uint16_t umr_wqe_stride;
38 	uint16_t max_rdmar_ds;
39 #ifndef RTE_ARCH_64
40 	rte_spinlock_t uar32_sl;
41 #endif /* RTE_ARCH_64 */
42 };
43 
44 struct mlx5_crypto_qp {
45 	struct mlx5_crypto_priv *priv;
46 	struct mlx5_devx_cq cq_obj;
47 	struct mlx5_devx_qp qp_obj;
48 	struct rte_cryptodev_stats stats;
49 	struct rte_crypto_op **ops;
50 	struct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */
51 	struct mlx5_mr_ctrl mr_ctrl;
52 	uint8_t *wqe;
53 	uint16_t entries_n;
54 	uint16_t pi;
55 	uint16_t ci;
56 	uint16_t db_pi;
57 };
58 
59 struct mlx5_crypto_dek {
60 	struct mlx5_list_entry entry; /* Pointer to DEK hash list entry. */
61 	struct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */
62 	uint8_t data[MLX5_CRYPTO_KEY_LENGTH]; /* DEK key data. */
63 	bool size_is_48; /* Whether the key\data size is 48 bytes or not. */
64 } __rte_cache_aligned;
65 
66 struct mlx5_crypto_devarg_params {
67 	bool login_devarg;
68 	struct mlx5_devx_crypto_login_attr login_attr;
69 	uint64_t keytag;
70 	uint32_t max_segs_num;
71 };
72 
73 int
74 mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,
75 			struct mlx5_crypto_dek *dek);
76 
77 struct mlx5_crypto_dek *
78 mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,
79 			struct rte_crypto_cipher_xform *cipher);
80 
81 int
82 mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);
83 
84 void
85 mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv);
86 
87 #endif /* MLX5_CRYPTO_H_ */
88