1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2021 NVIDIA Corporation & Affiliates 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_mempool.h> 7 #include <rte_errno.h> 8 #include <rte_log.h> 9 #include <rte_bus_pci.h> 10 #include <rte_memory.h> 11 12 #include <mlx5_glue.h> 13 #include <mlx5_common.h> 14 #include <mlx5_devx_cmds.h> 15 #include <mlx5_common_os.h> 16 17 #include "mlx5_crypto_utils.h" 18 #include "mlx5_crypto.h" 19 20 #define MLX5_CRYPTO_DRIVER_NAME crypto_mlx5 21 #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5 22 #define MLX5_CRYPTO_MAX_QPS 1024 23 #define MLX5_CRYPTO_MAX_SEGS 56 24 25 #define MLX5_CRYPTO_FEATURE_FLAGS \ 26 (RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \ 27 RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | \ 28 RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | \ 29 RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT | \ 30 RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | \ 31 RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY | \ 32 RTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS) 33 34 TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list = 35 TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list); 36 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 37 38 int mlx5_crypto_logtype; 39 40 uint8_t mlx5_crypto_driver_id; 41 42 const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = { 43 { /* AES XTS */ 44 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 45 {.sym = { 46 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, 47 {.cipher = { 48 .algo = RTE_CRYPTO_CIPHER_AES_XTS, 49 .block_size = 16, 50 .key_size = { 51 .min = 32, 52 .max = 64, 53 .increment = 32 54 }, 55 .iv_size = { 56 .min = 16, 57 .max = 16, 58 .increment = 0 59 }, 60 .dataunit_set = 61 RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES | 62 RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES, 63 }, } 64 }, } 65 }, 66 }; 67 68 static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME); 69 70 static const struct rte_driver mlx5_drv = { 71 .name = mlx5_crypto_drv_name, 72 .alias = mlx5_crypto_drv_name 73 }; 74 75 static struct cryptodev_driver mlx5_cryptodev_driver; 76 77 struct mlx5_crypto_session { 78 uint32_t bs_bpt_eo_es; 79 /**< bsf_size, bsf_p_type, encryption_order and encryption standard, 80 * saved in big endian format. 81 */ 82 uint32_t bsp_res; 83 /**< crypto_block_size_pointer and reserved 24 bits saved in big 84 * endian format. 85 */ 86 uint32_t iv_offset:16; 87 /**< Starting point for Initialisation Vector. */ 88 struct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */ 89 uint32_t dek_id; /**< DEK ID */ 90 } __rte_packed; 91 92 static void 93 mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev, 94 struct rte_cryptodev_info *dev_info) 95 { 96 RTE_SET_USED(dev); 97 if (dev_info != NULL) { 98 dev_info->driver_id = mlx5_crypto_driver_id; 99 dev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS; 100 dev_info->capabilities = mlx5_crypto_caps; 101 dev_info->max_nb_queue_pairs = MLX5_CRYPTO_MAX_QPS; 102 dev_info->min_mbuf_headroom_req = 0; 103 dev_info->min_mbuf_tailroom_req = 0; 104 dev_info->sym.max_nb_sessions = 0; 105 /* 106 * If 0, the device does not have any limitation in number of 107 * sessions that can be used. 108 */ 109 } 110 } 111 112 static int 113 mlx5_crypto_dev_configure(struct rte_cryptodev *dev, 114 struct rte_cryptodev_config *config) 115 { 116 struct mlx5_crypto_priv *priv = dev->data->dev_private; 117 118 if (config == NULL) { 119 DRV_LOG(ERR, "Invalid crypto dev configure parameters."); 120 return -EINVAL; 121 } 122 if ((config->ff_disable & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) != 0) { 123 DRV_LOG(ERR, 124 "Disabled symmetric crypto feature is not supported."); 125 return -ENOTSUP; 126 } 127 if (mlx5_crypto_dek_setup(priv) != 0) { 128 DRV_LOG(ERR, "Dek hash list creation has failed."); 129 return -ENOMEM; 130 } 131 priv->dev_config = *config; 132 DRV_LOG(DEBUG, "Device %u was configured.", dev->driver_id); 133 return 0; 134 } 135 136 static void 137 mlx5_crypto_dev_stop(struct rte_cryptodev *dev) 138 { 139 RTE_SET_USED(dev); 140 } 141 142 static int 143 mlx5_crypto_dev_start(struct rte_cryptodev *dev) 144 { 145 RTE_SET_USED(dev); 146 return 0; 147 } 148 149 static int 150 mlx5_crypto_dev_close(struct rte_cryptodev *dev) 151 { 152 struct mlx5_crypto_priv *priv = dev->data->dev_private; 153 154 mlx5_crypto_dek_unset(priv); 155 DRV_LOG(DEBUG, "Device %u was closed.", dev->driver_id); 156 return 0; 157 } 158 159 static unsigned int 160 mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) 161 { 162 return sizeof(struct mlx5_crypto_session); 163 } 164 165 static int 166 mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev, 167 struct rte_crypto_sym_xform *xform, 168 struct rte_cryptodev_sym_session *session, 169 struct rte_mempool *mp) 170 { 171 struct mlx5_crypto_priv *priv = dev->data->dev_private; 172 struct mlx5_crypto_session *sess_private_data; 173 struct rte_crypto_cipher_xform *cipher; 174 uint8_t encryption_order; 175 int ret; 176 177 if (unlikely(xform->next != NULL)) { 178 DRV_LOG(ERR, "Xform next is not supported."); 179 return -ENOTSUP; 180 } 181 if (unlikely((xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) || 182 (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_XTS))) { 183 DRV_LOG(ERR, "Only AES-XTS algorithm is supported."); 184 return -ENOTSUP; 185 } 186 ret = rte_mempool_get(mp, (void *)&sess_private_data); 187 if (ret != 0) { 188 DRV_LOG(ERR, 189 "Failed to get session %p private data from mempool.", 190 sess_private_data); 191 return -ENOMEM; 192 } 193 cipher = &xform->cipher; 194 sess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher); 195 if (sess_private_data->dek == NULL) { 196 rte_mempool_put(mp, sess_private_data); 197 DRV_LOG(ERR, "Failed to prepare dek."); 198 return -ENOMEM; 199 } 200 if (cipher->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) 201 encryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY; 202 else 203 encryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE; 204 sess_private_data->bs_bpt_eo_es = rte_cpu_to_be_32 205 (MLX5_BSF_SIZE_64B << MLX5_BSF_SIZE_OFFSET | 206 MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET | 207 encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET | 208 MLX5_ENCRYPTION_STANDARD_AES_XTS); 209 switch (xform->cipher.dataunit_len) { 210 case 0: 211 sess_private_data->bsp_res = 0; 212 break; 213 case 512: 214 sess_private_data->bsp_res = rte_cpu_to_be_32 215 ((uint32_t)MLX5_BLOCK_SIZE_512B << 216 MLX5_BLOCK_SIZE_OFFSET); 217 break; 218 case 4096: 219 sess_private_data->bsp_res = rte_cpu_to_be_32 220 ((uint32_t)MLX5_BLOCK_SIZE_4096B << 221 MLX5_BLOCK_SIZE_OFFSET); 222 break; 223 default: 224 DRV_LOG(ERR, "Cipher data unit length is not supported."); 225 return -ENOTSUP; 226 } 227 sess_private_data->iv_offset = cipher->iv.offset; 228 sess_private_data->dek_id = 229 rte_cpu_to_be_32(sess_private_data->dek->obj->id & 230 0xffffff); 231 set_sym_session_private_data(session, dev->driver_id, 232 sess_private_data); 233 DRV_LOG(DEBUG, "Session %p was configured.", sess_private_data); 234 return 0; 235 } 236 237 static void 238 mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev, 239 struct rte_cryptodev_sym_session *sess) 240 { 241 struct mlx5_crypto_priv *priv = dev->data->dev_private; 242 struct mlx5_crypto_session *spriv = get_sym_session_private_data(sess, 243 dev->driver_id); 244 245 if (unlikely(spriv == NULL)) { 246 DRV_LOG(ERR, "Failed to get session %p private data.", spriv); 247 return; 248 } 249 mlx5_crypto_dek_destroy(priv, spriv->dek); 250 set_sym_session_private_data(sess, dev->driver_id, NULL); 251 rte_mempool_put(rte_mempool_from_obj(spriv), spriv); 252 DRV_LOG(DEBUG, "Session %p was cleared.", spriv); 253 } 254 255 static void 256 mlx5_crypto_indirect_mkeys_release(struct mlx5_crypto_qp *qp, uint16_t n) 257 { 258 uint16_t i; 259 260 for (i = 0; i < n; i++) 261 if (qp->mkey[i]) 262 claim_zero(mlx5_devx_cmd_destroy(qp->mkey[i])); 263 } 264 265 static void 266 mlx5_crypto_qp_release(struct mlx5_crypto_qp *qp) 267 { 268 if (qp == NULL) 269 return; 270 mlx5_devx_qp_destroy(&qp->qp_obj); 271 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 272 mlx5_devx_cq_destroy(&qp->cq_obj); 273 rte_free(qp); 274 } 275 276 static int 277 mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) 278 { 279 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id]; 280 281 mlx5_crypto_indirect_mkeys_release(qp, qp->entries_n); 282 mlx5_crypto_qp_release(qp); 283 dev->data->queue_pairs[qp_id] = NULL; 284 return 0; 285 } 286 287 static __rte_noinline uint32_t 288 mlx5_crypto_get_block_size(struct rte_crypto_op *op) 289 { 290 uint32_t bl = op->sym->cipher.data.length; 291 292 switch (bl) { 293 case (1 << 20): 294 return RTE_BE32(MLX5_BLOCK_SIZE_1MB << MLX5_BLOCK_SIZE_OFFSET); 295 case (1 << 12): 296 return RTE_BE32(MLX5_BLOCK_SIZE_4096B << 297 MLX5_BLOCK_SIZE_OFFSET); 298 case (1 << 9): 299 return RTE_BE32(MLX5_BLOCK_SIZE_512B << MLX5_BLOCK_SIZE_OFFSET); 300 default: 301 DRV_LOG(ERR, "Unknown block size: %u.", bl); 302 return UINT32_MAX; 303 } 304 } 305 306 /** 307 * Query LKey from a packet buffer for QP. If not found, add the mempool. 308 * 309 * @param priv 310 * Pointer to the priv object. 311 * @param addr 312 * Search key. 313 * @param mr_ctrl 314 * Pointer to per-queue MR control structure. 315 * @param ol_flags 316 * Mbuf offload features. 317 * 318 * @return 319 * Searched LKey on success, UINT32_MAX on no match. 320 */ 321 static __rte_always_inline uint32_t 322 mlx5_crypto_addr2mr(struct mlx5_crypto_priv *priv, uintptr_t addr, 323 struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags) 324 { 325 uint32_t lkey; 326 327 /* Check generation bit to see if there's any change on existing MRs. */ 328 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 329 mlx5_mr_flush_local_cache(mr_ctrl); 330 /* Linear search on MR cache array. */ 331 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 332 MLX5_MR_CACHE_N, addr); 333 if (likely(lkey != UINT32_MAX)) 334 return lkey; 335 /* Take slower bottom-half on miss. */ 336 return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr, 337 !!(ol_flags & EXT_ATTACHED_MBUF)); 338 } 339 340 static __rte_always_inline uint32_t 341 mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp, 342 struct rte_mbuf *mbuf, struct mlx5_wqe_dseg *klm, 343 uint32_t offset, uint32_t *remain) 344 { 345 uint32_t data_len = (rte_pktmbuf_data_len(mbuf) - offset); 346 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 347 348 if (data_len > *remain) 349 data_len = *remain; 350 *remain -= data_len; 351 klm->bcount = rte_cpu_to_be_32(data_len); 352 klm->pbuf = rte_cpu_to_be_64(addr); 353 klm->lkey = mlx5_crypto_addr2mr(priv, addr, &qp->mr_ctrl, 354 mbuf->ol_flags); 355 return klm->lkey; 356 357 } 358 359 static __rte_always_inline uint32_t 360 mlx5_crypto_klms_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp, 361 struct rte_crypto_op *op, struct rte_mbuf *mbuf, 362 struct mlx5_wqe_dseg *klm) 363 { 364 uint32_t remain_len = op->sym->cipher.data.length; 365 uint32_t nb_segs = mbuf->nb_segs; 366 uint32_t klm_n = 1u; 367 368 /* First mbuf needs to take the cipher offset. */ 369 if (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, klm, 370 op->sym->cipher.data.offset, &remain_len) == UINT32_MAX)) { 371 op->status = RTE_CRYPTO_OP_STATUS_ERROR; 372 return 0; 373 } 374 while (remain_len) { 375 nb_segs--; 376 mbuf = mbuf->next; 377 if (unlikely(mbuf == NULL || nb_segs == 0)) { 378 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; 379 return 0; 380 } 381 if (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, ++klm, 0, 382 &remain_len) == UINT32_MAX)) { 383 op->status = RTE_CRYPTO_OP_STATUS_ERROR; 384 return 0; 385 } 386 klm_n++; 387 } 388 return klm_n; 389 } 390 391 static __rte_always_inline int 392 mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv, 393 struct mlx5_crypto_qp *qp, 394 struct rte_crypto_op *op, 395 struct mlx5_umr_wqe *umr) 396 { 397 struct mlx5_crypto_session *sess = get_sym_session_private_data 398 (op->sym->session, mlx5_crypto_driver_id); 399 struct mlx5_wqe_cseg *cseg = &umr->ctr; 400 struct mlx5_wqe_mkey_cseg *mkc = &umr->mkc; 401 struct mlx5_wqe_dseg *klms = &umr->kseg[0]; 402 struct mlx5_wqe_umr_bsf_seg *bsf = ((struct mlx5_wqe_umr_bsf_seg *) 403 RTE_PTR_ADD(umr, priv->umr_wqe_size)) - 1; 404 uint32_t ds; 405 bool ipl = op->sym->m_dst == NULL || op->sym->m_dst == op->sym->m_src; 406 /* Set UMR WQE. */ 407 uint32_t klm_n = mlx5_crypto_klms_set(priv, qp, op, 408 ipl ? op->sym->m_src : op->sym->m_dst, klms); 409 410 if (unlikely(klm_n == 0)) 411 return 0; 412 bsf->bs_bpt_eo_es = sess->bs_bpt_eo_es; 413 if (unlikely(!sess->bsp_res)) { 414 bsf->bsp_res = mlx5_crypto_get_block_size(op); 415 if (unlikely(bsf->bsp_res == UINT32_MAX)) { 416 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; 417 return 0; 418 } 419 } else { 420 bsf->bsp_res = sess->bsp_res; 421 } 422 bsf->raw_data_size = rte_cpu_to_be_32(op->sym->cipher.data.length); 423 memcpy(bsf->xts_initial_tweak, 424 rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv_offset), 16); 425 bsf->res_dp = sess->dek_id; 426 mkc->len = rte_cpu_to_be_64(op->sym->cipher.data.length); 427 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | MLX5_OPCODE_UMR); 428 qp->db_pi += priv->umr_wqe_stride; 429 /* Set RDMA_WRITE WQE. */ 430 cseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size); 431 klms = RTE_PTR_ADD(cseg, sizeof(struct mlx5_rdma_write_wqe)); 432 if (!ipl) { 433 klm_n = mlx5_crypto_klms_set(priv, qp, op, op->sym->m_src, 434 klms); 435 if (unlikely(klm_n == 0)) 436 return 0; 437 } else { 438 memcpy(klms, &umr->kseg[0], sizeof(*klms) * klm_n); 439 } 440 ds = 2 + klm_n; 441 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds); 442 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | 443 MLX5_OPCODE_RDMA_WRITE); 444 ds = RTE_ALIGN(ds, 4); 445 qp->db_pi += ds >> 2; 446 /* Set NOP WQE if needed. */ 447 if (priv->max_rdmar_ds > ds) { 448 cseg += ds; 449 ds = priv->max_rdmar_ds - ds; 450 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds); 451 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | 452 MLX5_OPCODE_NOP); 453 qp->db_pi += ds >> 2; /* Here, DS is 4 aligned for sure. */ 454 } 455 qp->wqe = (uint8_t *)cseg; 456 return 1; 457 } 458 459 static __rte_always_inline void 460 mlx5_crypto_uar_write(uint64_t val, struct mlx5_crypto_priv *priv) 461 { 462 #ifdef RTE_ARCH_64 463 *priv->uar_addr = val; 464 #else /* !RTE_ARCH_64 */ 465 rte_spinlock_lock(&priv->uar32_sl); 466 *(volatile uint32_t *)priv->uar_addr = val; 467 rte_io_wmb(); 468 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; 469 rte_spinlock_unlock(&priv->uar32_sl); 470 #endif 471 } 472 473 static uint16_t 474 mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops, 475 uint16_t nb_ops) 476 { 477 struct mlx5_crypto_qp *qp = queue_pair; 478 struct mlx5_crypto_priv *priv = qp->priv; 479 struct mlx5_umr_wqe *umr; 480 struct rte_crypto_op *op; 481 uint16_t mask = qp->entries_n - 1; 482 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 483 uint32_t idx; 484 485 if (remain < nb_ops) 486 nb_ops = remain; 487 else 488 remain = nb_ops; 489 if (unlikely(remain == 0)) 490 return 0; 491 do { 492 idx = qp->pi & mask; 493 op = *ops++; 494 umr = RTE_PTR_ADD(qp->qp_obj.umem_buf, 495 priv->wqe_set_size * idx); 496 if (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) { 497 qp->stats.enqueue_err_count++; 498 if (remain != nb_ops) { 499 qp->stats.enqueued_count -= remain; 500 break; 501 } 502 return 0; 503 } 504 qp->ops[idx] = op; 505 qp->pi++; 506 } while (--remain); 507 qp->stats.enqueued_count += nb_ops; 508 rte_io_wmb(); 509 qp->qp_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi); 510 rte_wmb(); 511 mlx5_crypto_uar_write(*(volatile uint64_t *)qp->wqe, qp->priv); 512 rte_wmb(); 513 return nb_ops; 514 } 515 516 static __rte_noinline void 517 mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op) 518 { 519 const uint32_t idx = qp->ci & (qp->entries_n - 1); 520 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 521 &qp->cq_obj.cqes[idx]; 522 523 op->status = RTE_CRYPTO_OP_STATUS_ERROR; 524 qp->stats.dequeue_err_count++; 525 DRV_LOG(ERR, "CQE ERR:%x.\n", rte_be_to_cpu_32(cqe->syndrome)); 526 } 527 528 static uint16_t 529 mlx5_crypto_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops, 530 uint16_t nb_ops) 531 { 532 struct mlx5_crypto_qp *qp = queue_pair; 533 volatile struct mlx5_cqe *restrict cqe; 534 struct rte_crypto_op *restrict op; 535 const unsigned int cq_size = qp->entries_n; 536 const unsigned int mask = cq_size - 1; 537 uint32_t idx; 538 uint32_t next_idx = qp->ci & mask; 539 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 540 uint16_t i = 0; 541 int ret; 542 543 if (unlikely(max == 0)) 544 return 0; 545 do { 546 idx = next_idx; 547 next_idx = (qp->ci + 1) & mask; 548 op = qp->ops[idx]; 549 cqe = &qp->cq_obj.cqes[idx]; 550 ret = check_cqe(cqe, cq_size, qp->ci); 551 rte_io_rmb(); 552 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 553 if (unlikely(ret != MLX5_CQE_STATUS_HW_OWN)) 554 mlx5_crypto_cqe_err_handle(qp, op); 555 break; 556 } 557 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; 558 ops[i++] = op; 559 qp->ci++; 560 } while (i < max); 561 if (likely(i != 0)) { 562 rte_io_wmb(); 563 qp->cq_obj.db_rec[0] = rte_cpu_to_be_32(qp->ci); 564 qp->stats.dequeued_count += i; 565 } 566 return i; 567 } 568 569 static void 570 mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp) 571 { 572 uint32_t i; 573 574 for (i = 0 ; i < qp->entries_n; i++) { 575 struct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->qp_obj.umem_buf, 576 i * priv->wqe_set_size); 577 struct mlx5_wqe_umr_cseg *ucseg = (struct mlx5_wqe_umr_cseg *) 578 (cseg + 1); 579 struct mlx5_wqe_umr_bsf_seg *bsf = 580 (struct mlx5_wqe_umr_bsf_seg *)(RTE_PTR_ADD(cseg, 581 priv->umr_wqe_size)) - 1; 582 struct mlx5_wqe_rseg *rseg; 583 584 /* Init UMR WQE. */ 585 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | 586 (priv->umr_wqe_size / MLX5_WSEG_SIZE)); 587 cseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR << 588 MLX5_COMP_MODE_OFFSET); 589 cseg->misc = rte_cpu_to_be_32(qp->mkey[i]->id); 590 ucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET); 591 ucseg->mkey_mask = RTE_BE64(1u << 0); /* Mkey length bit. */ 592 ucseg->ko_to_bs = rte_cpu_to_be_32 593 ((RTE_ALIGN(priv->max_segs_num, 4u) << 594 MLX5_UMRC_KO_OFFSET) | (4 << MLX5_UMRC_TO_BS_OFFSET)); 595 bsf->keytag = priv->keytag; 596 /* Init RDMA WRITE WQE. */ 597 cseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size); 598 cseg->flags = RTE_BE32((MLX5_COMP_ALWAYS << 599 MLX5_COMP_MODE_OFFSET) | 600 MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE); 601 rseg = (struct mlx5_wqe_rseg *)(cseg + 1); 602 rseg->rkey = rte_cpu_to_be_32(qp->mkey[i]->id); 603 } 604 } 605 606 static int 607 mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv, 608 struct mlx5_crypto_qp *qp) 609 { 610 struct mlx5_umr_wqe *umr; 611 uint32_t i; 612 struct mlx5_devx_mkey_attr attr = { 613 .pd = priv->pdn, 614 .umr_en = 1, 615 .crypto_en = 1, 616 .set_remote_rw = 1, 617 .klm_num = RTE_ALIGN(priv->max_segs_num, 4), 618 }; 619 620 for (umr = (struct mlx5_umr_wqe *)qp->qp_obj.umem_buf, i = 0; 621 i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) { 622 attr.klm_array = (struct mlx5_klm *)&umr->kseg[0]; 623 qp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr); 624 if (!qp->mkey[i]) 625 goto error; 626 } 627 return 0; 628 error: 629 DRV_LOG(ERR, "Failed to allocate indirect mkey."); 630 mlx5_crypto_indirect_mkeys_release(qp, i); 631 return -1; 632 } 633 634 static int 635 mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, 636 const struct rte_cryptodev_qp_conf *qp_conf, 637 int socket_id) 638 { 639 struct mlx5_crypto_priv *priv = dev->data->dev_private; 640 struct mlx5_devx_qp_attr attr = {0}; 641 struct mlx5_crypto_qp *qp; 642 uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors); 643 uint32_t ret; 644 uint32_t alloc_size = sizeof(*qp); 645 struct mlx5_devx_cq_attr cq_attr = { 646 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), 647 }; 648 649 if (dev->data->queue_pairs[qp_id] != NULL) 650 mlx5_crypto_queue_pair_release(dev, qp_id); 651 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 652 alloc_size += (sizeof(struct rte_crypto_op *) + 653 sizeof(struct mlx5_devx_obj *)) * 654 RTE_BIT32(log_nb_desc); 655 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 656 socket_id); 657 if (qp == NULL) { 658 DRV_LOG(ERR, "Failed to allocate QP memory."); 659 rte_errno = ENOMEM; 660 return -rte_errno; 661 } 662 if (mlx5_devx_cq_create(priv->ctx, &qp->cq_obj, log_nb_desc, 663 &cq_attr, socket_id) != 0) { 664 DRV_LOG(ERR, "Failed to create CQ."); 665 goto error; 666 } 667 attr.pd = priv->pdn; 668 attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar); 669 attr.cqn = qp->cq_obj.cq->id; 670 attr.rq_size = 0; 671 attr.sq_size = RTE_BIT32(log_nb_desc); 672 attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); 673 ret = mlx5_devx_qp_create(priv->ctx, &qp->qp_obj, log_nb_desc, &attr, 674 socket_id); 675 if (ret) { 676 DRV_LOG(ERR, "Failed to create QP."); 677 goto error; 678 } 679 if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N, 680 priv->dev_config.socket_id) != 0) { 681 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 682 (uint32_t)qp_id); 683 rte_errno = ENOMEM; 684 goto error; 685 } 686 qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen; 687 /* 688 * In Order to configure self loopback, when calling devx qp2rts the 689 * remote QP id that is used is the id of the same QP. 690 */ 691 if (mlx5_devx_qp2rts(&qp->qp_obj, qp->qp_obj.qp->id)) 692 goto error; 693 qp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1), 694 RTE_CACHE_LINE_SIZE); 695 qp->ops = (struct rte_crypto_op **)(qp->mkey + RTE_BIT32(log_nb_desc)); 696 qp->entries_n = 1 << log_nb_desc; 697 if (mlx5_crypto_indirect_mkeys_prepare(priv, qp)) { 698 DRV_LOG(ERR, "Cannot allocate indirect memory regions."); 699 rte_errno = ENOMEM; 700 goto error; 701 } 702 mlx5_crypto_qp_init(priv, qp); 703 qp->priv = priv; 704 dev->data->queue_pairs[qp_id] = qp; 705 return 0; 706 error: 707 mlx5_crypto_qp_release(qp); 708 return -1; 709 } 710 711 static void 712 mlx5_crypto_stats_get(struct rte_cryptodev *dev, 713 struct rte_cryptodev_stats *stats) 714 { 715 int qp_id; 716 717 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 718 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id]; 719 720 stats->enqueued_count += qp->stats.enqueued_count; 721 stats->dequeued_count += qp->stats.dequeued_count; 722 stats->enqueue_err_count += qp->stats.enqueue_err_count; 723 stats->dequeue_err_count += qp->stats.dequeue_err_count; 724 } 725 } 726 727 static void 728 mlx5_crypto_stats_reset(struct rte_cryptodev *dev) 729 { 730 int qp_id; 731 732 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 733 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id]; 734 735 memset(&qp->stats, 0, sizeof(qp->stats)); 736 } 737 } 738 739 static struct rte_cryptodev_ops mlx5_crypto_ops = { 740 .dev_configure = mlx5_crypto_dev_configure, 741 .dev_start = mlx5_crypto_dev_start, 742 .dev_stop = mlx5_crypto_dev_stop, 743 .dev_close = mlx5_crypto_dev_close, 744 .dev_infos_get = mlx5_crypto_dev_infos_get, 745 .stats_get = mlx5_crypto_stats_get, 746 .stats_reset = mlx5_crypto_stats_reset, 747 .queue_pair_setup = mlx5_crypto_queue_pair_setup, 748 .queue_pair_release = mlx5_crypto_queue_pair_release, 749 .sym_session_get_size = mlx5_crypto_sym_session_get_size, 750 .sym_session_configure = mlx5_crypto_sym_session_configure, 751 .sym_session_clear = mlx5_crypto_sym_session_clear, 752 .sym_get_raw_dp_ctx_size = NULL, 753 .sym_configure_raw_dp_ctx = NULL, 754 }; 755 756 static void 757 mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv) 758 { 759 if (priv->pd != NULL) { 760 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 761 priv->pd = NULL; 762 } 763 if (priv->uar != NULL) { 764 mlx5_glue->devx_free_uar(priv->uar); 765 priv->uar = NULL; 766 } 767 } 768 769 static int 770 mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) 771 { 772 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 773 struct mlx5dv_obj obj; 774 struct mlx5dv_pd pd_info; 775 int ret; 776 777 priv->pd = mlx5_glue->alloc_pd(priv->ctx); 778 if (priv->pd == NULL) { 779 DRV_LOG(ERR, "Failed to allocate PD."); 780 return errno ? -errno : -ENOMEM; 781 } 782 obj.pd.in = priv->pd; 783 obj.pd.out = &pd_info; 784 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 785 if (ret != 0) { 786 DRV_LOG(ERR, "Fail to get PD object info."); 787 mlx5_glue->dealloc_pd(priv->pd); 788 priv->pd = NULL; 789 return -errno; 790 } 791 priv->pdn = pd_info.pdn; 792 return 0; 793 #else 794 (void)priv; 795 DRV_LOG(ERR, "Cannot get pdn - no DV support."); 796 return -ENOTSUP; 797 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 798 } 799 800 static int 801 mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv) 802 { 803 if (mlx5_crypto_pd_create(priv) != 0) 804 return -1; 805 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1); 806 if (priv->uar) 807 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); 808 if (priv->uar == NULL || priv->uar_addr == NULL) { 809 rte_errno = errno; 810 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 811 DRV_LOG(ERR, "Failed to allocate UAR."); 812 return -1; 813 } 814 return 0; 815 } 816 817 818 static int 819 mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque) 820 { 821 struct mlx5_crypto_devarg_params *devarg_prms = opaque; 822 struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr; 823 unsigned long tmp; 824 FILE *file; 825 int ret; 826 int i; 827 828 if (strcmp(key, "class") == 0) 829 return 0; 830 if (strcmp(key, "wcs_file") == 0) { 831 file = fopen(val, "rb"); 832 if (file == NULL) { 833 rte_errno = ENOTSUP; 834 return -rte_errno; 835 } 836 for (i = 0 ; i < MLX5_CRYPTO_CREDENTIAL_SIZE ; i++) { 837 ret = fscanf(file, "%02hhX", &attr->credential[i]); 838 if (ret <= 0) { 839 fclose(file); 840 DRV_LOG(ERR, 841 "Failed to read credential from file."); 842 rte_errno = EINVAL; 843 return -rte_errno; 844 } 845 } 846 fclose(file); 847 devarg_prms->login_devarg = true; 848 return 0; 849 } 850 errno = 0; 851 tmp = strtoul(val, NULL, 0); 852 if (errno) { 853 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", key, val); 854 return -errno; 855 } 856 if (strcmp(key, "max_segs_num") == 0) { 857 if (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) { 858 DRV_LOG(WARNING, "Invalid max_segs_num: %d, should" 859 " be less than %d.", 860 (uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS); 861 rte_errno = EINVAL; 862 return -rte_errno; 863 } 864 devarg_prms->max_segs_num = (uint32_t)tmp; 865 } else if (strcmp(key, "import_kek_id") == 0) { 866 attr->session_import_kek_ptr = (uint32_t)tmp; 867 } else if (strcmp(key, "credential_id") == 0) { 868 attr->credential_pointer = (uint32_t)tmp; 869 } else if (strcmp(key, "keytag") == 0) { 870 devarg_prms->keytag = tmp; 871 } else { 872 DRV_LOG(WARNING, "Invalid key %s.", key); 873 } 874 return 0; 875 } 876 877 static int 878 mlx5_crypto_parse_devargs(struct rte_devargs *devargs, 879 struct mlx5_crypto_devarg_params *devarg_prms) 880 { 881 struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr; 882 struct rte_kvargs *kvlist; 883 884 /* Default values. */ 885 attr->credential_pointer = 0; 886 attr->session_import_kek_ptr = 0; 887 devarg_prms->keytag = 0; 888 devarg_prms->max_segs_num = 8; 889 if (devargs == NULL) { 890 DRV_LOG(ERR, 891 "No login devargs in order to enable crypto operations in the device."); 892 rte_errno = EINVAL; 893 return -1; 894 } 895 kvlist = rte_kvargs_parse(devargs->args, NULL); 896 if (kvlist == NULL) { 897 DRV_LOG(ERR, "Failed to parse devargs."); 898 rte_errno = EINVAL; 899 return -1; 900 } 901 if (rte_kvargs_process(kvlist, NULL, mlx5_crypto_args_check_handler, 902 devarg_prms) != 0) { 903 DRV_LOG(ERR, "Devargs handler function Failed."); 904 rte_kvargs_free(kvlist); 905 rte_errno = EINVAL; 906 return -1; 907 } 908 rte_kvargs_free(kvlist); 909 if (devarg_prms->login_devarg == false) { 910 DRV_LOG(ERR, 911 "No login credential devarg in order to enable crypto operations " 912 "in the device."); 913 rte_errno = EINVAL; 914 return -1; 915 } 916 return 0; 917 } 918 919 /** 920 * Callback for memory event. 921 * 922 * @param event_type 923 * Memory event type. 924 * @param addr 925 * Address of memory. 926 * @param len 927 * Size of memory. 928 */ 929 static void 930 mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, 931 size_t len, void *arg __rte_unused) 932 { 933 struct mlx5_crypto_priv *priv; 934 935 /* Must be called from the primary process. */ 936 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 937 switch (event_type) { 938 case RTE_MEM_EVENT_FREE: 939 pthread_mutex_lock(&priv_list_lock); 940 /* Iterate all the existing mlx5 devices. */ 941 TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next) 942 mlx5_free_mr_by_addr(&priv->mr_scache, 943 priv->ctx->device->name, 944 addr, len); 945 pthread_mutex_unlock(&priv_list_lock); 946 break; 947 case RTE_MEM_EVENT_ALLOC: 948 default: 949 break; 950 } 951 } 952 953 static int 954 mlx5_crypto_dev_probe(struct rte_device *dev) 955 { 956 struct ibv_device *ibv; 957 struct rte_cryptodev *crypto_dev; 958 struct ibv_context *ctx; 959 struct mlx5_devx_obj *login; 960 struct mlx5_crypto_priv *priv; 961 struct mlx5_crypto_devarg_params devarg_prms = { 0 }; 962 struct mlx5_hca_attr attr = { 0 }; 963 struct rte_cryptodev_pmd_init_params init_params = { 964 .name = "", 965 .private_data_size = sizeof(struct mlx5_crypto_priv), 966 .socket_id = dev->numa_node, 967 .max_nb_queue_pairs = 968 RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS, 969 }; 970 uint16_t rdmw_wqe_size; 971 int ret; 972 973 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 974 DRV_LOG(ERR, "Non-primary process type is not supported."); 975 rte_errno = ENOTSUP; 976 return -rte_errno; 977 } 978 ibv = mlx5_os_get_ibv_dev(dev); 979 if (ibv == NULL) 980 return -rte_errno; 981 ctx = mlx5_glue->dv_open_device(ibv); 982 if (ctx == NULL) { 983 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); 984 rte_errno = ENODEV; 985 return -rte_errno; 986 } 987 if (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 || 988 attr.crypto == 0 || attr.aes_xts == 0) { 989 DRV_LOG(ERR, "Not enough capabilities to support crypto " 990 "operations, maybe old FW/OFED version?"); 991 claim_zero(mlx5_glue->close_device(ctx)); 992 rte_errno = ENOTSUP; 993 return -ENOTSUP; 994 } 995 ret = mlx5_crypto_parse_devargs(dev->devargs, &devarg_prms); 996 if (ret) { 997 DRV_LOG(ERR, "Failed to parse devargs."); 998 claim_zero(mlx5_glue->close_device(ctx)); 999 return -rte_errno; 1000 } 1001 login = mlx5_devx_cmd_create_crypto_login_obj(ctx, 1002 &devarg_prms.login_attr); 1003 if (login == NULL) { 1004 DRV_LOG(ERR, "Failed to configure login."); 1005 claim_zero(mlx5_glue->close_device(ctx)); 1006 return -rte_errno; 1007 } 1008 crypto_dev = rte_cryptodev_pmd_create(ibv->name, dev, 1009 &init_params); 1010 if (crypto_dev == NULL) { 1011 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); 1012 claim_zero(mlx5_glue->close_device(ctx)); 1013 return -ENODEV; 1014 } 1015 DRV_LOG(INFO, 1016 "Crypto device %s was created successfully.", ibv->name); 1017 crypto_dev->dev_ops = &mlx5_crypto_ops; 1018 crypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst; 1019 crypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst; 1020 crypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS; 1021 crypto_dev->driver_id = mlx5_crypto_driver_id; 1022 priv = crypto_dev->data->dev_private; 1023 priv->ctx = ctx; 1024 priv->login_obj = login; 1025 priv->crypto_dev = crypto_dev; 1026 priv->qp_ts_format = attr.qp_ts_format; 1027 if (mlx5_crypto_hw_global_prepare(priv) != 0) { 1028 rte_cryptodev_pmd_destroy(priv->crypto_dev); 1029 claim_zero(mlx5_glue->close_device(priv->ctx)); 1030 return -1; 1031 } 1032 if (mlx5_mr_btree_init(&priv->mr_scache.cache, 1033 MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) { 1034 DRV_LOG(ERR, "Failed to allocate shared cache MR memory."); 1035 mlx5_crypto_hw_global_release(priv); 1036 rte_cryptodev_pmd_destroy(priv->crypto_dev); 1037 claim_zero(mlx5_glue->close_device(priv->ctx)); 1038 rte_errno = ENOMEM; 1039 return -rte_errno; 1040 } 1041 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; 1042 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; 1043 priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); 1044 priv->max_segs_num = devarg_prms.max_segs_num; 1045 priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + 1046 sizeof(struct mlx5_umr_wqe) + 1047 RTE_ALIGN(priv->max_segs_num, 4) * 1048 sizeof(struct mlx5_wqe_dseg); 1049 rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) + 1050 sizeof(struct mlx5_wqe_dseg) * 1051 (priv->max_segs_num <= 2 ? 2 : 2 + 1052 RTE_ALIGN(priv->max_segs_num - 2, 4)); 1053 priv->wqe_set_size = priv->umr_wqe_size + rdmw_wqe_size; 1054 priv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB; 1055 priv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg); 1056 /* Register callback function for global shared MR cache management. */ 1057 if (TAILQ_EMPTY(&mlx5_crypto_priv_list)) 1058 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1059 mlx5_crypto_mr_mem_event_cb, 1060 NULL); 1061 pthread_mutex_lock(&priv_list_lock); 1062 TAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next); 1063 pthread_mutex_unlock(&priv_list_lock); 1064 return 0; 1065 } 1066 1067 static int 1068 mlx5_crypto_dev_remove(struct rte_device *dev) 1069 { 1070 struct mlx5_crypto_priv *priv = NULL; 1071 1072 pthread_mutex_lock(&priv_list_lock); 1073 TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next) 1074 if (priv->crypto_dev->device == dev) 1075 break; 1076 if (priv) 1077 TAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next); 1078 pthread_mutex_unlock(&priv_list_lock); 1079 if (priv) { 1080 if (TAILQ_EMPTY(&mlx5_crypto_priv_list)) 1081 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", 1082 NULL); 1083 mlx5_mr_release_cache(&priv->mr_scache); 1084 mlx5_crypto_hw_global_release(priv); 1085 rte_cryptodev_pmd_destroy(priv->crypto_dev); 1086 claim_zero(mlx5_devx_cmd_destroy(priv->login_obj)); 1087 claim_zero(mlx5_glue->close_device(priv->ctx)); 1088 } 1089 return 0; 1090 } 1091 1092 static const struct rte_pci_id mlx5_crypto_pci_id_map[] = { 1093 { 1094 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1095 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 1096 }, 1097 { 1098 .vendor_id = 0 1099 } 1100 }; 1101 1102 static struct mlx5_class_driver mlx5_crypto_driver = { 1103 .drv_class = MLX5_CLASS_CRYPTO, 1104 .name = RTE_STR(MLX5_CRYPTO_DRIVER_NAME), 1105 .id_table = mlx5_crypto_pci_id_map, 1106 .probe = mlx5_crypto_dev_probe, 1107 .remove = mlx5_crypto_dev_remove, 1108 }; 1109 1110 RTE_INIT(rte_mlx5_crypto_init) 1111 { 1112 mlx5_common_init(); 1113 if (mlx5_glue != NULL) 1114 mlx5_class_driver_register(&mlx5_crypto_driver); 1115 } 1116 1117 RTE_PMD_REGISTER_CRYPTO_DRIVER(mlx5_cryptodev_driver, mlx5_drv, 1118 mlx5_crypto_driver_id); 1119 1120 RTE_LOG_REGISTER_DEFAULT(mlx5_crypto_logtype, NOTICE) 1121 RTE_PMD_EXPORT_NAME(MLX5_CRYPTO_DRIVER_NAME, __COUNTER__); 1122 RTE_PMD_REGISTER_PCI_TABLE(MLX5_CRYPTO_DRIVER_NAME, mlx5_crypto_pci_id_map); 1123 RTE_PMD_REGISTER_KMOD_DEP(MLX5_CRYPTO_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 1124