17a34c215SFiona Trahe /* SPDX-License-Identifier: BSD-3-Clause 235233274STomasz Jozwiak * Copyright(c) 2015-2019 Intel Corporation 37a34c215SFiona Trahe */ 47a34c215SFiona Trahe 535233274STomasz Jozwiak #include <rte_malloc.h> 635233274STomasz Jozwiak 7be8343b0SFiona Trahe #include "qat_comp.h" 87a34c215SFiona Trahe #include "qat_comp_pmd.h" 972385564SFiona Trahe 1035233274STomasz Jozwiak #define QAT_PMD_COMP_SGL_DEF_SEGMENTS 16 1135233274STomasz Jozwiak 1282822753SAdam Dybkowski struct stream_create_info { 1382822753SAdam Dybkowski struct qat_comp_dev_private *comp_dev; 1482822753SAdam Dybkowski int socket_id; 1582822753SAdam Dybkowski int error; 1682822753SAdam Dybkowski }; 1782822753SAdam Dybkowski 18c0c90bc4SFiona Trahe static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = { 19c0c90bc4SFiona Trahe {/* COMPRESSION - deflate */ 20c0c90bc4SFiona Trahe .algo = RTE_COMP_ALGO_DEFLATE, 21c0c90bc4SFiona Trahe .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM | 22c0c90bc4SFiona Trahe RTE_COMP_FF_CRC32_CHECKSUM | 23c0c90bc4SFiona Trahe RTE_COMP_FF_ADLER32_CHECKSUM | 24c0c90bc4SFiona Trahe RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 25c0c90bc4SFiona Trahe RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 261947bd18SFiona Trahe RTE_COMP_FF_HUFFMAN_FIXED | 27a124830aSFiona Trahe RTE_COMP_FF_HUFFMAN_DYNAMIC | 281947bd18SFiona Trahe RTE_COMP_FF_OOP_SGL_IN_SGL_OUT | 291947bd18SFiona Trahe RTE_COMP_FF_OOP_SGL_IN_LB_OUT | 3082822753SAdam Dybkowski RTE_COMP_FF_OOP_LB_IN_SGL_OUT | 3182822753SAdam Dybkowski RTE_COMP_FF_STATEFUL_DECOMPRESSION, 32c0c90bc4SFiona Trahe .window_size = {.min = 15, .max = 15, .increment = 0} }, 33c0c90bc4SFiona Trahe {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } }; 34c0c90bc4SFiona Trahe 35edd37ac1SFiona Trahe static void 3672385564SFiona Trahe qat_comp_stats_get(struct rte_compressdev *dev, 3772385564SFiona Trahe struct rte_compressdev_stats *stats) 3872385564SFiona Trahe { 3972385564SFiona Trahe struct qat_common_stats qat_stats = {0}; 4072385564SFiona Trahe struct qat_comp_dev_private *qat_priv; 4172385564SFiona Trahe 4272385564SFiona Trahe if (stats == NULL || dev == NULL) { 4372385564SFiona Trahe QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev); 4472385564SFiona Trahe return; 4572385564SFiona Trahe } 4672385564SFiona Trahe qat_priv = dev->data->dev_private; 4772385564SFiona Trahe 4872385564SFiona Trahe qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION); 4972385564SFiona Trahe stats->enqueued_count = qat_stats.enqueued_count; 5072385564SFiona Trahe stats->dequeued_count = qat_stats.dequeued_count; 5172385564SFiona Trahe stats->enqueue_err_count = qat_stats.enqueue_err_count; 5272385564SFiona Trahe stats->dequeue_err_count = qat_stats.dequeue_err_count; 5372385564SFiona Trahe } 5472385564SFiona Trahe 55edd37ac1SFiona Trahe static void 5672385564SFiona Trahe qat_comp_stats_reset(struct rte_compressdev *dev) 5772385564SFiona Trahe { 5872385564SFiona Trahe struct qat_comp_dev_private *qat_priv; 5972385564SFiona Trahe 6072385564SFiona Trahe if (dev == NULL) { 6172385564SFiona Trahe QAT_LOG(ERR, "invalid compressdev ptr %p", dev); 6272385564SFiona Trahe return; 6372385564SFiona Trahe } 6472385564SFiona Trahe qat_priv = dev->data->dev_private; 6572385564SFiona Trahe 6672385564SFiona Trahe qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION); 6772385564SFiona Trahe 6872385564SFiona Trahe } 69be8343b0SFiona Trahe 70edd37ac1SFiona Trahe static int 71be8343b0SFiona Trahe qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id) 72be8343b0SFiona Trahe { 73be8343b0SFiona Trahe struct qat_comp_dev_private *qat_private = dev->data->dev_private; 7435233274STomasz Jozwiak struct qat_qp **qp_addr = 7535233274STomasz Jozwiak (struct qat_qp **)&(dev->data->queue_pairs[queue_pair_id]); 7635233274STomasz Jozwiak struct qat_qp *qp = (struct qat_qp *)*qp_addr; 7735233274STomasz Jozwiak uint32_t i; 78be8343b0SFiona Trahe 79be8343b0SFiona Trahe QAT_LOG(DEBUG, "Release comp qp %u on device %d", 80be8343b0SFiona Trahe queue_pair_id, dev->data->dev_id); 81be8343b0SFiona Trahe 82be8343b0SFiona Trahe qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id] 83be8343b0SFiona Trahe = NULL; 84be8343b0SFiona Trahe 8535233274STomasz Jozwiak for (i = 0; i < qp->nb_descriptors; i++) { 8635233274STomasz Jozwiak 8735233274STomasz Jozwiak struct qat_comp_op_cookie *cookie = qp->op_cookies[i]; 8835233274STomasz Jozwiak 8935233274STomasz Jozwiak rte_free(cookie->qat_sgl_src_d); 9035233274STomasz Jozwiak rte_free(cookie->qat_sgl_dst_d); 9135233274STomasz Jozwiak } 9235233274STomasz Jozwiak 93be8343b0SFiona Trahe return qat_qp_release((struct qat_qp **) 94be8343b0SFiona Trahe &(dev->data->queue_pairs[queue_pair_id])); 95be8343b0SFiona Trahe } 96be8343b0SFiona Trahe 97edd37ac1SFiona Trahe static int 98be8343b0SFiona Trahe qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, 99be8343b0SFiona Trahe uint32_t max_inflight_ops, int socket_id) 100be8343b0SFiona Trahe { 1011947bd18SFiona Trahe struct qat_qp *qp; 102be8343b0SFiona Trahe int ret = 0; 1031947bd18SFiona Trahe uint32_t i; 104be8343b0SFiona Trahe struct qat_qp_config qat_qp_conf; 105be8343b0SFiona Trahe 106be8343b0SFiona Trahe struct qat_qp **qp_addr = 107be8343b0SFiona Trahe (struct qat_qp **)&(dev->data->queue_pairs[qp_id]); 108be8343b0SFiona Trahe struct qat_comp_dev_private *qat_private = dev->data->dev_private; 109be8343b0SFiona Trahe const struct qat_qp_hw_data *comp_hw_qps = 110be8343b0SFiona Trahe qat_gen_config[qat_private->qat_dev->qat_dev_gen] 111be8343b0SFiona Trahe .qp_hw_data[QAT_SERVICE_COMPRESSION]; 112be8343b0SFiona Trahe const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id; 113be8343b0SFiona Trahe 114be8343b0SFiona Trahe /* If qp is already in use free ring memory and qp metadata. */ 115be8343b0SFiona Trahe if (*qp_addr != NULL) { 116be8343b0SFiona Trahe ret = qat_comp_qp_release(dev, qp_id); 117be8343b0SFiona Trahe if (ret < 0) 118be8343b0SFiona Trahe return ret; 119be8343b0SFiona Trahe } 120be8343b0SFiona Trahe if (qp_id >= qat_qps_per_service(comp_hw_qps, 121be8343b0SFiona Trahe QAT_SERVICE_COMPRESSION)) { 122be8343b0SFiona Trahe QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id); 123be8343b0SFiona Trahe return -EINVAL; 124be8343b0SFiona Trahe } 125be8343b0SFiona Trahe 126be8343b0SFiona Trahe qat_qp_conf.hw = qp_hw_data; 127be8343b0SFiona Trahe qat_qp_conf.build_request = qat_comp_build_request; 128be8343b0SFiona Trahe qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie); 129be8343b0SFiona Trahe qat_qp_conf.nb_descriptors = max_inflight_ops; 130be8343b0SFiona Trahe qat_qp_conf.socket_id = socket_id; 131be8343b0SFiona Trahe qat_qp_conf.service_str = "comp"; 132be8343b0SFiona Trahe 133be8343b0SFiona Trahe ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf); 134be8343b0SFiona Trahe if (ret != 0) 135be8343b0SFiona Trahe return ret; 136be8343b0SFiona Trahe 137be8343b0SFiona Trahe /* store a link to the qp in the qat_pci_device */ 138be8343b0SFiona Trahe qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id] 139be8343b0SFiona Trahe = *qp_addr; 140be8343b0SFiona Trahe 1411947bd18SFiona Trahe qp = (struct qat_qp *)*qp_addr; 14247c3f7a4SArek Kusztal qp->min_enq_burst_threshold = qat_private->min_enq_burst_threshold; 1431947bd18SFiona Trahe 1441947bd18SFiona Trahe for (i = 0; i < qp->nb_descriptors; i++) { 1451947bd18SFiona Trahe 1461947bd18SFiona Trahe struct qat_comp_op_cookie *cookie = 1471947bd18SFiona Trahe qp->op_cookies[i]; 1481947bd18SFiona Trahe 149*c13cecf6SAdam Dybkowski cookie->qp = qp; 150*c13cecf6SAdam Dybkowski cookie->cookie_index = i; 151*c13cecf6SAdam Dybkowski 15235233274STomasz Jozwiak cookie->qat_sgl_src_d = rte_zmalloc_socket(NULL, 15335233274STomasz Jozwiak sizeof(struct qat_sgl) + 15435233274STomasz Jozwiak sizeof(struct qat_flat_buf) * 15535233274STomasz Jozwiak QAT_PMD_COMP_SGL_DEF_SEGMENTS, 15635233274STomasz Jozwiak 64, dev->data->socket_id); 15735233274STomasz Jozwiak 15835233274STomasz Jozwiak cookie->qat_sgl_dst_d = rte_zmalloc_socket(NULL, 15935233274STomasz Jozwiak sizeof(struct qat_sgl) + 16035233274STomasz Jozwiak sizeof(struct qat_flat_buf) * 16135233274STomasz Jozwiak QAT_PMD_COMP_SGL_DEF_SEGMENTS, 16235233274STomasz Jozwiak 64, dev->data->socket_id); 16335233274STomasz Jozwiak 16435233274STomasz Jozwiak if (cookie->qat_sgl_src_d == NULL || 16535233274STomasz Jozwiak cookie->qat_sgl_dst_d == NULL) { 16635233274STomasz Jozwiak QAT_LOG(ERR, "Can't allocate SGL" 16735233274STomasz Jozwiak " for device %s", 16835233274STomasz Jozwiak qat_private->qat_dev->name); 16935233274STomasz Jozwiak return -ENOMEM; 17035233274STomasz Jozwiak } 17135233274STomasz Jozwiak 1721947bd18SFiona Trahe cookie->qat_sgl_src_phys_addr = 17335233274STomasz Jozwiak rte_malloc_virt2iova(cookie->qat_sgl_src_d); 1741947bd18SFiona Trahe 1751947bd18SFiona Trahe cookie->qat_sgl_dst_phys_addr = 17635233274STomasz Jozwiak rte_malloc_virt2iova(cookie->qat_sgl_dst_d); 17735233274STomasz Jozwiak 17835233274STomasz Jozwiak cookie->dst_nb_elems = cookie->src_nb_elems = 17935233274STomasz Jozwiak QAT_PMD_COMP_SGL_DEF_SEGMENTS; 18035233274STomasz Jozwiak 18135233274STomasz Jozwiak cookie->socket_id = dev->data->socket_id; 182b643808fSTomasz Jozwiak 183b643808fSTomasz Jozwiak cookie->error = 0; 1841947bd18SFiona Trahe } 1851947bd18SFiona Trahe 186be8343b0SFiona Trahe return ret; 187be8343b0SFiona Trahe } 188a795248dSFiona Trahe 189a124830aSFiona Trahe 190a124830aSFiona Trahe #define QAT_IM_BUFFER_DEBUG 0 191a124830aSFiona Trahe static const struct rte_memzone * 192a124830aSFiona Trahe qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev, 193a124830aSFiona Trahe uint32_t buff_size) 194a124830aSFiona Trahe { 195a124830aSFiona Trahe char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE]; 196a124830aSFiona Trahe const struct rte_memzone *memzone; 197a124830aSFiona Trahe uint8_t *mz_start = NULL; 198a124830aSFiona Trahe rte_iova_t mz_start_phys = 0; 199a124830aSFiona Trahe struct array_of_ptrs *array_of_pointers; 200a124830aSFiona Trahe int size_of_ptr_array; 201a124830aSFiona Trahe uint32_t full_size; 202a124830aSFiona Trahe uint32_t offset_of_sgls, offset_of_flat_buffs = 0; 203a124830aSFiona Trahe int i; 204a124830aSFiona Trahe int num_im_sgls = qat_gen_config[ 205a124830aSFiona Trahe comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required; 206a124830aSFiona Trahe 207a124830aSFiona Trahe QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls", 208a124830aSFiona Trahe comp_dev->qat_dev->name, num_im_sgls); 209a124830aSFiona Trahe snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE, 210a124830aSFiona Trahe "%s_inter_buff", comp_dev->qat_dev->name); 211a124830aSFiona Trahe memzone = rte_memzone_lookup(inter_buff_mz_name); 212a124830aSFiona Trahe if (memzone != NULL) { 213a124830aSFiona Trahe QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already"); 214a124830aSFiona Trahe return memzone; 215a124830aSFiona Trahe } 216a124830aSFiona Trahe 217a124830aSFiona Trahe /* Create a memzone to hold intermediate buffers and associated 218cea6abe3SFiona Trahe * meta-data needed by the firmware. The memzone contains 3 parts: 219a124830aSFiona Trahe * - a list of num_im_sgls physical pointers to sgls 220cea6abe3SFiona Trahe * - the num_im_sgl sgl structures, each pointing to 221cea6abe3SFiona Trahe * QAT_NUM_BUFS_IN_IM_SGL flat buffers 222cea6abe3SFiona Trahe * - the flat buffers: num_im_sgl * QAT_NUM_BUFS_IN_IM_SGL 223cea6abe3SFiona Trahe * buffers, each of buff_size 224cea6abe3SFiona Trahe * num_im_sgls depends on the hardware generation of the device 225cea6abe3SFiona Trahe * buff_size comes from the user via the config file 226a124830aSFiona Trahe */ 227a124830aSFiona Trahe 228a124830aSFiona Trahe size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t); 229a124830aSFiona Trahe offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK)) 230a124830aSFiona Trahe & QAT_64_BYTE_ALIGN_MASK; 231a124830aSFiona Trahe offset_of_flat_buffs = 232a124830aSFiona Trahe offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl); 233a124830aSFiona Trahe full_size = offset_of_flat_buffs + 234a124830aSFiona Trahe num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL; 235a124830aSFiona Trahe 236a124830aSFiona Trahe memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size, 237a124830aSFiona Trahe comp_dev->compressdev->data->socket_id, 23825e95179SMarko Kovacevic RTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN); 239a124830aSFiona Trahe if (memzone == NULL) { 240a124830aSFiona Trahe QAT_LOG(ERR, "Can't allocate intermediate buffers" 241a124830aSFiona Trahe " for device %s", comp_dev->qat_dev->name); 242a124830aSFiona Trahe return NULL; 243a124830aSFiona Trahe } 244a124830aSFiona Trahe 245a124830aSFiona Trahe mz_start = (uint8_t *)memzone->addr; 246a124830aSFiona Trahe mz_start_phys = memzone->phys_addr; 247a124830aSFiona Trahe QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64 248a124830aSFiona Trahe ", size required %d, size created %zu", 249a124830aSFiona Trahe inter_buff_mz_name, mz_start, mz_start_phys, 250a124830aSFiona Trahe full_size, memzone->len); 251a124830aSFiona Trahe 252a124830aSFiona Trahe array_of_pointers = (struct array_of_ptrs *)mz_start; 253a124830aSFiona Trahe for (i = 0; i < num_im_sgls; i++) { 254a124830aSFiona Trahe uint32_t curr_sgl_offset = 255a124830aSFiona Trahe offset_of_sgls + i * sizeof(struct qat_inter_sgl); 256a124830aSFiona Trahe struct qat_inter_sgl *sgl = 257a124830aSFiona Trahe (struct qat_inter_sgl *)(mz_start + curr_sgl_offset); 258cea6abe3SFiona Trahe int lb; 259a124830aSFiona Trahe array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset; 260a124830aSFiona Trahe 261a124830aSFiona Trahe sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL; 262a124830aSFiona Trahe sgl->num_mapped_bufs = 0; 263a124830aSFiona Trahe sgl->resrvd = 0; 264a124830aSFiona Trahe 265a124830aSFiona Trahe #if QAT_IM_BUFFER_DEBUG 266a124830aSFiona Trahe QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers" 267a124830aSFiona Trahe " = 0x%"PRIx64, i, array_of_pointers->pointer[i]); 268a124830aSFiona Trahe QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl); 269a124830aSFiona Trahe #endif 270cea6abe3SFiona Trahe for (lb = 0; lb < QAT_NUM_BUFS_IN_IM_SGL; lb++) { 271cea6abe3SFiona Trahe sgl->buffers[lb].addr = 272cea6abe3SFiona Trahe mz_start_phys + offset_of_flat_buffs + 273cea6abe3SFiona Trahe (((i * QAT_NUM_BUFS_IN_IM_SGL) + lb) * buff_size); 274cea6abe3SFiona Trahe sgl->buffers[lb].len = buff_size; 275cea6abe3SFiona Trahe sgl->buffers[lb].resrvd = 0; 276cea6abe3SFiona Trahe #if QAT_IM_BUFFER_DEBUG 277cea6abe3SFiona Trahe QAT_LOG(DEBUG, 278cea6abe3SFiona Trahe " : sgl->buffers[%d].addr = 0x%"PRIx64", len=%d", 279cea6abe3SFiona Trahe lb, sgl->buffers[lb].addr, sgl->buffers[lb].len); 280cea6abe3SFiona Trahe #endif 281cea6abe3SFiona Trahe } 282a124830aSFiona Trahe } 283a124830aSFiona Trahe #if QAT_IM_BUFFER_DEBUG 284a124830aSFiona Trahe QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone start:", 285a124830aSFiona Trahe mz_start, offset_of_flat_buffs + 32); 286a124830aSFiona Trahe #endif 287a124830aSFiona Trahe return memzone; 288a124830aSFiona Trahe } 289a124830aSFiona Trahe 290a795248dSFiona Trahe static struct rte_mempool * 291a795248dSFiona Trahe qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev, 2921e796b11STomasz Jozwiak struct rte_compressdev_config *config, 293a795248dSFiona Trahe uint32_t num_elements) 294a795248dSFiona Trahe { 295a795248dSFiona Trahe char xform_pool_name[RTE_MEMPOOL_NAMESIZE]; 296a795248dSFiona Trahe struct rte_mempool *mp; 297a795248dSFiona Trahe 298a795248dSFiona Trahe snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE, 299a795248dSFiona Trahe "%s_xforms", comp_dev->qat_dev->name); 300a795248dSFiona Trahe 301a795248dSFiona Trahe QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name); 302a795248dSFiona Trahe mp = rte_mempool_lookup(xform_pool_name); 303a795248dSFiona Trahe 304a795248dSFiona Trahe if (mp != NULL) { 305a795248dSFiona Trahe QAT_LOG(DEBUG, "xformpool already created"); 306a795248dSFiona Trahe if (mp->size != num_elements) { 307a795248dSFiona Trahe QAT_LOG(DEBUG, "xformpool wrong size - delete it"); 308a795248dSFiona Trahe rte_mempool_free(mp); 309a795248dSFiona Trahe mp = NULL; 310a795248dSFiona Trahe comp_dev->xformpool = NULL; 311a795248dSFiona Trahe } 312a795248dSFiona Trahe } 313a795248dSFiona Trahe 314a795248dSFiona Trahe if (mp == NULL) 315a795248dSFiona Trahe mp = rte_mempool_create(xform_pool_name, 316a795248dSFiona Trahe num_elements, 317a795248dSFiona Trahe qat_comp_xform_size(), 0, 0, 3181e796b11STomasz Jozwiak NULL, NULL, NULL, NULL, config->socket_id, 319a795248dSFiona Trahe 0); 320a795248dSFiona Trahe if (mp == NULL) { 321a795248dSFiona Trahe QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d", 322a795248dSFiona Trahe xform_pool_name, num_elements, qat_comp_xform_size()); 323a795248dSFiona Trahe return NULL; 324a795248dSFiona Trahe } 325a795248dSFiona Trahe 326a795248dSFiona Trahe return mp; 327a795248dSFiona Trahe } 328a795248dSFiona Trahe 329a795248dSFiona Trahe static void 33082822753SAdam Dybkowski qat_comp_stream_init(struct rte_mempool *mp __rte_unused, void *opaque, 33182822753SAdam Dybkowski void *obj, unsigned int obj_idx) 33282822753SAdam Dybkowski { 33382822753SAdam Dybkowski struct stream_create_info *info = opaque; 33482822753SAdam Dybkowski struct qat_comp_stream *stream = obj; 33582822753SAdam Dybkowski char mz_name[RTE_MEMZONE_NAMESIZE]; 33682822753SAdam Dybkowski const struct rte_memzone *memzone; 33782822753SAdam Dybkowski struct qat_inter_sgl *ram_banks_desc; 33882822753SAdam Dybkowski 33982822753SAdam Dybkowski /* find a memzone for RAM banks */ 34082822753SAdam Dybkowski snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "%s_%u_rambanks", 34182822753SAdam Dybkowski info->comp_dev->qat_dev->name, obj_idx); 34282822753SAdam Dybkowski memzone = rte_memzone_lookup(mz_name); 34382822753SAdam Dybkowski if (memzone == NULL) { 34482822753SAdam Dybkowski /* allocate a memzone for compression state and RAM banks */ 34582822753SAdam Dybkowski memzone = rte_memzone_reserve_aligned(mz_name, 34682822753SAdam Dybkowski QAT_STATE_REGISTERS_MAX_SIZE 34782822753SAdam Dybkowski + sizeof(struct qat_inter_sgl) 34882822753SAdam Dybkowski + QAT_INFLATE_CONTEXT_SIZE, 34982822753SAdam Dybkowski info->socket_id, 35082822753SAdam Dybkowski RTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN); 35182822753SAdam Dybkowski if (memzone == NULL) { 35282822753SAdam Dybkowski QAT_LOG(ERR, 35382822753SAdam Dybkowski "Can't allocate RAM banks for device %s, object %u", 35482822753SAdam Dybkowski info->comp_dev->qat_dev->name, obj_idx); 35582822753SAdam Dybkowski info->error = -ENOMEM; 35682822753SAdam Dybkowski return; 35782822753SAdam Dybkowski } 35882822753SAdam Dybkowski } 35982822753SAdam Dybkowski 36082822753SAdam Dybkowski /* prepare the buffer list descriptor for RAM banks */ 36182822753SAdam Dybkowski ram_banks_desc = (struct qat_inter_sgl *) 36282822753SAdam Dybkowski (((uint8_t *) memzone->addr) + QAT_STATE_REGISTERS_MAX_SIZE); 36382822753SAdam Dybkowski ram_banks_desc->num_bufs = 1; 36482822753SAdam Dybkowski ram_banks_desc->buffers[0].len = QAT_INFLATE_CONTEXT_SIZE; 36582822753SAdam Dybkowski ram_banks_desc->buffers[0].addr = memzone->iova 36682822753SAdam Dybkowski + QAT_STATE_REGISTERS_MAX_SIZE 36782822753SAdam Dybkowski + sizeof(struct qat_inter_sgl); 36882822753SAdam Dybkowski 36982822753SAdam Dybkowski memset(stream, 0, qat_comp_stream_size()); 37082822753SAdam Dybkowski stream->memzone = memzone; 37182822753SAdam Dybkowski stream->state_registers_decomp = memzone->addr; 37282822753SAdam Dybkowski stream->state_registers_decomp_phys = memzone->iova; 37382822753SAdam Dybkowski stream->inflate_context = ((uint8_t *) memzone->addr) 37482822753SAdam Dybkowski + QAT_STATE_REGISTERS_MAX_SIZE; 37582822753SAdam Dybkowski stream->inflate_context_phys = memzone->iova 37682822753SAdam Dybkowski + QAT_STATE_REGISTERS_MAX_SIZE; 37782822753SAdam Dybkowski } 37882822753SAdam Dybkowski 37982822753SAdam Dybkowski static void 38082822753SAdam Dybkowski qat_comp_stream_destroy(struct rte_mempool *mp __rte_unused, 38182822753SAdam Dybkowski void *opaque __rte_unused, void *obj, 38282822753SAdam Dybkowski unsigned obj_idx __rte_unused) 38382822753SAdam Dybkowski { 38482822753SAdam Dybkowski struct qat_comp_stream *stream = obj; 38582822753SAdam Dybkowski 38682822753SAdam Dybkowski rte_memzone_free(stream->memzone); 38782822753SAdam Dybkowski } 38882822753SAdam Dybkowski 38982822753SAdam Dybkowski static struct rte_mempool * 39082822753SAdam Dybkowski qat_comp_create_stream_pool(struct qat_comp_dev_private *comp_dev, 39182822753SAdam Dybkowski int socket_id, 39282822753SAdam Dybkowski uint32_t num_elements) 39382822753SAdam Dybkowski { 39482822753SAdam Dybkowski char stream_pool_name[RTE_MEMPOOL_NAMESIZE]; 39582822753SAdam Dybkowski struct rte_mempool *mp; 39682822753SAdam Dybkowski 39782822753SAdam Dybkowski snprintf(stream_pool_name, RTE_MEMPOOL_NAMESIZE, 39882822753SAdam Dybkowski "%s_streams", comp_dev->qat_dev->name); 39982822753SAdam Dybkowski 40082822753SAdam Dybkowski QAT_LOG(DEBUG, "streampool: %s", stream_pool_name); 40182822753SAdam Dybkowski mp = rte_mempool_lookup(stream_pool_name); 40282822753SAdam Dybkowski 40382822753SAdam Dybkowski if (mp != NULL) { 40482822753SAdam Dybkowski QAT_LOG(DEBUG, "streampool already created"); 40582822753SAdam Dybkowski if (mp->size != num_elements) { 40682822753SAdam Dybkowski QAT_LOG(DEBUG, "streampool wrong size - delete it"); 40782822753SAdam Dybkowski rte_mempool_obj_iter(mp, qat_comp_stream_destroy, NULL); 40882822753SAdam Dybkowski rte_mempool_free(mp); 40982822753SAdam Dybkowski mp = NULL; 41082822753SAdam Dybkowski comp_dev->streampool = NULL; 41182822753SAdam Dybkowski } 41282822753SAdam Dybkowski } 41382822753SAdam Dybkowski 41482822753SAdam Dybkowski if (mp == NULL) { 41582822753SAdam Dybkowski struct stream_create_info info = { 41682822753SAdam Dybkowski .comp_dev = comp_dev, 41782822753SAdam Dybkowski .socket_id = socket_id, 41882822753SAdam Dybkowski .error = 0 41982822753SAdam Dybkowski }; 42082822753SAdam Dybkowski mp = rte_mempool_create(stream_pool_name, 42182822753SAdam Dybkowski num_elements, 42282822753SAdam Dybkowski qat_comp_stream_size(), 0, 0, 42382822753SAdam Dybkowski NULL, NULL, qat_comp_stream_init, &info, 42482822753SAdam Dybkowski socket_id, 0); 42582822753SAdam Dybkowski if (mp == NULL) { 42682822753SAdam Dybkowski QAT_LOG(ERR, 42782822753SAdam Dybkowski "Err creating mempool %s w %d elements of size %d", 42882822753SAdam Dybkowski stream_pool_name, num_elements, 42982822753SAdam Dybkowski qat_comp_stream_size()); 43082822753SAdam Dybkowski } else if (info.error) { 43182822753SAdam Dybkowski rte_mempool_obj_iter(mp, qat_comp_stream_destroy, NULL); 43282822753SAdam Dybkowski QAT_LOG(ERR, 43382822753SAdam Dybkowski "Destoying mempool %s as at least one element failed initialisation", 43482822753SAdam Dybkowski stream_pool_name); 43582822753SAdam Dybkowski rte_mempool_free(mp); 43682822753SAdam Dybkowski mp = NULL; 43782822753SAdam Dybkowski } 43882822753SAdam Dybkowski } 43982822753SAdam Dybkowski 44082822753SAdam Dybkowski return mp; 44182822753SAdam Dybkowski } 44282822753SAdam Dybkowski 44382822753SAdam Dybkowski static void 444a795248dSFiona Trahe _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev) 445a795248dSFiona Trahe { 446a124830aSFiona Trahe /* Free intermediate buffers */ 447a124830aSFiona Trahe if (comp_dev->interm_buff_mz) { 448a124830aSFiona Trahe rte_memzone_free(comp_dev->interm_buff_mz); 449a124830aSFiona Trahe comp_dev->interm_buff_mz = NULL; 450a124830aSFiona Trahe } 451a124830aSFiona Trahe 452a795248dSFiona Trahe /* Free private_xform pool */ 453a795248dSFiona Trahe if (comp_dev->xformpool) { 454a795248dSFiona Trahe /* Free internal mempool for private xforms */ 455a795248dSFiona Trahe rte_mempool_free(comp_dev->xformpool); 456a795248dSFiona Trahe comp_dev->xformpool = NULL; 457a795248dSFiona Trahe } 45882822753SAdam Dybkowski 45982822753SAdam Dybkowski /* Free stream pool */ 46082822753SAdam Dybkowski if (comp_dev->streampool) { 46182822753SAdam Dybkowski rte_mempool_obj_iter(comp_dev->streampool, 46282822753SAdam Dybkowski qat_comp_stream_destroy, NULL); 46382822753SAdam Dybkowski rte_mempool_free(comp_dev->streampool); 46482822753SAdam Dybkowski comp_dev->streampool = NULL; 46582822753SAdam Dybkowski } 466a795248dSFiona Trahe } 467a795248dSFiona Trahe 468edd37ac1SFiona Trahe static int 469a795248dSFiona Trahe qat_comp_dev_config(struct rte_compressdev *dev, 470a795248dSFiona Trahe struct rte_compressdev_config *config) 471a795248dSFiona Trahe { 472a795248dSFiona Trahe struct qat_comp_dev_private *comp_dev = dev->data->dev_private; 473a795248dSFiona Trahe int ret = 0; 474a795248dSFiona Trahe 475a124830aSFiona Trahe if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) { 476a124830aSFiona Trahe QAT_LOG(WARNING, 477a124830aSFiona Trahe "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so" 478a124830aSFiona Trahe " QAT device can't be used for Dynamic Deflate. " 479a124830aSFiona Trahe "Did you really intend to do this?"); 480a124830aSFiona Trahe } else { 481a124830aSFiona Trahe comp_dev->interm_buff_mz = 482a124830aSFiona Trahe qat_comp_setup_inter_buffers(comp_dev, 483a124830aSFiona Trahe RTE_PMD_QAT_COMP_IM_BUFFER_SIZE); 484a124830aSFiona Trahe if (comp_dev->interm_buff_mz == NULL) { 485a124830aSFiona Trahe ret = -ENOMEM; 486a124830aSFiona Trahe goto error_out; 487a124830aSFiona Trahe } 488a124830aSFiona Trahe } 489a124830aSFiona Trahe 49082822753SAdam Dybkowski if (config->max_nb_priv_xforms) { 49182822753SAdam Dybkowski comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev, 49282822753SAdam Dybkowski config, config->max_nb_priv_xforms); 493a795248dSFiona Trahe if (comp_dev->xformpool == NULL) { 494a795248dSFiona Trahe ret = -ENOMEM; 495a795248dSFiona Trahe goto error_out; 496a795248dSFiona Trahe } 49782822753SAdam Dybkowski } else 49882822753SAdam Dybkowski comp_dev->xformpool = NULL; 49982822753SAdam Dybkowski 50082822753SAdam Dybkowski if (config->max_nb_streams) { 50182822753SAdam Dybkowski comp_dev->streampool = qat_comp_create_stream_pool(comp_dev, 50282822753SAdam Dybkowski config->socket_id, config->max_nb_streams); 50382822753SAdam Dybkowski if (comp_dev->streampool == NULL) { 50482822753SAdam Dybkowski ret = -ENOMEM; 50582822753SAdam Dybkowski goto error_out; 50682822753SAdam Dybkowski } 50782822753SAdam Dybkowski } else 50882822753SAdam Dybkowski comp_dev->streampool = NULL; 50982822753SAdam Dybkowski 510a795248dSFiona Trahe return 0; 511a795248dSFiona Trahe 512a795248dSFiona Trahe error_out: 513a795248dSFiona Trahe _qat_comp_dev_config_clear(comp_dev); 514a795248dSFiona Trahe return ret; 515a795248dSFiona Trahe } 516a795248dSFiona Trahe 517edd37ac1SFiona Trahe static int 518d8d380adSFiona Trahe qat_comp_dev_start(struct rte_compressdev *dev __rte_unused) 519d8d380adSFiona Trahe { 520d8d380adSFiona Trahe return 0; 521d8d380adSFiona Trahe } 522d8d380adSFiona Trahe 523edd37ac1SFiona Trahe static void 524d8d380adSFiona Trahe qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused) 525d8d380adSFiona Trahe { 526d8d380adSFiona Trahe 527d8d380adSFiona Trahe } 528a795248dSFiona Trahe 529edd37ac1SFiona Trahe static int 530a795248dSFiona Trahe qat_comp_dev_close(struct rte_compressdev *dev) 531a795248dSFiona Trahe { 532a795248dSFiona Trahe int i; 533a795248dSFiona Trahe int ret = 0; 534a795248dSFiona Trahe struct qat_comp_dev_private *comp_dev = dev->data->dev_private; 535a795248dSFiona Trahe 536a795248dSFiona Trahe for (i = 0; i < dev->data->nb_queue_pairs; i++) { 537a795248dSFiona Trahe ret = qat_comp_qp_release(dev, i); 538a795248dSFiona Trahe if (ret < 0) 539a795248dSFiona Trahe return ret; 540a795248dSFiona Trahe } 541a795248dSFiona Trahe 542a795248dSFiona Trahe _qat_comp_dev_config_clear(comp_dev); 543a795248dSFiona Trahe 544a795248dSFiona Trahe return ret; 545a795248dSFiona Trahe } 54684aaaf8eSFiona Trahe 54784aaaf8eSFiona Trahe 548edd37ac1SFiona Trahe static void 54984aaaf8eSFiona Trahe qat_comp_dev_info_get(struct rte_compressdev *dev, 55084aaaf8eSFiona Trahe struct rte_compressdev_info *info) 55184aaaf8eSFiona Trahe { 55284aaaf8eSFiona Trahe struct qat_comp_dev_private *comp_dev = dev->data->dev_private; 55384aaaf8eSFiona Trahe const struct qat_qp_hw_data *comp_hw_qps = 55484aaaf8eSFiona Trahe qat_gen_config[comp_dev->qat_dev->qat_dev_gen] 55584aaaf8eSFiona Trahe .qp_hw_data[QAT_SERVICE_COMPRESSION]; 55684aaaf8eSFiona Trahe 55784aaaf8eSFiona Trahe if (info != NULL) { 55884aaaf8eSFiona Trahe info->max_nb_queue_pairs = 55984aaaf8eSFiona Trahe qat_qps_per_service(comp_hw_qps, 56084aaaf8eSFiona Trahe QAT_SERVICE_COMPRESSION); 56184aaaf8eSFiona Trahe info->feature_flags = dev->feature_flags; 56284aaaf8eSFiona Trahe info->capabilities = comp_dev->qat_dev_capabilities; 56384aaaf8eSFiona Trahe } 56484aaaf8eSFiona Trahe } 565a232ca8bSFiona Trahe 566c0c90bc4SFiona Trahe static uint16_t 5672519de89SFiona Trahe qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused, 5682519de89SFiona Trahe struct rte_comp_op **ops __rte_unused, 5692519de89SFiona Trahe uint16_t nb_ops __rte_unused) 5702519de89SFiona Trahe { 5712519de89SFiona Trahe QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !"); 5722519de89SFiona Trahe return 0; 5732519de89SFiona Trahe } 5742519de89SFiona Trahe 5752519de89SFiona Trahe static struct rte_compressdev_ops compress_qat_dummy_ops = { 5762519de89SFiona Trahe 5772519de89SFiona Trahe /* Device related operations */ 5782519de89SFiona Trahe .dev_configure = NULL, 5792519de89SFiona Trahe .dev_start = NULL, 5802519de89SFiona Trahe .dev_stop = qat_comp_dev_stop, 5812519de89SFiona Trahe .dev_close = qat_comp_dev_close, 5822519de89SFiona Trahe .dev_infos_get = NULL, 5832519de89SFiona Trahe 5842519de89SFiona Trahe .stats_get = NULL, 5852519de89SFiona Trahe .stats_reset = qat_comp_stats_reset, 5862519de89SFiona Trahe .queue_pair_setup = NULL, 5872519de89SFiona Trahe .queue_pair_release = qat_comp_qp_release, 5882519de89SFiona Trahe 5892519de89SFiona Trahe /* Compression related operations */ 5902519de89SFiona Trahe .private_xform_create = NULL, 5912519de89SFiona Trahe .private_xform_free = qat_comp_private_xform_free 5922519de89SFiona Trahe }; 5932519de89SFiona Trahe 5942519de89SFiona Trahe static uint16_t 595*c13cecf6SAdam Dybkowski qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops, 5962519de89SFiona Trahe uint16_t nb_ops) 5972519de89SFiona Trahe { 5982519de89SFiona Trahe uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops); 5992519de89SFiona Trahe struct qat_qp *tmp_qp = (struct qat_qp *)qp; 6002519de89SFiona Trahe 6012519de89SFiona Trahe if (ret) { 6022519de89SFiona Trahe if ((*ops)->debug_status == 6032519de89SFiona Trahe (uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) { 6042519de89SFiona Trahe tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst = 6052519de89SFiona Trahe qat_comp_pmd_enq_deq_dummy_op_burst; 6062519de89SFiona Trahe tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst = 6072519de89SFiona Trahe qat_comp_pmd_enq_deq_dummy_op_burst; 6082519de89SFiona Trahe 6092519de89SFiona Trahe tmp_qp->qat_dev->comp_dev->compressdev->dev_ops = 6102519de89SFiona Trahe &compress_qat_dummy_ops; 6112519de89SFiona Trahe QAT_LOG(ERR, "QAT PMD detected wrong FW version !"); 6122519de89SFiona Trahe 6132519de89SFiona Trahe } else { 6142519de89SFiona Trahe tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst = 615*c13cecf6SAdam Dybkowski (compressdev_dequeue_pkt_burst_t) 616*c13cecf6SAdam Dybkowski qat_dequeue_op_burst; 6172519de89SFiona Trahe } 6182519de89SFiona Trahe } 6192519de89SFiona Trahe return ret; 6202519de89SFiona Trahe } 621edd37ac1SFiona Trahe 622c0c90bc4SFiona Trahe static struct rte_compressdev_ops compress_qat_ops = { 623edd37ac1SFiona Trahe 624edd37ac1SFiona Trahe /* Device related operations */ 625edd37ac1SFiona Trahe .dev_configure = qat_comp_dev_config, 626edd37ac1SFiona Trahe .dev_start = qat_comp_dev_start, 627edd37ac1SFiona Trahe .dev_stop = qat_comp_dev_stop, 628edd37ac1SFiona Trahe .dev_close = qat_comp_dev_close, 629edd37ac1SFiona Trahe .dev_infos_get = qat_comp_dev_info_get, 630edd37ac1SFiona Trahe 631edd37ac1SFiona Trahe .stats_get = qat_comp_stats_get, 632edd37ac1SFiona Trahe .stats_reset = qat_comp_stats_reset, 633edd37ac1SFiona Trahe .queue_pair_setup = qat_comp_qp_setup, 634edd37ac1SFiona Trahe .queue_pair_release = qat_comp_qp_release, 635edd37ac1SFiona Trahe 636edd37ac1SFiona Trahe /* Compression related operations */ 637edd37ac1SFiona Trahe .private_xform_create = qat_comp_private_xform_create, 63882822753SAdam Dybkowski .private_xform_free = qat_comp_private_xform_free, 63982822753SAdam Dybkowski .stream_create = qat_comp_stream_create, 64082822753SAdam Dybkowski .stream_free = qat_comp_stream_free 641edd37ac1SFiona Trahe }; 642c0c90bc4SFiona Trahe 643df8cca46SFiona Trahe /* An rte_driver is needed in the registration of the device with compressdev. 644df8cca46SFiona Trahe * The actual qat pci's rte_driver can't be used as its name represents 645df8cca46SFiona Trahe * the whole pci device with all services. Think of this as a holder for a name 646df8cca46SFiona Trahe * for the compression part of the pci device. 647df8cca46SFiona Trahe */ 648df8cca46SFiona Trahe static const char qat_comp_drv_name[] = RTE_STR(COMPRESSDEV_NAME_QAT_PMD); 649df8cca46SFiona Trahe static const struct rte_driver compdev_qat_driver = { 650df8cca46SFiona Trahe .name = qat_comp_drv_name, 651df8cca46SFiona Trahe .alias = qat_comp_drv_name 652df8cca46SFiona Trahe }; 653c0c90bc4SFiona Trahe int 65447c3f7a4SArek Kusztal qat_comp_dev_create(struct qat_pci_device *qat_pci_dev, 65547c3f7a4SArek Kusztal struct qat_dev_cmd_param *qat_dev_cmd_param) 656c0c90bc4SFiona Trahe { 65747c3f7a4SArek Kusztal int i = 0; 658a124830aSFiona Trahe if (qat_pci_dev->qat_dev_gen == QAT_GEN3) { 6599cd9d3e7SAdam Dybkowski QAT_LOG(ERR, "Compression PMD not supported on QAT P5xxx"); 660a124830aSFiona Trahe return 0; 661a124830aSFiona Trahe } 662c0c90bc4SFiona Trahe 663c0c90bc4SFiona Trahe struct rte_compressdev_pmd_init_params init_params = { 664c0c90bc4SFiona Trahe .name = "", 665c0c90bc4SFiona Trahe .socket_id = qat_pci_dev->pci_dev->device.numa_node, 666c0c90bc4SFiona Trahe }; 667c0c90bc4SFiona Trahe char name[RTE_COMPRESSDEV_NAME_MAX_LEN]; 668c0c90bc4SFiona Trahe struct rte_compressdev *compressdev; 669c0c90bc4SFiona Trahe struct qat_comp_dev_private *comp_dev; 670c0c90bc4SFiona Trahe 671c0c90bc4SFiona Trahe snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s", 672c0c90bc4SFiona Trahe qat_pci_dev->name, "comp"); 673c0c90bc4SFiona Trahe QAT_LOG(DEBUG, "Creating QAT COMP device %s", name); 674c0c90bc4SFiona Trahe 675df8cca46SFiona Trahe /* Populate subset device to use in compressdev device creation */ 676df8cca46SFiona Trahe qat_pci_dev->comp_rte_dev.driver = &compdev_qat_driver; 677df8cca46SFiona Trahe qat_pci_dev->comp_rte_dev.numa_node = 678df8cca46SFiona Trahe qat_pci_dev->pci_dev->device.numa_node; 679df8cca46SFiona Trahe qat_pci_dev->comp_rte_dev.devargs = NULL; 680df8cca46SFiona Trahe 681c0c90bc4SFiona Trahe compressdev = rte_compressdev_pmd_create(name, 682df8cca46SFiona Trahe &(qat_pci_dev->comp_rte_dev), 683c0c90bc4SFiona Trahe sizeof(struct qat_comp_dev_private), 684c0c90bc4SFiona Trahe &init_params); 685c0c90bc4SFiona Trahe 686c0c90bc4SFiona Trahe if (compressdev == NULL) 687c0c90bc4SFiona Trahe return -ENODEV; 688c0c90bc4SFiona Trahe 689c0c90bc4SFiona Trahe compressdev->dev_ops = &compress_qat_ops; 690c0c90bc4SFiona Trahe 691*c13cecf6SAdam Dybkowski compressdev->enqueue_burst = (compressdev_enqueue_pkt_burst_t) 692*c13cecf6SAdam Dybkowski qat_enqueue_comp_op_burst; 693*c13cecf6SAdam Dybkowski compressdev->dequeue_burst = qat_comp_pmd_dequeue_first_op_burst; 694c0c90bc4SFiona Trahe 695c0c90bc4SFiona Trahe compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 696c0c90bc4SFiona Trahe 697c0c90bc4SFiona Trahe comp_dev = compressdev->data->dev_private; 698c0c90bc4SFiona Trahe comp_dev->qat_dev = qat_pci_dev; 699c0c90bc4SFiona Trahe comp_dev->compressdev = compressdev; 700c0c90bc4SFiona Trahe qat_pci_dev->comp_dev = comp_dev; 701c0c90bc4SFiona Trahe 702c0c90bc4SFiona Trahe switch (qat_pci_dev->qat_dev_gen) { 703c0c90bc4SFiona Trahe case QAT_GEN1: 704c0c90bc4SFiona Trahe case QAT_GEN2: 7051f5e4053SFiona Trahe case QAT_GEN3: 706c0c90bc4SFiona Trahe comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities; 707c0c90bc4SFiona Trahe break; 708c0c90bc4SFiona Trahe default: 709c0c90bc4SFiona Trahe comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities; 710c0c90bc4SFiona Trahe QAT_LOG(DEBUG, 711c0c90bc4SFiona Trahe "QAT gen %d capabilities unknown, default to GEN1", 712c0c90bc4SFiona Trahe qat_pci_dev->qat_dev_gen); 713c0c90bc4SFiona Trahe break; 714c0c90bc4SFiona Trahe } 715c0c90bc4SFiona Trahe 71647c3f7a4SArek Kusztal while (1) { 71747c3f7a4SArek Kusztal if (qat_dev_cmd_param[i].name == NULL) 71847c3f7a4SArek Kusztal break; 71947c3f7a4SArek Kusztal if (!strcmp(qat_dev_cmd_param[i].name, COMP_ENQ_THRESHOLD_NAME)) 72047c3f7a4SArek Kusztal comp_dev->min_enq_burst_threshold = 72147c3f7a4SArek Kusztal qat_dev_cmd_param[i].val; 72247c3f7a4SArek Kusztal i++; 72347c3f7a4SArek Kusztal } 72447c3f7a4SArek Kusztal 725c0c90bc4SFiona Trahe QAT_LOG(DEBUG, 726c0c90bc4SFiona Trahe "Created QAT COMP device %s as compressdev instance %d", 727c0c90bc4SFiona Trahe name, compressdev->data->dev_id); 728c0c90bc4SFiona Trahe return 0; 729c0c90bc4SFiona Trahe } 730c0c90bc4SFiona Trahe 731c0c90bc4SFiona Trahe int 732c0c90bc4SFiona Trahe qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev) 733c0c90bc4SFiona Trahe { 734c0c90bc4SFiona Trahe struct qat_comp_dev_private *comp_dev; 735c0c90bc4SFiona Trahe 736c0c90bc4SFiona Trahe if (qat_pci_dev == NULL) 737c0c90bc4SFiona Trahe return -ENODEV; 738c0c90bc4SFiona Trahe 739c0c90bc4SFiona Trahe comp_dev = qat_pci_dev->comp_dev; 740c0c90bc4SFiona Trahe if (comp_dev == NULL) 741c0c90bc4SFiona Trahe return 0; 742c0c90bc4SFiona Trahe 743c0c90bc4SFiona Trahe /* clean up any resources used by the device */ 744c0c90bc4SFiona Trahe qat_comp_dev_close(comp_dev->compressdev); 745c0c90bc4SFiona Trahe 746c0c90bc4SFiona Trahe rte_compressdev_pmd_destroy(comp_dev->compressdev); 747c0c90bc4SFiona Trahe qat_pci_dev->comp_dev = NULL; 748c0c90bc4SFiona Trahe 749c0c90bc4SFiona Trahe return 0; 750c0c90bc4SFiona Trahe } 751