xref: /dpdk/drivers/compress/qat/qat_comp_pmd.c (revision 9cd9d3e702fba4700539c1a2eddac13dd14ecf70)
17a34c215SFiona Trahe /* SPDX-License-Identifier: BSD-3-Clause
235233274STomasz Jozwiak  * Copyright(c) 2015-2019 Intel Corporation
37a34c215SFiona Trahe  */
47a34c215SFiona Trahe 
535233274STomasz Jozwiak #include <rte_malloc.h>
635233274STomasz Jozwiak 
7be8343b0SFiona Trahe #include "qat_comp.h"
87a34c215SFiona Trahe #include "qat_comp_pmd.h"
972385564SFiona Trahe 
1035233274STomasz Jozwiak #define QAT_PMD_COMP_SGL_DEF_SEGMENTS 16
1135233274STomasz Jozwiak 
1282822753SAdam Dybkowski struct stream_create_info {
1382822753SAdam Dybkowski 	struct qat_comp_dev_private *comp_dev;
1482822753SAdam Dybkowski 	int socket_id;
1582822753SAdam Dybkowski 	int error;
1682822753SAdam Dybkowski };
1782822753SAdam Dybkowski 
18c0c90bc4SFiona Trahe static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
19c0c90bc4SFiona Trahe 	{/* COMPRESSION - deflate */
20c0c90bc4SFiona Trahe 	 .algo = RTE_COMP_ALGO_DEFLATE,
21c0c90bc4SFiona Trahe 	 .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
22c0c90bc4SFiona Trahe 				RTE_COMP_FF_CRC32_CHECKSUM |
23c0c90bc4SFiona Trahe 				RTE_COMP_FF_ADLER32_CHECKSUM |
24c0c90bc4SFiona Trahe 				RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
25c0c90bc4SFiona Trahe 				RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
261947bd18SFiona Trahe 				RTE_COMP_FF_HUFFMAN_FIXED |
27a124830aSFiona Trahe 				RTE_COMP_FF_HUFFMAN_DYNAMIC |
281947bd18SFiona Trahe 				RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
291947bd18SFiona Trahe 				RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
3082822753SAdam Dybkowski 				RTE_COMP_FF_OOP_LB_IN_SGL_OUT |
3182822753SAdam Dybkowski 				RTE_COMP_FF_STATEFUL_DECOMPRESSION,
32c0c90bc4SFiona Trahe 	 .window_size = {.min = 15, .max = 15, .increment = 0} },
33c0c90bc4SFiona Trahe 	{RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
34c0c90bc4SFiona Trahe 
35edd37ac1SFiona Trahe static void
3672385564SFiona Trahe qat_comp_stats_get(struct rte_compressdev *dev,
3772385564SFiona Trahe 		struct rte_compressdev_stats *stats)
3872385564SFiona Trahe {
3972385564SFiona Trahe 	struct qat_common_stats qat_stats = {0};
4072385564SFiona Trahe 	struct qat_comp_dev_private *qat_priv;
4172385564SFiona Trahe 
4272385564SFiona Trahe 	if (stats == NULL || dev == NULL) {
4372385564SFiona Trahe 		QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
4472385564SFiona Trahe 		return;
4572385564SFiona Trahe 	}
4672385564SFiona Trahe 	qat_priv = dev->data->dev_private;
4772385564SFiona Trahe 
4872385564SFiona Trahe 	qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
4972385564SFiona Trahe 	stats->enqueued_count = qat_stats.enqueued_count;
5072385564SFiona Trahe 	stats->dequeued_count = qat_stats.dequeued_count;
5172385564SFiona Trahe 	stats->enqueue_err_count = qat_stats.enqueue_err_count;
5272385564SFiona Trahe 	stats->dequeue_err_count = qat_stats.dequeue_err_count;
5372385564SFiona Trahe }
5472385564SFiona Trahe 
55edd37ac1SFiona Trahe static void
5672385564SFiona Trahe qat_comp_stats_reset(struct rte_compressdev *dev)
5772385564SFiona Trahe {
5872385564SFiona Trahe 	struct qat_comp_dev_private *qat_priv;
5972385564SFiona Trahe 
6072385564SFiona Trahe 	if (dev == NULL) {
6172385564SFiona Trahe 		QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
6272385564SFiona Trahe 		return;
6372385564SFiona Trahe 	}
6472385564SFiona Trahe 	qat_priv = dev->data->dev_private;
6572385564SFiona Trahe 
6672385564SFiona Trahe 	qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
6772385564SFiona Trahe 
6872385564SFiona Trahe }
69be8343b0SFiona Trahe 
70edd37ac1SFiona Trahe static int
71be8343b0SFiona Trahe qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
72be8343b0SFiona Trahe {
73be8343b0SFiona Trahe 	struct qat_comp_dev_private *qat_private = dev->data->dev_private;
7435233274STomasz Jozwiak 	struct qat_qp **qp_addr =
7535233274STomasz Jozwiak 		(struct qat_qp **)&(dev->data->queue_pairs[queue_pair_id]);
7635233274STomasz Jozwiak 	struct qat_qp *qp = (struct qat_qp *)*qp_addr;
7735233274STomasz Jozwiak 	uint32_t i;
78be8343b0SFiona Trahe 
79be8343b0SFiona Trahe 	QAT_LOG(DEBUG, "Release comp qp %u on device %d",
80be8343b0SFiona Trahe 				queue_pair_id, dev->data->dev_id);
81be8343b0SFiona Trahe 
82be8343b0SFiona Trahe 	qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
83be8343b0SFiona Trahe 						= NULL;
84be8343b0SFiona Trahe 
8535233274STomasz Jozwiak 	for (i = 0; i < qp->nb_descriptors; i++) {
8635233274STomasz Jozwiak 
8735233274STomasz Jozwiak 		struct qat_comp_op_cookie *cookie = qp->op_cookies[i];
8835233274STomasz Jozwiak 
8935233274STomasz Jozwiak 		rte_free(cookie->qat_sgl_src_d);
9035233274STomasz Jozwiak 		rte_free(cookie->qat_sgl_dst_d);
9135233274STomasz Jozwiak 	}
9235233274STomasz Jozwiak 
93be8343b0SFiona Trahe 	return qat_qp_release((struct qat_qp **)
94be8343b0SFiona Trahe 			&(dev->data->queue_pairs[queue_pair_id]));
95be8343b0SFiona Trahe }
96be8343b0SFiona Trahe 
97edd37ac1SFiona Trahe static int
98be8343b0SFiona Trahe qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
99be8343b0SFiona Trahe 		  uint32_t max_inflight_ops, int socket_id)
100be8343b0SFiona Trahe {
1011947bd18SFiona Trahe 	struct qat_qp *qp;
102be8343b0SFiona Trahe 	int ret = 0;
1031947bd18SFiona Trahe 	uint32_t i;
104be8343b0SFiona Trahe 	struct qat_qp_config qat_qp_conf;
105be8343b0SFiona Trahe 
106be8343b0SFiona Trahe 	struct qat_qp **qp_addr =
107be8343b0SFiona Trahe 			(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
108be8343b0SFiona Trahe 	struct qat_comp_dev_private *qat_private = dev->data->dev_private;
109be8343b0SFiona Trahe 	const struct qat_qp_hw_data *comp_hw_qps =
110be8343b0SFiona Trahe 			qat_gen_config[qat_private->qat_dev->qat_dev_gen]
111be8343b0SFiona Trahe 				      .qp_hw_data[QAT_SERVICE_COMPRESSION];
112be8343b0SFiona Trahe 	const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
113be8343b0SFiona Trahe 
114be8343b0SFiona Trahe 	/* If qp is already in use free ring memory and qp metadata. */
115be8343b0SFiona Trahe 	if (*qp_addr != NULL) {
116be8343b0SFiona Trahe 		ret = qat_comp_qp_release(dev, qp_id);
117be8343b0SFiona Trahe 		if (ret < 0)
118be8343b0SFiona Trahe 			return ret;
119be8343b0SFiona Trahe 	}
120be8343b0SFiona Trahe 	if (qp_id >= qat_qps_per_service(comp_hw_qps,
121be8343b0SFiona Trahe 					 QAT_SERVICE_COMPRESSION)) {
122be8343b0SFiona Trahe 		QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
123be8343b0SFiona Trahe 		return -EINVAL;
124be8343b0SFiona Trahe 	}
125be8343b0SFiona Trahe 
126be8343b0SFiona Trahe 	qat_qp_conf.hw = qp_hw_data;
127be8343b0SFiona Trahe 	qat_qp_conf.build_request = qat_comp_build_request;
128be8343b0SFiona Trahe 	qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
129be8343b0SFiona Trahe 	qat_qp_conf.nb_descriptors = max_inflight_ops;
130be8343b0SFiona Trahe 	qat_qp_conf.socket_id = socket_id;
131be8343b0SFiona Trahe 	qat_qp_conf.service_str = "comp";
132be8343b0SFiona Trahe 
133be8343b0SFiona Trahe 	ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
134be8343b0SFiona Trahe 	if (ret != 0)
135be8343b0SFiona Trahe 		return ret;
136be8343b0SFiona Trahe 
137be8343b0SFiona Trahe 	/* store a link to the qp in the qat_pci_device */
138be8343b0SFiona Trahe 	qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
139be8343b0SFiona Trahe 								= *qp_addr;
140be8343b0SFiona Trahe 
1411947bd18SFiona Trahe 	qp = (struct qat_qp *)*qp_addr;
14247c3f7a4SArek Kusztal 	qp->min_enq_burst_threshold = qat_private->min_enq_burst_threshold;
1431947bd18SFiona Trahe 
1441947bd18SFiona Trahe 	for (i = 0; i < qp->nb_descriptors; i++) {
1451947bd18SFiona Trahe 
1461947bd18SFiona Trahe 		struct qat_comp_op_cookie *cookie =
1471947bd18SFiona Trahe 				qp->op_cookies[i];
1481947bd18SFiona Trahe 
14935233274STomasz Jozwiak 		cookie->qat_sgl_src_d = rte_zmalloc_socket(NULL,
15035233274STomasz Jozwiak 					sizeof(struct qat_sgl) +
15135233274STomasz Jozwiak 					sizeof(struct qat_flat_buf) *
15235233274STomasz Jozwiak 					QAT_PMD_COMP_SGL_DEF_SEGMENTS,
15335233274STomasz Jozwiak 					64, dev->data->socket_id);
15435233274STomasz Jozwiak 
15535233274STomasz Jozwiak 		cookie->qat_sgl_dst_d = rte_zmalloc_socket(NULL,
15635233274STomasz Jozwiak 					sizeof(struct qat_sgl) +
15735233274STomasz Jozwiak 					sizeof(struct qat_flat_buf) *
15835233274STomasz Jozwiak 					QAT_PMD_COMP_SGL_DEF_SEGMENTS,
15935233274STomasz Jozwiak 					64, dev->data->socket_id);
16035233274STomasz Jozwiak 
16135233274STomasz Jozwiak 		if (cookie->qat_sgl_src_d == NULL ||
16235233274STomasz Jozwiak 				cookie->qat_sgl_dst_d == NULL) {
16335233274STomasz Jozwiak 			QAT_LOG(ERR, "Can't allocate SGL"
16435233274STomasz Jozwiak 				     " for device %s",
16535233274STomasz Jozwiak 				     qat_private->qat_dev->name);
16635233274STomasz Jozwiak 			return -ENOMEM;
16735233274STomasz Jozwiak 		}
16835233274STomasz Jozwiak 
1691947bd18SFiona Trahe 		cookie->qat_sgl_src_phys_addr =
17035233274STomasz Jozwiak 				rte_malloc_virt2iova(cookie->qat_sgl_src_d);
1711947bd18SFiona Trahe 
1721947bd18SFiona Trahe 		cookie->qat_sgl_dst_phys_addr =
17335233274STomasz Jozwiak 				rte_malloc_virt2iova(cookie->qat_sgl_dst_d);
17435233274STomasz Jozwiak 
17535233274STomasz Jozwiak 		cookie->dst_nb_elems = cookie->src_nb_elems =
17635233274STomasz Jozwiak 				QAT_PMD_COMP_SGL_DEF_SEGMENTS;
17735233274STomasz Jozwiak 
17835233274STomasz Jozwiak 		cookie->socket_id = dev->data->socket_id;
179b643808fSTomasz Jozwiak 
180b643808fSTomasz Jozwiak 		cookie->error = 0;
1811947bd18SFiona Trahe 	}
1821947bd18SFiona Trahe 
183be8343b0SFiona Trahe 	return ret;
184be8343b0SFiona Trahe }
185a795248dSFiona Trahe 
186a124830aSFiona Trahe 
187a124830aSFiona Trahe #define QAT_IM_BUFFER_DEBUG 0
188a124830aSFiona Trahe static const struct rte_memzone *
189a124830aSFiona Trahe qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
190a124830aSFiona Trahe 			      uint32_t buff_size)
191a124830aSFiona Trahe {
192a124830aSFiona Trahe 	char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
193a124830aSFiona Trahe 	const struct rte_memzone *memzone;
194a124830aSFiona Trahe 	uint8_t *mz_start = NULL;
195a124830aSFiona Trahe 	rte_iova_t mz_start_phys = 0;
196a124830aSFiona Trahe 	struct array_of_ptrs *array_of_pointers;
197a124830aSFiona Trahe 	int size_of_ptr_array;
198a124830aSFiona Trahe 	uint32_t full_size;
199a124830aSFiona Trahe 	uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
200a124830aSFiona Trahe 	int i;
201a124830aSFiona Trahe 	int num_im_sgls = qat_gen_config[
202a124830aSFiona Trahe 		comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
203a124830aSFiona Trahe 
204a124830aSFiona Trahe 	QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
205a124830aSFiona Trahe 				comp_dev->qat_dev->name, num_im_sgls);
206a124830aSFiona Trahe 	snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
207a124830aSFiona Trahe 				"%s_inter_buff", comp_dev->qat_dev->name);
208a124830aSFiona Trahe 	memzone = rte_memzone_lookup(inter_buff_mz_name);
209a124830aSFiona Trahe 	if (memzone != NULL) {
210a124830aSFiona Trahe 		QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
211a124830aSFiona Trahe 		return memzone;
212a124830aSFiona Trahe 	}
213a124830aSFiona Trahe 
214a124830aSFiona Trahe 	/* Create a memzone to hold intermediate buffers and associated
215cea6abe3SFiona Trahe 	 * meta-data needed by the firmware. The memzone contains 3 parts:
216a124830aSFiona Trahe 	 *  - a list of num_im_sgls physical pointers to sgls
217cea6abe3SFiona Trahe 	 *  - the num_im_sgl sgl structures, each pointing to
218cea6abe3SFiona Trahe 	 *    QAT_NUM_BUFS_IN_IM_SGL flat buffers
219cea6abe3SFiona Trahe 	 *  - the flat buffers: num_im_sgl * QAT_NUM_BUFS_IN_IM_SGL
220cea6abe3SFiona Trahe 	 *    buffers, each of buff_size
221cea6abe3SFiona Trahe 	 * num_im_sgls depends on the hardware generation of the device
222cea6abe3SFiona Trahe 	 * buff_size comes from the user via the config file
223a124830aSFiona Trahe 	 */
224a124830aSFiona Trahe 
225a124830aSFiona Trahe 	size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
226a124830aSFiona Trahe 	offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
227a124830aSFiona Trahe 			& QAT_64_BYTE_ALIGN_MASK;
228a124830aSFiona Trahe 	offset_of_flat_buffs =
229a124830aSFiona Trahe 	    offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
230a124830aSFiona Trahe 	full_size = offset_of_flat_buffs +
231a124830aSFiona Trahe 			num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
232a124830aSFiona Trahe 
233a124830aSFiona Trahe 	memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
234a124830aSFiona Trahe 			comp_dev->compressdev->data->socket_id,
23525e95179SMarko Kovacevic 			RTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN);
236a124830aSFiona Trahe 	if (memzone == NULL) {
237a124830aSFiona Trahe 		QAT_LOG(ERR, "Can't allocate intermediate buffers"
238a124830aSFiona Trahe 				" for device %s", comp_dev->qat_dev->name);
239a124830aSFiona Trahe 		return NULL;
240a124830aSFiona Trahe 	}
241a124830aSFiona Trahe 
242a124830aSFiona Trahe 	mz_start = (uint8_t *)memzone->addr;
243a124830aSFiona Trahe 	mz_start_phys = memzone->phys_addr;
244a124830aSFiona Trahe 	QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
245a124830aSFiona Trahe 			", size required %d, size created %zu",
246a124830aSFiona Trahe 			inter_buff_mz_name, mz_start, mz_start_phys,
247a124830aSFiona Trahe 			full_size, memzone->len);
248a124830aSFiona Trahe 
249a124830aSFiona Trahe 	array_of_pointers = (struct array_of_ptrs *)mz_start;
250a124830aSFiona Trahe 	for (i = 0; i < num_im_sgls; i++) {
251a124830aSFiona Trahe 		uint32_t curr_sgl_offset =
252a124830aSFiona Trahe 		    offset_of_sgls + i * sizeof(struct qat_inter_sgl);
253a124830aSFiona Trahe 		struct qat_inter_sgl *sgl =
254a124830aSFiona Trahe 		    (struct qat_inter_sgl *)(mz_start +	curr_sgl_offset);
255cea6abe3SFiona Trahe 		int lb;
256a124830aSFiona Trahe 		array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
257a124830aSFiona Trahe 
258a124830aSFiona Trahe 		sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
259a124830aSFiona Trahe 		sgl->num_mapped_bufs = 0;
260a124830aSFiona Trahe 		sgl->resrvd = 0;
261a124830aSFiona Trahe 
262a124830aSFiona Trahe #if QAT_IM_BUFFER_DEBUG
263a124830aSFiona Trahe 		QAT_LOG(DEBUG, "  : phys addr of sgl[%i] in array_of_pointers"
264a124830aSFiona Trahe 			" = 0x%"PRIx64, i, array_of_pointers->pointer[i]);
265a124830aSFiona Trahe 		QAT_LOG(DEBUG, "  : virt address of sgl[%i] = %p", i, sgl);
266a124830aSFiona Trahe #endif
267cea6abe3SFiona Trahe 		for (lb = 0; lb < QAT_NUM_BUFS_IN_IM_SGL; lb++) {
268cea6abe3SFiona Trahe 			sgl->buffers[lb].addr =
269cea6abe3SFiona Trahe 			  mz_start_phys + offset_of_flat_buffs +
270cea6abe3SFiona Trahe 			  (((i * QAT_NUM_BUFS_IN_IM_SGL) + lb) * buff_size);
271cea6abe3SFiona Trahe 			sgl->buffers[lb].len = buff_size;
272cea6abe3SFiona Trahe 			sgl->buffers[lb].resrvd = 0;
273cea6abe3SFiona Trahe #if QAT_IM_BUFFER_DEBUG
274cea6abe3SFiona Trahe 			QAT_LOG(DEBUG,
275cea6abe3SFiona Trahe 			  "  : sgl->buffers[%d].addr = 0x%"PRIx64", len=%d",
276cea6abe3SFiona Trahe 			  lb, sgl->buffers[lb].addr, sgl->buffers[lb].len);
277cea6abe3SFiona Trahe #endif
278cea6abe3SFiona Trahe 		}
279a124830aSFiona Trahe 	}
280a124830aSFiona Trahe #if QAT_IM_BUFFER_DEBUG
281a124830aSFiona Trahe 	QAT_DP_HEXDUMP_LOG(DEBUG,  "IM buffer memzone start:",
282a124830aSFiona Trahe 			mz_start, offset_of_flat_buffs + 32);
283a124830aSFiona Trahe #endif
284a124830aSFiona Trahe 	return memzone;
285a124830aSFiona Trahe }
286a124830aSFiona Trahe 
287a795248dSFiona Trahe static struct rte_mempool *
288a795248dSFiona Trahe qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
2891e796b11STomasz Jozwiak 			   struct rte_compressdev_config *config,
290a795248dSFiona Trahe 			   uint32_t num_elements)
291a795248dSFiona Trahe {
292a795248dSFiona Trahe 	char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
293a795248dSFiona Trahe 	struct rte_mempool *mp;
294a795248dSFiona Trahe 
295a795248dSFiona Trahe 	snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
296a795248dSFiona Trahe 			"%s_xforms", comp_dev->qat_dev->name);
297a795248dSFiona Trahe 
298a795248dSFiona Trahe 	QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
299a795248dSFiona Trahe 	mp = rte_mempool_lookup(xform_pool_name);
300a795248dSFiona Trahe 
301a795248dSFiona Trahe 	if (mp != NULL) {
302a795248dSFiona Trahe 		QAT_LOG(DEBUG, "xformpool already created");
303a795248dSFiona Trahe 		if (mp->size != num_elements) {
304a795248dSFiona Trahe 			QAT_LOG(DEBUG, "xformpool wrong size - delete it");
305a795248dSFiona Trahe 			rte_mempool_free(mp);
306a795248dSFiona Trahe 			mp = NULL;
307a795248dSFiona Trahe 			comp_dev->xformpool = NULL;
308a795248dSFiona Trahe 		}
309a795248dSFiona Trahe 	}
310a795248dSFiona Trahe 
311a795248dSFiona Trahe 	if (mp == NULL)
312a795248dSFiona Trahe 		mp = rte_mempool_create(xform_pool_name,
313a795248dSFiona Trahe 				num_elements,
314a795248dSFiona Trahe 				qat_comp_xform_size(), 0, 0,
3151e796b11STomasz Jozwiak 				NULL, NULL, NULL, NULL, config->socket_id,
316a795248dSFiona Trahe 				0);
317a795248dSFiona Trahe 	if (mp == NULL) {
318a795248dSFiona Trahe 		QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
319a795248dSFiona Trahe 			xform_pool_name, num_elements, qat_comp_xform_size());
320a795248dSFiona Trahe 		return NULL;
321a795248dSFiona Trahe 	}
322a795248dSFiona Trahe 
323a795248dSFiona Trahe 	return mp;
324a795248dSFiona Trahe }
325a795248dSFiona Trahe 
326a795248dSFiona Trahe static void
32782822753SAdam Dybkowski qat_comp_stream_init(struct rte_mempool *mp __rte_unused, void *opaque,
32882822753SAdam Dybkowski 		     void *obj, unsigned int obj_idx)
32982822753SAdam Dybkowski {
33082822753SAdam Dybkowski 	struct stream_create_info *info = opaque;
33182822753SAdam Dybkowski 	struct qat_comp_stream *stream = obj;
33282822753SAdam Dybkowski 	char mz_name[RTE_MEMZONE_NAMESIZE];
33382822753SAdam Dybkowski 	const struct rte_memzone *memzone;
33482822753SAdam Dybkowski 	struct qat_inter_sgl *ram_banks_desc;
33582822753SAdam Dybkowski 
33682822753SAdam Dybkowski 	/* find a memzone for RAM banks */
33782822753SAdam Dybkowski 	snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "%s_%u_rambanks",
33882822753SAdam Dybkowski 		 info->comp_dev->qat_dev->name, obj_idx);
33982822753SAdam Dybkowski 	memzone = rte_memzone_lookup(mz_name);
34082822753SAdam Dybkowski 	if (memzone == NULL) {
34182822753SAdam Dybkowski 		/* allocate a memzone for compression state and RAM banks */
34282822753SAdam Dybkowski 		memzone = rte_memzone_reserve_aligned(mz_name,
34382822753SAdam Dybkowski 			QAT_STATE_REGISTERS_MAX_SIZE
34482822753SAdam Dybkowski 				+ sizeof(struct qat_inter_sgl)
34582822753SAdam Dybkowski 				+ QAT_INFLATE_CONTEXT_SIZE,
34682822753SAdam Dybkowski 			info->socket_id,
34782822753SAdam Dybkowski 			RTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN);
34882822753SAdam Dybkowski 		if (memzone == NULL) {
34982822753SAdam Dybkowski 			QAT_LOG(ERR,
35082822753SAdam Dybkowski 			    "Can't allocate RAM banks for device %s, object %u",
35182822753SAdam Dybkowski 				info->comp_dev->qat_dev->name, obj_idx);
35282822753SAdam Dybkowski 			info->error = -ENOMEM;
35382822753SAdam Dybkowski 			return;
35482822753SAdam Dybkowski 		}
35582822753SAdam Dybkowski 	}
35682822753SAdam Dybkowski 
35782822753SAdam Dybkowski 	/* prepare the buffer list descriptor for RAM banks */
35882822753SAdam Dybkowski 	ram_banks_desc = (struct qat_inter_sgl *)
35982822753SAdam Dybkowski 		(((uint8_t *) memzone->addr) + QAT_STATE_REGISTERS_MAX_SIZE);
36082822753SAdam Dybkowski 	ram_banks_desc->num_bufs = 1;
36182822753SAdam Dybkowski 	ram_banks_desc->buffers[0].len = QAT_INFLATE_CONTEXT_SIZE;
36282822753SAdam Dybkowski 	ram_banks_desc->buffers[0].addr = memzone->iova
36382822753SAdam Dybkowski 			+ QAT_STATE_REGISTERS_MAX_SIZE
36482822753SAdam Dybkowski 			+ sizeof(struct qat_inter_sgl);
36582822753SAdam Dybkowski 
36682822753SAdam Dybkowski 	memset(stream, 0, qat_comp_stream_size());
36782822753SAdam Dybkowski 	stream->memzone = memzone;
36882822753SAdam Dybkowski 	stream->state_registers_decomp = memzone->addr;
36982822753SAdam Dybkowski 	stream->state_registers_decomp_phys = memzone->iova;
37082822753SAdam Dybkowski 	stream->inflate_context = ((uint8_t *) memzone->addr)
37182822753SAdam Dybkowski 			+ QAT_STATE_REGISTERS_MAX_SIZE;
37282822753SAdam Dybkowski 	stream->inflate_context_phys = memzone->iova
37382822753SAdam Dybkowski 			+ QAT_STATE_REGISTERS_MAX_SIZE;
37482822753SAdam Dybkowski }
37582822753SAdam Dybkowski 
37682822753SAdam Dybkowski static void
37782822753SAdam Dybkowski qat_comp_stream_destroy(struct rte_mempool *mp __rte_unused,
37882822753SAdam Dybkowski 			void *opaque __rte_unused, void *obj,
37982822753SAdam Dybkowski 			unsigned obj_idx __rte_unused)
38082822753SAdam Dybkowski {
38182822753SAdam Dybkowski 	struct qat_comp_stream *stream = obj;
38282822753SAdam Dybkowski 
38382822753SAdam Dybkowski 	rte_memzone_free(stream->memzone);
38482822753SAdam Dybkowski }
38582822753SAdam Dybkowski 
38682822753SAdam Dybkowski static struct rte_mempool *
38782822753SAdam Dybkowski qat_comp_create_stream_pool(struct qat_comp_dev_private *comp_dev,
38882822753SAdam Dybkowski 			    int socket_id,
38982822753SAdam Dybkowski 			    uint32_t num_elements)
39082822753SAdam Dybkowski {
39182822753SAdam Dybkowski 	char stream_pool_name[RTE_MEMPOOL_NAMESIZE];
39282822753SAdam Dybkowski 	struct rte_mempool *mp;
39382822753SAdam Dybkowski 
39482822753SAdam Dybkowski 	snprintf(stream_pool_name, RTE_MEMPOOL_NAMESIZE,
39582822753SAdam Dybkowski 		 "%s_streams", comp_dev->qat_dev->name);
39682822753SAdam Dybkowski 
39782822753SAdam Dybkowski 	QAT_LOG(DEBUG, "streampool: %s", stream_pool_name);
39882822753SAdam Dybkowski 	mp = rte_mempool_lookup(stream_pool_name);
39982822753SAdam Dybkowski 
40082822753SAdam Dybkowski 	if (mp != NULL) {
40182822753SAdam Dybkowski 		QAT_LOG(DEBUG, "streampool already created");
40282822753SAdam Dybkowski 		if (mp->size != num_elements) {
40382822753SAdam Dybkowski 			QAT_LOG(DEBUG, "streampool wrong size - delete it");
40482822753SAdam Dybkowski 			rte_mempool_obj_iter(mp, qat_comp_stream_destroy, NULL);
40582822753SAdam Dybkowski 			rte_mempool_free(mp);
40682822753SAdam Dybkowski 			mp = NULL;
40782822753SAdam Dybkowski 			comp_dev->streampool = NULL;
40882822753SAdam Dybkowski 		}
40982822753SAdam Dybkowski 	}
41082822753SAdam Dybkowski 
41182822753SAdam Dybkowski 	if (mp == NULL) {
41282822753SAdam Dybkowski 		struct stream_create_info info = {
41382822753SAdam Dybkowski 			.comp_dev = comp_dev,
41482822753SAdam Dybkowski 			.socket_id = socket_id,
41582822753SAdam Dybkowski 			.error = 0
41682822753SAdam Dybkowski 		};
41782822753SAdam Dybkowski 		mp = rte_mempool_create(stream_pool_name,
41882822753SAdam Dybkowski 				num_elements,
41982822753SAdam Dybkowski 				qat_comp_stream_size(), 0, 0,
42082822753SAdam Dybkowski 				NULL, NULL, qat_comp_stream_init, &info,
42182822753SAdam Dybkowski 				socket_id, 0);
42282822753SAdam Dybkowski 		if (mp == NULL) {
42382822753SAdam Dybkowski 			QAT_LOG(ERR,
42482822753SAdam Dybkowski 			     "Err creating mempool %s w %d elements of size %d",
42582822753SAdam Dybkowski 			     stream_pool_name, num_elements,
42682822753SAdam Dybkowski 			     qat_comp_stream_size());
42782822753SAdam Dybkowski 		} else if (info.error) {
42882822753SAdam Dybkowski 			rte_mempool_obj_iter(mp, qat_comp_stream_destroy, NULL);
42982822753SAdam Dybkowski 			QAT_LOG(ERR,
43082822753SAdam Dybkowski 			     "Destoying mempool %s as at least one element failed initialisation",
43182822753SAdam Dybkowski 			     stream_pool_name);
43282822753SAdam Dybkowski 			rte_mempool_free(mp);
43382822753SAdam Dybkowski 			mp = NULL;
43482822753SAdam Dybkowski 		}
43582822753SAdam Dybkowski 	}
43682822753SAdam Dybkowski 
43782822753SAdam Dybkowski 	return mp;
43882822753SAdam Dybkowski }
43982822753SAdam Dybkowski 
44082822753SAdam Dybkowski static void
441a795248dSFiona Trahe _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
442a795248dSFiona Trahe {
443a124830aSFiona Trahe 	/* Free intermediate buffers */
444a124830aSFiona Trahe 	if (comp_dev->interm_buff_mz) {
445a124830aSFiona Trahe 		rte_memzone_free(comp_dev->interm_buff_mz);
446a124830aSFiona Trahe 		comp_dev->interm_buff_mz = NULL;
447a124830aSFiona Trahe 	}
448a124830aSFiona Trahe 
449a795248dSFiona Trahe 	/* Free private_xform pool */
450a795248dSFiona Trahe 	if (comp_dev->xformpool) {
451a795248dSFiona Trahe 		/* Free internal mempool for private xforms */
452a795248dSFiona Trahe 		rte_mempool_free(comp_dev->xformpool);
453a795248dSFiona Trahe 		comp_dev->xformpool = NULL;
454a795248dSFiona Trahe 	}
45582822753SAdam Dybkowski 
45682822753SAdam Dybkowski 	/* Free stream pool */
45782822753SAdam Dybkowski 	if (comp_dev->streampool) {
45882822753SAdam Dybkowski 		rte_mempool_obj_iter(comp_dev->streampool,
45982822753SAdam Dybkowski 				     qat_comp_stream_destroy, NULL);
46082822753SAdam Dybkowski 		rte_mempool_free(comp_dev->streampool);
46182822753SAdam Dybkowski 		comp_dev->streampool = NULL;
46282822753SAdam Dybkowski 	}
463a795248dSFiona Trahe }
464a795248dSFiona Trahe 
465edd37ac1SFiona Trahe static int
466a795248dSFiona Trahe qat_comp_dev_config(struct rte_compressdev *dev,
467a795248dSFiona Trahe 		struct rte_compressdev_config *config)
468a795248dSFiona Trahe {
469a795248dSFiona Trahe 	struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
470a795248dSFiona Trahe 	int ret = 0;
471a795248dSFiona Trahe 
472a124830aSFiona Trahe 	if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
473a124830aSFiona Trahe 		QAT_LOG(WARNING,
474a124830aSFiona Trahe 			"RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
475a124830aSFiona Trahe 			" QAT device can't be used for Dynamic Deflate. "
476a124830aSFiona Trahe 			"Did you really intend to do this?");
477a124830aSFiona Trahe 	} else {
478a124830aSFiona Trahe 		comp_dev->interm_buff_mz =
479a124830aSFiona Trahe 				qat_comp_setup_inter_buffers(comp_dev,
480a124830aSFiona Trahe 					RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
481a124830aSFiona Trahe 		if (comp_dev->interm_buff_mz == NULL) {
482a124830aSFiona Trahe 			ret = -ENOMEM;
483a124830aSFiona Trahe 			goto error_out;
484a124830aSFiona Trahe 		}
485a124830aSFiona Trahe 	}
486a124830aSFiona Trahe 
48782822753SAdam Dybkowski 	if (config->max_nb_priv_xforms) {
48882822753SAdam Dybkowski 		comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
48982822753SAdam Dybkowski 					    config, config->max_nb_priv_xforms);
490a795248dSFiona Trahe 		if (comp_dev->xformpool == NULL) {
491a795248dSFiona Trahe 			ret = -ENOMEM;
492a795248dSFiona Trahe 			goto error_out;
493a795248dSFiona Trahe 		}
49482822753SAdam Dybkowski 	} else
49582822753SAdam Dybkowski 		comp_dev->xformpool = NULL;
49682822753SAdam Dybkowski 
49782822753SAdam Dybkowski 	if (config->max_nb_streams) {
49882822753SAdam Dybkowski 		comp_dev->streampool = qat_comp_create_stream_pool(comp_dev,
49982822753SAdam Dybkowski 				     config->socket_id, config->max_nb_streams);
50082822753SAdam Dybkowski 		if (comp_dev->streampool == NULL) {
50182822753SAdam Dybkowski 			ret = -ENOMEM;
50282822753SAdam Dybkowski 			goto error_out;
50382822753SAdam Dybkowski 		}
50482822753SAdam Dybkowski 	} else
50582822753SAdam Dybkowski 		comp_dev->streampool = NULL;
50682822753SAdam Dybkowski 
507a795248dSFiona Trahe 	return 0;
508a795248dSFiona Trahe 
509a795248dSFiona Trahe error_out:
510a795248dSFiona Trahe 	_qat_comp_dev_config_clear(comp_dev);
511a795248dSFiona Trahe 	return ret;
512a795248dSFiona Trahe }
513a795248dSFiona Trahe 
514edd37ac1SFiona Trahe static int
515d8d380adSFiona Trahe qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
516d8d380adSFiona Trahe {
517d8d380adSFiona Trahe 	return 0;
518d8d380adSFiona Trahe }
519d8d380adSFiona Trahe 
520edd37ac1SFiona Trahe static void
521d8d380adSFiona Trahe qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
522d8d380adSFiona Trahe {
523d8d380adSFiona Trahe 
524d8d380adSFiona Trahe }
525a795248dSFiona Trahe 
526edd37ac1SFiona Trahe static int
527a795248dSFiona Trahe qat_comp_dev_close(struct rte_compressdev *dev)
528a795248dSFiona Trahe {
529a795248dSFiona Trahe 	int i;
530a795248dSFiona Trahe 	int ret = 0;
531a795248dSFiona Trahe 	struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
532a795248dSFiona Trahe 
533a795248dSFiona Trahe 	for (i = 0; i < dev->data->nb_queue_pairs; i++) {
534a795248dSFiona Trahe 		ret = qat_comp_qp_release(dev, i);
535a795248dSFiona Trahe 		if (ret < 0)
536a795248dSFiona Trahe 			return ret;
537a795248dSFiona Trahe 	}
538a795248dSFiona Trahe 
539a795248dSFiona Trahe 	_qat_comp_dev_config_clear(comp_dev);
540a795248dSFiona Trahe 
541a795248dSFiona Trahe 	return ret;
542a795248dSFiona Trahe }
54384aaaf8eSFiona Trahe 
54484aaaf8eSFiona Trahe 
545edd37ac1SFiona Trahe static void
54684aaaf8eSFiona Trahe qat_comp_dev_info_get(struct rte_compressdev *dev,
54784aaaf8eSFiona Trahe 			struct rte_compressdev_info *info)
54884aaaf8eSFiona Trahe {
54984aaaf8eSFiona Trahe 	struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
55084aaaf8eSFiona Trahe 	const struct qat_qp_hw_data *comp_hw_qps =
55184aaaf8eSFiona Trahe 		qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
55284aaaf8eSFiona Trahe 			      .qp_hw_data[QAT_SERVICE_COMPRESSION];
55384aaaf8eSFiona Trahe 
55484aaaf8eSFiona Trahe 	if (info != NULL) {
55584aaaf8eSFiona Trahe 		info->max_nb_queue_pairs =
55684aaaf8eSFiona Trahe 			qat_qps_per_service(comp_hw_qps,
55784aaaf8eSFiona Trahe 					    QAT_SERVICE_COMPRESSION);
55884aaaf8eSFiona Trahe 		info->feature_flags = dev->feature_flags;
55984aaaf8eSFiona Trahe 		info->capabilities = comp_dev->qat_dev_capabilities;
56084aaaf8eSFiona Trahe 	}
56184aaaf8eSFiona Trahe }
562a232ca8bSFiona Trahe 
563c0c90bc4SFiona Trahe static uint16_t
564a232ca8bSFiona Trahe qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
565a232ca8bSFiona Trahe 		uint16_t nb_ops)
566a232ca8bSFiona Trahe {
567a232ca8bSFiona Trahe 	return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
568a232ca8bSFiona Trahe }
569a232ca8bSFiona Trahe 
570c0c90bc4SFiona Trahe static uint16_t
571a232ca8bSFiona Trahe qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
572a232ca8bSFiona Trahe 			      uint16_t nb_ops)
573a232ca8bSFiona Trahe {
574a232ca8bSFiona Trahe 	return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
575a232ca8bSFiona Trahe }
576edd37ac1SFiona Trahe 
5772519de89SFiona Trahe static uint16_t
5782519de89SFiona Trahe qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused,
5792519de89SFiona Trahe 				    struct rte_comp_op **ops __rte_unused,
5802519de89SFiona Trahe 				    uint16_t nb_ops __rte_unused)
5812519de89SFiona Trahe {
5822519de89SFiona Trahe 	QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !");
5832519de89SFiona Trahe 	return 0;
5842519de89SFiona Trahe }
5852519de89SFiona Trahe 
5862519de89SFiona Trahe static struct rte_compressdev_ops compress_qat_dummy_ops = {
5872519de89SFiona Trahe 
5882519de89SFiona Trahe 	/* Device related operations */
5892519de89SFiona Trahe 	.dev_configure		= NULL,
5902519de89SFiona Trahe 	.dev_start		= NULL,
5912519de89SFiona Trahe 	.dev_stop		= qat_comp_dev_stop,
5922519de89SFiona Trahe 	.dev_close		= qat_comp_dev_close,
5932519de89SFiona Trahe 	.dev_infos_get		= NULL,
5942519de89SFiona Trahe 
5952519de89SFiona Trahe 	.stats_get		= NULL,
5962519de89SFiona Trahe 	.stats_reset		= qat_comp_stats_reset,
5972519de89SFiona Trahe 	.queue_pair_setup	= NULL,
5982519de89SFiona Trahe 	.queue_pair_release	= qat_comp_qp_release,
5992519de89SFiona Trahe 
6002519de89SFiona Trahe 	/* Compression related operations */
6012519de89SFiona Trahe 	.private_xform_create	= NULL,
6022519de89SFiona Trahe 	.private_xform_free	= qat_comp_private_xform_free
6032519de89SFiona Trahe };
6042519de89SFiona Trahe 
6052519de89SFiona Trahe static uint16_t
6062519de89SFiona Trahe qat_comp_pmd_dequeue_frst_op_burst(void *qp, struct rte_comp_op **ops,
6072519de89SFiona Trahe 				   uint16_t nb_ops)
6082519de89SFiona Trahe {
6092519de89SFiona Trahe 	uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
6102519de89SFiona Trahe 	struct qat_qp *tmp_qp = (struct qat_qp *)qp;
6112519de89SFiona Trahe 
6122519de89SFiona Trahe 	if (ret) {
6132519de89SFiona Trahe 		if ((*ops)->debug_status ==
6142519de89SFiona Trahe 				(uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) {
6152519de89SFiona Trahe 			tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst =
6162519de89SFiona Trahe 					qat_comp_pmd_enq_deq_dummy_op_burst;
6172519de89SFiona Trahe 			tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
6182519de89SFiona Trahe 					qat_comp_pmd_enq_deq_dummy_op_burst;
6192519de89SFiona Trahe 
6202519de89SFiona Trahe 			tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
6212519de89SFiona Trahe 					&compress_qat_dummy_ops;
6222519de89SFiona Trahe 			QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
6232519de89SFiona Trahe 
6242519de89SFiona Trahe 		} else {
6252519de89SFiona Trahe 			tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
6262519de89SFiona Trahe 					qat_comp_pmd_dequeue_op_burst;
6272519de89SFiona Trahe 		}
6282519de89SFiona Trahe 	}
6292519de89SFiona Trahe 	return ret;
6302519de89SFiona Trahe }
631edd37ac1SFiona Trahe 
632c0c90bc4SFiona Trahe static struct rte_compressdev_ops compress_qat_ops = {
633edd37ac1SFiona Trahe 
634edd37ac1SFiona Trahe 	/* Device related operations */
635edd37ac1SFiona Trahe 	.dev_configure		= qat_comp_dev_config,
636edd37ac1SFiona Trahe 	.dev_start		= qat_comp_dev_start,
637edd37ac1SFiona Trahe 	.dev_stop		= qat_comp_dev_stop,
638edd37ac1SFiona Trahe 	.dev_close		= qat_comp_dev_close,
639edd37ac1SFiona Trahe 	.dev_infos_get		= qat_comp_dev_info_get,
640edd37ac1SFiona Trahe 
641edd37ac1SFiona Trahe 	.stats_get		= qat_comp_stats_get,
642edd37ac1SFiona Trahe 	.stats_reset		= qat_comp_stats_reset,
643edd37ac1SFiona Trahe 	.queue_pair_setup	= qat_comp_qp_setup,
644edd37ac1SFiona Trahe 	.queue_pair_release	= qat_comp_qp_release,
645edd37ac1SFiona Trahe 
646edd37ac1SFiona Trahe 	/* Compression related operations */
647edd37ac1SFiona Trahe 	.private_xform_create	= qat_comp_private_xform_create,
64882822753SAdam Dybkowski 	.private_xform_free	= qat_comp_private_xform_free,
64982822753SAdam Dybkowski 	.stream_create		= qat_comp_stream_create,
65082822753SAdam Dybkowski 	.stream_free		= qat_comp_stream_free
651edd37ac1SFiona Trahe };
652c0c90bc4SFiona Trahe 
653df8cca46SFiona Trahe /* An rte_driver is needed in the registration of the device with compressdev.
654df8cca46SFiona Trahe  * The actual qat pci's rte_driver can't be used as its name represents
655df8cca46SFiona Trahe  * the whole pci device with all services. Think of this as a holder for a name
656df8cca46SFiona Trahe  * for the compression part of the pci device.
657df8cca46SFiona Trahe  */
658df8cca46SFiona Trahe static const char qat_comp_drv_name[] = RTE_STR(COMPRESSDEV_NAME_QAT_PMD);
659df8cca46SFiona Trahe static const struct rte_driver compdev_qat_driver = {
660df8cca46SFiona Trahe 	.name = qat_comp_drv_name,
661df8cca46SFiona Trahe 	.alias = qat_comp_drv_name
662df8cca46SFiona Trahe };
663c0c90bc4SFiona Trahe int
66447c3f7a4SArek Kusztal qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,
66547c3f7a4SArek Kusztal 		struct qat_dev_cmd_param *qat_dev_cmd_param)
666c0c90bc4SFiona Trahe {
66747c3f7a4SArek Kusztal 	int i = 0;
668a124830aSFiona Trahe 	if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
669*9cd9d3e7SAdam Dybkowski 		QAT_LOG(ERR, "Compression PMD not supported on QAT P5xxx");
670a124830aSFiona Trahe 		return 0;
671a124830aSFiona Trahe 	}
672c0c90bc4SFiona Trahe 
673c0c90bc4SFiona Trahe 	struct rte_compressdev_pmd_init_params init_params = {
674c0c90bc4SFiona Trahe 		.name = "",
675c0c90bc4SFiona Trahe 		.socket_id = qat_pci_dev->pci_dev->device.numa_node,
676c0c90bc4SFiona Trahe 	};
677c0c90bc4SFiona Trahe 	char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
678c0c90bc4SFiona Trahe 	struct rte_compressdev *compressdev;
679c0c90bc4SFiona Trahe 	struct qat_comp_dev_private *comp_dev;
680c0c90bc4SFiona Trahe 
681c0c90bc4SFiona Trahe 	snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
682c0c90bc4SFiona Trahe 			qat_pci_dev->name, "comp");
683c0c90bc4SFiona Trahe 	QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
684c0c90bc4SFiona Trahe 
685df8cca46SFiona Trahe 	/* Populate subset device to use in compressdev device creation */
686df8cca46SFiona Trahe 	qat_pci_dev->comp_rte_dev.driver = &compdev_qat_driver;
687df8cca46SFiona Trahe 	qat_pci_dev->comp_rte_dev.numa_node =
688df8cca46SFiona Trahe 					qat_pci_dev->pci_dev->device.numa_node;
689df8cca46SFiona Trahe 	qat_pci_dev->comp_rte_dev.devargs = NULL;
690df8cca46SFiona Trahe 
691c0c90bc4SFiona Trahe 	compressdev = rte_compressdev_pmd_create(name,
692df8cca46SFiona Trahe 			&(qat_pci_dev->comp_rte_dev),
693c0c90bc4SFiona Trahe 			sizeof(struct qat_comp_dev_private),
694c0c90bc4SFiona Trahe 			&init_params);
695c0c90bc4SFiona Trahe 
696c0c90bc4SFiona Trahe 	if (compressdev == NULL)
697c0c90bc4SFiona Trahe 		return -ENODEV;
698c0c90bc4SFiona Trahe 
699c0c90bc4SFiona Trahe 	compressdev->dev_ops = &compress_qat_ops;
700c0c90bc4SFiona Trahe 
701c0c90bc4SFiona Trahe 	compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
7022519de89SFiona Trahe 	compressdev->dequeue_burst = qat_comp_pmd_dequeue_frst_op_burst;
703c0c90bc4SFiona Trahe 
704c0c90bc4SFiona Trahe 	compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
705c0c90bc4SFiona Trahe 
706c0c90bc4SFiona Trahe 	comp_dev = compressdev->data->dev_private;
707c0c90bc4SFiona Trahe 	comp_dev->qat_dev = qat_pci_dev;
708c0c90bc4SFiona Trahe 	comp_dev->compressdev = compressdev;
709c0c90bc4SFiona Trahe 	qat_pci_dev->comp_dev = comp_dev;
710c0c90bc4SFiona Trahe 
711c0c90bc4SFiona Trahe 	switch (qat_pci_dev->qat_dev_gen) {
712c0c90bc4SFiona Trahe 	case QAT_GEN1:
713c0c90bc4SFiona Trahe 	case QAT_GEN2:
7141f5e4053SFiona Trahe 	case QAT_GEN3:
715c0c90bc4SFiona Trahe 		comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
716c0c90bc4SFiona Trahe 		break;
717c0c90bc4SFiona Trahe 	default:
718c0c90bc4SFiona Trahe 		comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
719c0c90bc4SFiona Trahe 		QAT_LOG(DEBUG,
720c0c90bc4SFiona Trahe 			"QAT gen %d capabilities unknown, default to GEN1",
721c0c90bc4SFiona Trahe 					qat_pci_dev->qat_dev_gen);
722c0c90bc4SFiona Trahe 		break;
723c0c90bc4SFiona Trahe 	}
724c0c90bc4SFiona Trahe 
72547c3f7a4SArek Kusztal 	while (1) {
72647c3f7a4SArek Kusztal 		if (qat_dev_cmd_param[i].name == NULL)
72747c3f7a4SArek Kusztal 			break;
72847c3f7a4SArek Kusztal 		if (!strcmp(qat_dev_cmd_param[i].name, COMP_ENQ_THRESHOLD_NAME))
72947c3f7a4SArek Kusztal 			comp_dev->min_enq_burst_threshold =
73047c3f7a4SArek Kusztal 					qat_dev_cmd_param[i].val;
73147c3f7a4SArek Kusztal 		i++;
73247c3f7a4SArek Kusztal 	}
73347c3f7a4SArek Kusztal 
734c0c90bc4SFiona Trahe 	QAT_LOG(DEBUG,
735c0c90bc4SFiona Trahe 		    "Created QAT COMP device %s as compressdev instance %d",
736c0c90bc4SFiona Trahe 			name, compressdev->data->dev_id);
737c0c90bc4SFiona Trahe 	return 0;
738c0c90bc4SFiona Trahe }
739c0c90bc4SFiona Trahe 
740c0c90bc4SFiona Trahe int
741c0c90bc4SFiona Trahe qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
742c0c90bc4SFiona Trahe {
743c0c90bc4SFiona Trahe 	struct qat_comp_dev_private *comp_dev;
744c0c90bc4SFiona Trahe 
745c0c90bc4SFiona Trahe 	if (qat_pci_dev == NULL)
746c0c90bc4SFiona Trahe 		return -ENODEV;
747c0c90bc4SFiona Trahe 
748c0c90bc4SFiona Trahe 	comp_dev = qat_pci_dev->comp_dev;
749c0c90bc4SFiona Trahe 	if (comp_dev == NULL)
750c0c90bc4SFiona Trahe 		return 0;
751c0c90bc4SFiona Trahe 
752c0c90bc4SFiona Trahe 	/* clean up any resources used by the device */
753c0c90bc4SFiona Trahe 	qat_comp_dev_close(comp_dev->compressdev);
754c0c90bc4SFiona Trahe 
755c0c90bc4SFiona Trahe 	rte_compressdev_pmd_destroy(comp_dev->compressdev);
756c0c90bc4SFiona Trahe 	qat_pci_dev->comp_dev = NULL;
757c0c90bc4SFiona Trahe 
758c0c90bc4SFiona Trahe 	return 0;
759c0c90bc4SFiona Trahe }
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