1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2021 Intel Corporation 3 */ 4 5 #include "qat_comp.h" 6 #include "qat_comp_pmd.h" 7 #include "qat_comp_pmd_gens.h" 8 #include "icp_qat_hw_gen4_comp.h" 9 #include "icp_qat_hw_gen4_comp_defs.h" 10 11 #define QAT_NUM_INTERM_BUFS_GEN4 0 12 13 static const struct rte_compressdev_capabilities 14 qat_gen4_comp_capabilities[] = { 15 {/* COMPRESSION - deflate */ 16 .algo = RTE_COMP_ALGO_DEFLATE, 17 .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM | 18 RTE_COMP_FF_CRC32_CHECKSUM | 19 RTE_COMP_FF_ADLER32_CHECKSUM | 20 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 21 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 22 RTE_COMP_FF_HUFFMAN_FIXED | 23 RTE_COMP_FF_HUFFMAN_DYNAMIC | 24 RTE_COMP_FF_OOP_SGL_IN_SGL_OUT | 25 RTE_COMP_FF_OOP_SGL_IN_LB_OUT | 26 RTE_COMP_FF_OOP_LB_IN_SGL_OUT, 27 .window_size = {.min = 15, .max = 15, .increment = 0} }, 28 RTE_COMP_END_OF_CAPABILITIES_LIST() }; 29 30 int 31 qat_comp_dev_config_gen4(struct rte_compressdev *dev, 32 struct rte_compressdev_config *config) 33 { 34 /* QAT GEN4 doesn't need preallocated intermediate buffers */ 35 36 return qat_comp_dev_config(dev, config); 37 } 38 39 static struct rte_compressdev_ops qat_comp_ops_gen4 = { 40 41 /* Device related operations */ 42 .dev_configure = qat_comp_dev_config_gen4, 43 .dev_start = qat_comp_dev_start, 44 .dev_stop = qat_comp_dev_stop, 45 .dev_close = qat_comp_dev_close, 46 .dev_infos_get = qat_comp_dev_info_get, 47 48 .stats_get = qat_comp_stats_get, 49 .stats_reset = qat_comp_stats_reset, 50 .queue_pair_setup = qat_comp_qp_setup, 51 .queue_pair_release = qat_comp_qp_release, 52 53 /* Compression related operations */ 54 .private_xform_create = qat_comp_private_xform_create, 55 .private_xform_free = qat_comp_private_xform_free, 56 .stream_create = qat_comp_stream_create, 57 .stream_free = qat_comp_stream_free 58 }; 59 60 static struct qat_comp_capabilities_info 61 qat_comp_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused) 62 { 63 struct qat_comp_capabilities_info capa_info = { 64 .data = qat_gen4_comp_capabilities, 65 .size = sizeof(qat_gen4_comp_capabilities) 66 }; 67 return capa_info; 68 } 69 70 uint16_t 71 qat_comp_get_ram_bank_flags_gen4(void) 72 { 73 return 0; 74 } 75 76 int 77 qat_comp_set_slice_cfg_word_gen4(struct qat_comp_xform *qat_xform, 78 const struct rte_comp_xform *xform, 79 enum rte_comp_op_type op_type, uint32_t *comp_slice_cfg_word) 80 { 81 if (qat_xform->qat_comp_request_type == 82 QAT_COMP_REQUEST_FIXED_COMP_STATELESS || 83 qat_xform->qat_comp_request_type == 84 QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) { 85 /* Compression */ 86 struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr; 87 struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr; 88 89 memset(&hw_comp_upper_csr, 0, sizeof(hw_comp_upper_csr)); 90 memset(&hw_comp_lower_csr, 0, sizeof(hw_comp_lower_csr)); 91 92 hw_comp_lower_csr.lllbd = 93 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED; 94 95 if (xform->compress.algo == RTE_COMP_ALGO_DEFLATE) { 96 hw_comp_lower_csr.skip_ctrl = 97 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL; 98 99 if (qat_xform->qat_comp_request_type == 100 QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) { 101 hw_comp_lower_csr.algo = 102 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77; 103 hw_comp_lower_csr.lllbd = 104 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED; 105 } else { 106 hw_comp_lower_csr.algo = 107 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE; 108 hw_comp_upper_csr.scb_ctrl = 109 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE; 110 } 111 112 if (op_type == RTE_COMP_OP_STATEFUL) { 113 hw_comp_upper_csr.som_ctrl = 114 ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE; 115 } 116 } else { 117 QAT_LOG(ERR, "Compression algorithm not supported"); 118 return -EINVAL; 119 } 120 121 switch (xform->compress.level) { 122 case 1: 123 case 2: 124 case 3: 125 case 4: 126 case 5: 127 hw_comp_lower_csr.sd = 128 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1; 129 hw_comp_lower_csr.hash_col = 130 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW; 131 break; 132 case 6: 133 case 7: 134 case 8: 135 case RTE_COMP_LEVEL_PMD_DEFAULT: 136 hw_comp_lower_csr.sd = 137 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6; 138 break; 139 case 9: 140 case 10: 141 case 11: 142 case 12: 143 hw_comp_lower_csr.sd = 144 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9; 145 break; 146 default: 147 QAT_LOG(ERR, "Compression level not supported"); 148 return -EINVAL; 149 } 150 151 hw_comp_lower_csr.abd = ICP_QAT_HW_COMP_20_ABD_ABD_DISABLED; 152 hw_comp_lower_csr.hash_update = 153 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW; 154 hw_comp_lower_csr.edmm = 155 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED; 156 157 hw_comp_upper_csr.nice = 158 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL; 159 hw_comp_upper_csr.lazy = 160 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL; 161 162 comp_slice_cfg_word[0] = 163 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER( 164 hw_comp_lower_csr); 165 comp_slice_cfg_word[1] = 166 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER( 167 hw_comp_upper_csr); 168 } else { 169 /* Decompression */ 170 struct icp_qat_hw_decomp_20_config_csr_lower 171 hw_decomp_lower_csr; 172 173 memset(&hw_decomp_lower_csr, 0, sizeof(hw_decomp_lower_csr)); 174 175 if (xform->compress.algo == RTE_COMP_ALGO_DEFLATE) 176 hw_decomp_lower_csr.algo = 177 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE; 178 else { 179 QAT_LOG(ERR, "Compression algorithm not supported"); 180 return -EINVAL; 181 } 182 183 comp_slice_cfg_word[0] = 184 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER( 185 hw_decomp_lower_csr); 186 comp_slice_cfg_word[1] = 0; 187 } 188 189 return 0; 190 } 191 192 unsigned int 193 qat_comp_get_num_im_bufs_required_gen4(void) 194 { 195 return QAT_NUM_INTERM_BUFS_GEN4; 196 } 197 198 199 RTE_INIT(qat_comp_pmd_gen4_init) 200 { 201 qat_comp_gen_dev_ops[QAT_VQAT].compressdev_ops = 202 qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops = 203 &qat_comp_ops_gen4; 204 qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_capabilities = 205 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities = 206 qat_comp_cap_get_gen4; 207 qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_num_im_bufs_required = 208 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required = 209 qat_comp_get_num_im_bufs_required_gen4; 210 qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_ram_bank_flags = 211 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags = 212 qat_comp_get_ram_bank_flags_gen4; 213 qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_set_slice_cfg_word = 214 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word = 215 qat_comp_set_slice_cfg_word_gen4; 216 qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_feature_flags = 217 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags = 218 qat_comp_get_features_gen1; 219 } 220