1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2021 Intel Corporation 3 */ 4 5 #include <rte_compressdev.h> 6 #include <rte_compressdev_pmd.h> 7 8 #include "qat_comp_pmd.h" 9 #include "qat_comp.h" 10 #include "qat_comp_pmd_gens.h" 11 12 #define QAT_NUM_INTERM_BUFS_GEN1 12 13 14 const struct rte_compressdev_capabilities qat_gen1_comp_capabilities[] = { 15 {/* COMPRESSION - deflate */ 16 .algo = RTE_COMP_ALGO_DEFLATE, 17 .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM | 18 RTE_COMP_FF_CRC32_CHECKSUM | 19 RTE_COMP_FF_ADLER32_CHECKSUM | 20 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 21 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 22 RTE_COMP_FF_HUFFMAN_FIXED | 23 RTE_COMP_FF_HUFFMAN_DYNAMIC | 24 RTE_COMP_FF_OOP_SGL_IN_SGL_OUT | 25 RTE_COMP_FF_OOP_SGL_IN_LB_OUT | 26 RTE_COMP_FF_OOP_LB_IN_SGL_OUT | 27 RTE_COMP_FF_STATEFUL_DECOMPRESSION, 28 .window_size = {.min = 15, .max = 15, .increment = 0} }, 29 RTE_COMP_END_OF_CAPABILITIES_LIST() }; 30 31 static int 32 qat_comp_dev_config_gen1(struct rte_compressdev *dev, 33 struct rte_compressdev_config *config) 34 { 35 struct qat_comp_dev_private *comp_dev = dev->data->dev_private; 36 37 if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) { 38 QAT_LOG(WARNING, 39 "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so" 40 " QAT device can't be used for Dynamic Deflate."); 41 } else { 42 comp_dev->interm_buff_mz = 43 qat_comp_setup_inter_buffers(comp_dev, 44 RTE_PMD_QAT_COMP_IM_BUFFER_SIZE); 45 if (comp_dev->interm_buff_mz == NULL) 46 return -ENOMEM; 47 } 48 49 return qat_comp_dev_config(dev, config); 50 } 51 52 struct rte_compressdev_ops qat_comp_ops_gen1 = { 53 54 /* Device related operations */ 55 .dev_configure = qat_comp_dev_config_gen1, 56 .dev_start = qat_comp_dev_start, 57 .dev_stop = qat_comp_dev_stop, 58 .dev_close = qat_comp_dev_close, 59 .dev_infos_get = qat_comp_dev_info_get, 60 61 .stats_get = qat_comp_stats_get, 62 .stats_reset = qat_comp_stats_reset, 63 .queue_pair_setup = qat_comp_qp_setup, 64 .queue_pair_release = qat_comp_qp_release, 65 66 /* Compression related operations */ 67 .private_xform_create = qat_comp_private_xform_create, 68 .private_xform_free = qat_comp_private_xform_free, 69 .stream_create = qat_comp_stream_create, 70 .stream_free = qat_comp_stream_free 71 }; 72 73 struct qat_comp_capabilities_info 74 qat_comp_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused) 75 { 76 struct qat_comp_capabilities_info capa_info = { 77 .data = qat_gen1_comp_capabilities, 78 .size = sizeof(qat_gen1_comp_capabilities) 79 }; 80 return capa_info; 81 } 82 83 uint16_t 84 qat_comp_get_ram_bank_flags_gen1(void) 85 { 86 /* Enable A, B, C, D, and E (CAMs). */ 87 return ICP_QAT_FW_COMP_RAM_FLAGS_BUILD( 88 ICP_QAT_FW_COMP_BANK_DISABLED, /* Bank I */ 89 ICP_QAT_FW_COMP_BANK_DISABLED, /* Bank H */ 90 ICP_QAT_FW_COMP_BANK_DISABLED, /* Bank G */ 91 ICP_QAT_FW_COMP_BANK_DISABLED, /* Bank F */ 92 ICP_QAT_FW_COMP_BANK_ENABLED, /* Bank E */ 93 ICP_QAT_FW_COMP_BANK_ENABLED, /* Bank D */ 94 ICP_QAT_FW_COMP_BANK_ENABLED, /* Bank C */ 95 ICP_QAT_FW_COMP_BANK_ENABLED, /* Bank B */ 96 ICP_QAT_FW_COMP_BANK_ENABLED); /* Bank A */ 97 } 98 99 int 100 qat_comp_set_slice_cfg_word_gen1(struct qat_comp_xform *qat_xform, 101 const struct rte_comp_xform *xform, 102 __rte_unused enum rte_comp_op_type op_type, 103 uint32_t *comp_slice_cfg_word) 104 { 105 unsigned int algo, comp_level, direction; 106 107 if (xform->compress.algo == RTE_COMP_ALGO_DEFLATE) 108 algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE; 109 else { 110 QAT_LOG(ERR, "compression algorithm not supported"); 111 return -EINVAL; 112 } 113 114 if (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) { 115 direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS; 116 comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8; 117 } else { 118 direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS; 119 120 if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT) 121 comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8; 122 else if (xform->compress.level == 1) 123 comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1; 124 else if (xform->compress.level == 2) 125 comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4; 126 else if (xform->compress.level == 3) 127 comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8; 128 else if (xform->compress.level >= 4 && 129 xform->compress.level <= 9) 130 comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16; 131 else { 132 QAT_LOG(ERR, "compression level not supported"); 133 return -EINVAL; 134 } 135 } 136 137 comp_slice_cfg_word[0] = 138 ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( 139 direction, 140 /* In CPM 1.6 only valid mode ! */ 141 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, 142 algo, 143 /* Translate level to depth */ 144 comp_level, 145 ICP_QAT_HW_COMPRESSION_FILE_TYPE_0); 146 147 return 0; 148 } 149 150 static unsigned int 151 qat_comp_get_num_im_bufs_required_gen1(void) 152 { 153 return QAT_NUM_INTERM_BUFS_GEN1; 154 } 155 156 uint64_t 157 qat_comp_get_features_gen1(void) 158 { 159 return RTE_COMPDEV_FF_HW_ACCELERATED; 160 } 161 162 RTE_INIT(qat_comp_pmd_gen1_init) 163 { 164 qat_comp_gen_dev_ops[QAT_GEN1].compressdev_ops = 165 &qat_comp_ops_gen1; 166 qat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_capabilities = 167 qat_comp_cap_get_gen1; 168 qat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_num_im_bufs_required = 169 qat_comp_get_num_im_bufs_required_gen1; 170 qat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_ram_bank_flags = 171 qat_comp_get_ram_bank_flags_gen1; 172 qat_comp_gen_dev_ops[QAT_GEN1].qat_comp_set_slice_cfg_word = 173 qat_comp_set_slice_cfg_word_gen1; 174 qat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_feature_flags = 175 qat_comp_get_features_gen1; 176 } 177