1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Cavium, Inc 3 */ 4 5 #ifndef _RTE_OCTEONTX_ZIP_VF_H_ 6 #define _RTE_OCTEONTX_ZIP_VF_H_ 7 8 #include <unistd.h> 9 10 #include <rte_bus_pci.h> 11 #include <rte_comp.h> 12 #include <rte_compressdev.h> 13 #include <rte_compressdev_pmd.h> 14 #include <rte_malloc.h> 15 #include <rte_memory.h> 16 #include <rte_spinlock.h> 17 18 #include <zip_regs.h> 19 20 int octtx_zip_logtype_driver; 21 22 /* ZIP VF Control/Status registers (CSRs): */ 23 /* VF_BAR0: */ 24 #define ZIP_VQ_ENA (0x10) 25 #define ZIP_VQ_SBUF_ADDR (0x20) 26 #define ZIP_VF_PF_MBOXX(x) (0x400 | (x)<<3) 27 #define ZIP_VQ_DOORBELL (0x1000) 28 29 /**< Vendor ID */ 30 #define PCI_VENDOR_ID_CAVIUM 0x177D 31 /**< PCI device id of ZIP VF */ 32 #define PCI_DEVICE_ID_OCTEONTX_ZIPVF 0xA037 33 34 /* maxmum number of zip vf devices */ 35 #define ZIP_MAX_VFS 8 36 37 /* max size of one chunk */ 38 #define ZIP_MAX_CHUNK_SIZE 8192 39 40 /* each instruction is fixed 128 bytes */ 41 #define ZIP_CMD_SIZE 128 42 43 #define ZIP_CMD_SIZE_WORDS (ZIP_CMD_SIZE >> 3) /* 16 64_bit words */ 44 45 /* size of next chunk buffer pointer */ 46 #define ZIP_MAX_NCBP_SIZE 8 47 48 /* size of instruction queue in units of instruction size */ 49 #define ZIP_MAX_NUM_CMDS ((ZIP_MAX_CHUNK_SIZE - ZIP_MAX_NCBP_SIZE) / \ 50 ZIP_CMD_SIZE) /* 63 */ 51 52 /* size of instruct queue in bytes */ 53 #define ZIP_MAX_CMDQ_SIZE ((ZIP_MAX_NUM_CMDS * ZIP_CMD_SIZE) + \ 54 ZIP_MAX_NCBP_SIZE)/* ~8072ull */ 55 56 #define ZIP_BUF_SIZE 256 57 58 #define ZIP_SGPTR_ALIGN 16 59 #define ZIP_CMDQ_ALIGN 128 60 #define MAX_SG_LEN ((ZIP_BUF_SIZE - ZIP_SGPTR_ALIGN) / sizeof(void *)) 61 62 /**< ZIP PMD specified queue pairs */ 63 #define ZIP_MAX_VF_QUEUE 1 64 65 #define ZIP_ALIGN_ROUNDUP(x, _align) \ 66 ((_align) * (((x) + (_align) - 1) / (_align))) 67 68 /**< ZIP PMD device name */ 69 #define COMPRESSDEV_NAME_ZIP_PMD compress_octeonx 70 71 #define ZIP_PMD_LOG(level, fmt, args...) \ 72 rte_log(RTE_LOG_ ## level, \ 73 octtx_zip_logtype_driver, "%s(): "fmt "\n", \ 74 __func__, ##args) 75 76 #define ZIP_PMD_INFO(fmt, args...) \ 77 ZIP_PMD_LOG(INFO, fmt, ## args) 78 #define ZIP_PMD_ERR(fmt, args...) \ 79 ZIP_PMD_LOG(ERR, fmt, ## args) 80 81 /* resources required to process stream */ 82 enum { 83 RES_BUF = 0, 84 CMD_BUF, 85 HASH_CTX_BUF, 86 DECOMP_CTX_BUF, 87 IN_DATA_BUF, 88 OUT_DATA_BUF, 89 HISTORY_DATA_BUF, 90 MAX_BUFS_PER_STREAM 91 } NUM_BUFS_PER_STREAM; 92 93 94 struct zipvf_qp; 95 96 97 /** 98 * ZIP instruction Queue 99 */ 100 struct zipvf_cmdq { 101 rte_spinlock_t qlock; 102 /* queue lock */ 103 uint64_t *sw_head; 104 /* pointer to start of 8-byte word length queue-head */ 105 uint8_t *va; 106 /* pointer to instruction queue virtual address */ 107 rte_iova_t iova; 108 /* iova addr of cmdq head*/ 109 }; 110 111 /** 112 * ZIP device queue structure 113 */ 114 struct zipvf_qp { 115 struct zipvf_cmdq cmdq; 116 /* Hardware instruction queue structure */ 117 struct rte_ring *processed_pkts; 118 /* Ring for placing processed packets */ 119 struct rte_compressdev_stats qp_stats; 120 /* Queue pair statistics */ 121 uint16_t id; 122 /* Queue Pair Identifier */ 123 const char *name; 124 /* Unique Queue Pair Name */ 125 struct zip_vf *vf; 126 /* pointer to device, queue belongs to */ 127 } __rte_cache_aligned; 128 129 /** 130 * ZIP VF device structure. 131 */ 132 struct zip_vf { 133 int vfid; 134 /* vf index */ 135 struct rte_pci_device *pdev; 136 /* pci device */ 137 void *vbar0; 138 /* CSR base address for underlying BAR0 VF.*/ 139 uint64_t dom_sdom; 140 /* Storing mbox domain and subdomain id for app rerun*/ 141 uint32_t max_nb_queue_pairs; 142 /* pointer to device qps */ 143 struct rte_mempool *zip_mp; 144 /* pointer to pools */ 145 } __rte_cache_aligned; 146 147 int 148 zipvf_create(struct rte_compressdev *compressdev); 149 150 int 151 zipvf_destroy(struct rte_compressdev *compressdev); 152 153 int 154 zipvf_q_init(struct zipvf_qp *qp); 155 156 int 157 zipvf_q_term(struct zipvf_qp *qp); 158 159 160 uint64_t 161 zip_reg_read64(uint8_t *hw_addr, uint64_t offset); 162 163 void 164 zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val); 165 166 #endif /* _RTE_ZIP_VF_H_ */ 167