xref: /dpdk/drivers/compress/octeontx/otx_zip.h (revision 25d11a86c56d50947af33d0b79ede622809bd8b9)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018 Cavium, Inc
3  */
4 
5 #ifndef _RTE_OCTEONTX_ZIP_VF_H_
6 #define _RTE_OCTEONTX_ZIP_VF_H_
7 
8 #include <unistd.h>
9 
10 #include <rte_bus_pci.h>
11 #include <rte_comp.h>
12 #include <rte_compressdev.h>
13 #include <rte_compressdev_pmd.h>
14 #include <rte_malloc.h>
15 #include <rte_memory.h>
16 #include <rte_spinlock.h>
17 
18 #include <zip_regs.h>
19 
20 int octtx_zip_logtype_driver;
21 
22 /* ZIP VF Control/Status registers (CSRs): */
23 /* VF_BAR0: */
24 #define ZIP_VQ_ENA              (0x10)
25 #define ZIP_VQ_SBUF_ADDR        (0x20)
26 #define ZIP_VF_PF_MBOXX(x)      (0x400 | (x)<<3)
27 #define ZIP_VQ_DOORBELL         (0x1000)
28 
29 /**< Vendor ID */
30 #define PCI_VENDOR_ID_CAVIUM	0x177D
31 /**< PCI device id of ZIP VF */
32 #define PCI_DEVICE_ID_OCTEONTX_ZIPVF	0xA037
33 
34 /* maxmum number of zip vf devices */
35 #define ZIP_MAX_VFS 8
36 
37 /* max size of one chunk */
38 #define ZIP_MAX_CHUNK_SIZE	8192
39 
40 /* each instruction is fixed 128 bytes */
41 #define ZIP_CMD_SIZE		128
42 
43 #define ZIP_CMD_SIZE_WORDS	(ZIP_CMD_SIZE >> 3) /* 16 64_bit words */
44 
45 /* size of next chunk buffer pointer */
46 #define ZIP_MAX_NCBP_SIZE	8
47 
48 /* size of instruction queue in units of instruction size */
49 #define ZIP_MAX_NUM_CMDS	((ZIP_MAX_CHUNK_SIZE - ZIP_MAX_NCBP_SIZE) / \
50 				ZIP_CMD_SIZE) /* 63 */
51 
52 /* size of instruct queue in bytes */
53 #define ZIP_MAX_CMDQ_SIZE	((ZIP_MAX_NUM_CMDS * ZIP_CMD_SIZE) + \
54 				ZIP_MAX_NCBP_SIZE)/* ~8072ull */
55 
56 #define ZIP_BUF_SIZE	256
57 
58 #define ZIP_SGPTR_ALIGN	16
59 #define ZIP_CMDQ_ALIGN	128
60 #define MAX_SG_LEN	((ZIP_BUF_SIZE - ZIP_SGPTR_ALIGN) / sizeof(void *))
61 
62 /**< ZIP PMD specified queue pairs */
63 #define ZIP_MAX_VF_QUEUE	1
64 
65 #define ZIP_ALIGN_ROUNDUP(x, _align) \
66 	((_align) * (((x) + (_align) - 1) / (_align)))
67 
68 /**< ZIP PMD device name */
69 #define COMPRESSDEV_NAME_ZIP_PMD	compress_octeonx
70 
71 #define ZIP_PMD_LOG(level, fmt, args...) \
72 	rte_log(RTE_LOG_ ## level, \
73 	octtx_zip_logtype_driver, "%s(): "fmt "\n", \
74 	__func__, ##args)
75 
76 #define ZIP_PMD_INFO(fmt, args...) \
77 	ZIP_PMD_LOG(INFO, fmt, ## args)
78 #define ZIP_PMD_ERR(fmt, args...) \
79 	ZIP_PMD_LOG(ERR, fmt, ## args)
80 
81 /* resources required to process stream */
82 enum NUM_BUFS_PER_STREAM {
83 	RES_BUF = 0,
84 	CMD_BUF,
85 	HASH_CTX_BUF,
86 	DECOMP_CTX_BUF,
87 	IN_DATA_BUF,
88 	OUT_DATA_BUF,
89 	HISTORY_DATA_BUF,
90 	MAX_BUFS_PER_STREAM
91 };
92 
93 struct zip_stream;
94 struct zipvf_qp;
95 
96 /* Algorithm handler function prototype */
97 typedef int (*comp_func_t)(struct rte_comp_op *op,
98 			   struct zipvf_qp *qp, struct zip_stream *zstrm);
99 
100 /**
101  * ZIP private stream structure
102  */
103 struct zip_stream {
104 	union zip_inst_s *inst;
105 	/* zip instruction pointer */
106 	comp_func_t func;
107 	/* function to process comp operation */
108 	void *bufs[MAX_BUFS_PER_STREAM];
109 } __rte_cache_aligned;
110 
111 
112 /**
113  * ZIP instruction Queue
114  */
115 struct zipvf_cmdq {
116 	rte_spinlock_t qlock;
117 	/* queue lock */
118 	uint64_t *sw_head;
119 	/* pointer to start of 8-byte word length queue-head */
120 	uint8_t *va;
121 	/* pointer to instruction queue virtual address */
122 	rte_iova_t iova;
123 	/* iova addr of cmdq head*/
124 };
125 
126 /**
127  * ZIP device queue structure
128  */
129 struct zipvf_qp {
130 	struct zipvf_cmdq cmdq;
131 	/* Hardware instruction queue structure */
132 	struct rte_ring *processed_pkts;
133 	/* Ring for placing processed packets */
134 	struct rte_compressdev_stats qp_stats;
135 	/* Queue pair statistics */
136 	uint16_t id;
137 	/* Queue Pair Identifier */
138 	const char *name;
139 	/* Unique Queue Pair Name */
140 	struct zip_vf *vf;
141 	/* pointer to device, queue belongs to */
142 } __rte_cache_aligned;
143 
144 /**
145  * ZIP VF device structure.
146  */
147 struct zip_vf {
148 	int vfid;
149 	/* vf index */
150 	struct rte_pci_device *pdev;
151 	/* pci device */
152 	void *vbar0;
153 	/* CSR base address for underlying BAR0 VF.*/
154 	uint64_t dom_sdom;
155 	/* Storing mbox domain and subdomain id for app rerun*/
156 	uint32_t  max_nb_queue_pairs;
157 	/* pointer to device qps */
158 	struct rte_mempool *zip_mp;
159 	/* pointer to pools */
160 } __rte_cache_aligned;
161 
162 
163 static inline void
164 zipvf_prepare_in_buf(struct zip_stream *zstrm, struct rte_comp_op *op)
165 {
166 	uint32_t offset, inlen;
167 	struct rte_mbuf *m_src;
168 	union zip_inst_s *inst = zstrm->inst;
169 
170 	inlen = op->src.length;
171 	offset = op->src.offset;
172 	m_src = op->m_src;
173 
174 	/* Prepare direct input data pointer */
175 	inst->s.dg = 0;
176 	inst->s.inp_ptr_addr.s.addr =
177 			rte_pktmbuf_iova_offset(m_src, offset);
178 	inst->s.inp_ptr_ctl.s.length = inlen;
179 }
180 
181 static inline void
182 zipvf_prepare_out_buf(struct zip_stream *zstrm, struct rte_comp_op *op)
183 {
184 	uint32_t offset;
185 	struct rte_mbuf *m_dst;
186 	union zip_inst_s *inst = zstrm->inst;
187 
188 	offset = op->dst.offset;
189 	m_dst = op->m_dst;
190 
191 	/* Prepare direct input data pointer */
192 	inst->s.ds = 0;
193 	inst->s.out_ptr_addr.s.addr =
194 			rte_pktmbuf_iova_offset(m_dst, offset);
195 	inst->s.totaloutputlength = rte_pktmbuf_pkt_len(m_dst) -
196 			op->dst.offset;
197 	inst->s.out_ptr_ctl.s.length = inst->s.totaloutputlength;
198 }
199 
200 static inline void
201 zipvf_prepare_cmd_stateless(struct rte_comp_op *op, struct zip_stream *zstrm)
202 {
203 	union zip_inst_s *inst = zstrm->inst;
204 
205 	/* set flush flag to always 1*/
206 	inst->s.ef = 1;
207 
208 	if (inst->s.op == ZIP_OP_E_DECOMP)
209 		inst->s.sf = 1;
210 	else
211 		inst->s.sf = 0;
212 
213 	/* Set input checksum */
214 	inst->s.adlercrc32 = op->input_chksum;
215 
216 	/* Prepare gather buffers */
217 	zipvf_prepare_in_buf(zstrm, op);
218 	zipvf_prepare_out_buf(zstrm, op);
219 }
220 
221 #ifdef ZIP_DBG
222 static inline void
223 zip_dump_instruction(void *inst)
224 {
225 	union zip_inst_s *cmd83 = (union zip_inst_s *)inst;
226 	printf("####### START ########\n");
227 	printf("doneint:%d totaloutputlength:%d\n", cmd83->s.doneint,
228 		cmd83->s.totaloutputlength);
229 	printf("exnum:%d iv:%d exbits:%d hmif:%d halg:%d\n", cmd83->s.exn,
230 		cmd83->s.iv, cmd83->s.exbits, cmd83->s.hmif, cmd83->s.halg);
231 	printf("flush:%d speed:%d cc:%d\n", cmd83->s.sf,
232 		cmd83->s.ss, cmd83->s.cc);
233 	printf("eof:%d bof:%d op:%d dscatter:%d dgather:%d hgather:%d\n",
234 		cmd83->s.ef, cmd83->s.bf, cmd83->s.op, cmd83->s.ds,
235 		cmd83->s.dg, cmd83->s.hg);
236 	printf("historylength:%d adler32:%d\n", cmd83->s.historylength,
237 		cmd83->s.adlercrc32);
238 	printf("ctx_ptr.addr:0x%"PRIx64"\n", cmd83->s.ctx_ptr_addr.s.addr);
239 	printf("ctx_ptr.len:%d\n", cmd83->s.ctx_ptr_ctl.s.length);
240 	printf("history_ptr.addr:0x%"PRIx64"\n", cmd83->s.his_ptr_addr.s.addr);
241 	printf("history_ptr.len:%d\n", cmd83->s.his_ptr_ctl.s.length);
242 	printf("inp_ptr.addr:0x%"PRIx64"\n", cmd83->s.inp_ptr_addr.s.addr);
243 	printf("inp_ptr.len:%d\n", cmd83->s.inp_ptr_ctl.s.length);
244 	printf("out_ptr.addr:0x%"PRIx64"\n", cmd83->s.out_ptr_addr.s.addr);
245 	printf("out_ptr.len:%d\n", cmd83->s.out_ptr_ctl.s.length);
246 	printf("result_ptr.len:%d\n", cmd83->s.res_ptr_ctl.s.length);
247 	printf("####### END ########\n");
248 }
249 #endif
250 
251 int
252 zipvf_create(struct rte_compressdev *compressdev);
253 
254 int
255 zipvf_destroy(struct rte_compressdev *compressdev);
256 
257 int
258 zipvf_q_init(struct zipvf_qp *qp);
259 
260 int
261 zipvf_q_term(struct zipvf_qp *qp);
262 
263 void
264 zipvf_push_command(struct zipvf_qp *qp, union zip_inst_s *zcmd);
265 
266 int
267 zip_process_op(struct rte_comp_op *op,
268 				struct zipvf_qp *qp,
269 				struct zip_stream *zstrm);
270 
271 uint64_t
272 zip_reg_read64(uint8_t *hw_addr, uint64_t offset);
273 
274 void
275 zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val);
276 
277 #endif /* _RTE_ZIP_VF_H_ */
278