1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <rte_pci.h> 9 #include <rte_spinlock.h> 10 #include <rte_comp.h> 11 #include <rte_compressdev.h> 12 #include <rte_compressdev_pmd.h> 13 14 #include <mlx5_glue.h> 15 #include <mlx5_common.h> 16 #include <mlx5_common_pci.h> 17 #include <mlx5_devx_cmds.h> 18 #include <mlx5_common_os.h> 19 #include <mlx5_common_devx.h> 20 #include <mlx5_common_mr.h> 21 #include <mlx5_prm.h> 22 23 #include "mlx5_compress_utils.h" 24 25 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress 26 #define MLX5_COMPRESS_MAX_QPS 1024 27 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u 28 29 struct mlx5_compress_xform { 30 LIST_ENTRY(mlx5_compress_xform) next; 31 enum rte_comp_xform_type type; 32 enum rte_comp_checksum_type csum_type; 33 uint32_t opcode; 34 uint32_t gga_ctrl1; /* BE. */ 35 }; 36 37 struct mlx5_compress_priv { 38 TAILQ_ENTRY(mlx5_compress_priv) next; 39 struct ibv_context *ctx; /* Device context. */ 40 struct rte_pci_device *pci_dev; 41 struct rte_compressdev *cdev; 42 void *uar; 43 uint32_t pdn; /* Protection Domain number. */ 44 uint8_t min_block_size; 45 uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ 46 /* Minimum huffman block size supported by the device. */ 47 struct ibv_pd *pd; 48 struct rte_compressdev_config dev_config; 49 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; 50 rte_spinlock_t xform_sl; 51 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 52 volatile uint64_t *uar_addr; 53 #ifndef RTE_ARCH_64 54 rte_spinlock_t uar32_sl; 55 #endif /* RTE_ARCH_64 */ 56 }; 57 58 struct mlx5_compress_qp { 59 uint16_t qp_id; 60 uint16_t entries_n; 61 uint16_t pi; 62 uint16_t ci; 63 struct mlx5_mr_ctrl mr_ctrl; 64 int socket_id; 65 struct mlx5_devx_cq cq; 66 struct mlx5_devx_sq sq; 67 struct mlx5_pmd_mr opaque_mr; 68 struct rte_comp_op **ops; 69 struct mlx5_compress_priv *priv; 70 struct rte_compressdev_stats stats; 71 }; 72 73 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list = 74 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list); 75 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 76 77 int mlx5_compress_logtype; 78 79 static const struct rte_compressdev_capabilities mlx5_caps[] = { 80 { 81 .algo = RTE_COMP_ALGO_NULL, 82 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 83 RTE_COMP_FF_CRC32_CHECKSUM | 84 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 85 RTE_COMP_FF_SHAREABLE_PRIV_XFORM, 86 }, 87 { 88 .algo = RTE_COMP_ALGO_DEFLATE, 89 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 90 RTE_COMP_FF_CRC32_CHECKSUM | 91 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 92 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 93 RTE_COMP_FF_HUFFMAN_FIXED | 94 RTE_COMP_FF_HUFFMAN_DYNAMIC, 95 .window_size = {.min = 10, .max = 15, .increment = 1}, 96 }, 97 { 98 .algo = RTE_COMP_ALGO_LIST_END, 99 } 100 }; 101 102 static void 103 mlx5_compress_dev_info_get(struct rte_compressdev *dev, 104 struct rte_compressdev_info *info) 105 { 106 RTE_SET_USED(dev); 107 if (info != NULL) { 108 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS; 109 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 110 info->capabilities = mlx5_caps; 111 } 112 } 113 114 static int 115 mlx5_compress_dev_configure(struct rte_compressdev *dev, 116 struct rte_compressdev_config *config) 117 { 118 struct mlx5_compress_priv *priv; 119 120 if (dev == NULL || config == NULL) 121 return -EINVAL; 122 priv = dev->data->dev_private; 123 priv->dev_config = *config; 124 return 0; 125 } 126 127 static int 128 mlx5_compress_dev_close(struct rte_compressdev *dev) 129 { 130 RTE_SET_USED(dev); 131 return 0; 132 } 133 134 static int 135 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) 136 { 137 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 138 139 if (qp->sq.sq != NULL) 140 mlx5_devx_sq_destroy(&qp->sq); 141 if (qp->cq.cq != NULL) 142 mlx5_devx_cq_destroy(&qp->cq); 143 if (qp->opaque_mr.obj != NULL) { 144 void *opaq = qp->opaque_mr.addr; 145 146 mlx5_common_verbs_dereg_mr(&qp->opaque_mr); 147 if (opaq != NULL) 148 rte_free(opaq); 149 } 150 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 151 rte_free(qp); 152 dev->data->queue_pairs[qp_id] = NULL; 153 return 0; 154 } 155 156 static void 157 mlx5_compress_init_sq(struct mlx5_compress_qp *qp) 158 { 159 volatile struct mlx5_gga_wqe *restrict wqe = 160 (volatile struct mlx5_gga_wqe *)qp->sq.wqes; 161 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 162 const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u); 163 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << 164 MLX5_COMP_MODE_OFFSET); 165 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey); 166 int i; 167 168 /* All the next fields state should stay constant. */ 169 for (i = 0; i < qp->entries_n; ++i, ++wqe) { 170 wqe->sq_ds = sq_ds; 171 wqe->flags = flags; 172 wqe->opaque_lkey = opaq_lkey; 173 wqe->opaque_vaddr = rte_cpu_to_be_64 174 ((uint64_t)(uintptr_t)&opaq[i]); 175 } 176 } 177 178 static int 179 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, 180 uint32_t max_inflight_ops, int socket_id) 181 { 182 struct mlx5_compress_priv *priv = dev->data->dev_private; 183 struct mlx5_compress_qp *qp; 184 struct mlx5_devx_cq_attr cq_attr = { 185 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), 186 }; 187 struct mlx5_devx_create_sq_attr sq_attr = { 188 .user_index = qp_id, 189 .wq_attr = (struct mlx5_devx_wq_attr){ 190 .pd = priv->pdn, 191 .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar), 192 }, 193 }; 194 struct mlx5_devx_modify_sq_attr modify_attr = { 195 .state = MLX5_SQC_STATE_RDY, 196 }; 197 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); 198 uint32_t alloc_size = sizeof(*qp); 199 void *opaq_buf; 200 int ret; 201 202 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 203 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n); 204 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 205 socket_id); 206 if (qp == NULL) { 207 DRV_LOG(ERR, "Failed to allocate qp memory."); 208 rte_errno = ENOMEM; 209 return -rte_errno; 210 } 211 dev->data->queue_pairs[qp_id] = qp; 212 opaq_buf = rte_calloc(__func__, 1u << log_ops_n, 213 sizeof(struct mlx5_gga_compress_opaque), 214 sizeof(struct mlx5_gga_compress_opaque)); 215 if (opaq_buf == NULL) { 216 DRV_LOG(ERR, "Failed to allocate opaque memory."); 217 rte_errno = ENOMEM; 218 goto err; 219 } 220 if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N, 221 priv->dev_config.socket_id)) { 222 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 223 (uint32_t)qp_id); 224 rte_errno = ENOMEM; 225 goto err; 226 } 227 qp->entries_n = 1 << log_ops_n; 228 qp->socket_id = socket_id; 229 qp->qp_id = qp_id; 230 qp->priv = priv; 231 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), 232 RTE_CACHE_LINE_SIZE); 233 if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n * 234 sizeof(struct mlx5_gga_compress_opaque), 235 &qp->opaque_mr) != 0) { 236 rte_free(opaq_buf); 237 DRV_LOG(ERR, "Failed to register opaque MR."); 238 rte_errno = ENOMEM; 239 goto err; 240 } 241 ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr, 242 socket_id); 243 if (ret != 0) { 244 DRV_LOG(ERR, "Failed to create CQ."); 245 goto err; 246 } 247 sq_attr.cqn = qp->cq.cq->id; 248 sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format); 249 ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr, 250 socket_id); 251 if (ret != 0) { 252 DRV_LOG(ERR, "Failed to create SQ."); 253 goto err; 254 } 255 mlx5_compress_init_sq(qp); 256 ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr); 257 if (ret != 0) { 258 DRV_LOG(ERR, "Can't change SQ state to ready."); 259 goto err; 260 } 261 /* Save pointer of global generation number to check memory event. */ 262 qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen; 263 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", 264 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n); 265 return 0; 266 err: 267 mlx5_compress_qp_release(dev, qp_id); 268 return -1; 269 } 270 271 static int 272 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform) 273 { 274 struct mlx5_compress_priv *priv = dev->data->dev_private; 275 276 rte_spinlock_lock(&priv->xform_sl); 277 LIST_REMOVE((struct mlx5_compress_xform *)xform, next); 278 rte_spinlock_unlock(&priv->xform_sl); 279 rte_free(xform); 280 return 0; 281 } 282 283 static int 284 mlx5_compress_xform_create(struct rte_compressdev *dev, 285 const struct rte_comp_xform *xform, 286 void **private_xform) 287 { 288 struct mlx5_compress_priv *priv = dev->data->dev_private; 289 struct mlx5_compress_xform *xfrm; 290 uint32_t size; 291 292 if (xform->type == RTE_COMP_COMPRESS && xform->compress.level == 293 RTE_COMP_LEVEL_NONE) { 294 DRV_LOG(ERR, "Non-compressed block is not supported."); 295 return -ENOTSUP; 296 } 297 if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo != 298 RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS && 299 xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) { 300 DRV_LOG(ERR, "SHA is not supported."); 301 return -ENOTSUP; 302 } 303 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0, 304 priv->dev_config.socket_id); 305 if (xfrm == NULL) 306 return -ENOMEM; 307 xfrm->opcode = MLX5_OPCODE_MMO; 308 xfrm->type = xform->type; 309 switch (xform->type) { 310 case RTE_COMP_COMPRESS: 311 switch (xform->compress.algo) { 312 case RTE_COMP_ALGO_NULL: 313 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 314 WQE_CSEG_OPC_MOD_OFFSET; 315 break; 316 case RTE_COMP_ALGO_DEFLATE: 317 size = 1 << xform->compress.window_size; 318 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS; 319 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), 320 MLX5_COMP_MAX_WIN_SIZE_CONF) << 321 WQE_GGA_COMP_WIN_SIZE_OFFSET; 322 if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT) 323 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 324 else 325 size = priv->min_block_size - 1 + 326 xform->compress.level; 327 xfrm->gga_ctrl1 += RTE_MIN(size, 328 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) << 329 WQE_GGA_COMP_BLOCK_SIZE_OFFSET; 330 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << 331 WQE_CSEG_OPC_MOD_OFFSET; 332 size = xform->compress.deflate.huffman == 333 RTE_COMP_HUFFMAN_DYNAMIC ? 334 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX : 335 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN; 336 xfrm->gga_ctrl1 += size << 337 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET; 338 break; 339 default: 340 goto err; 341 } 342 xfrm->csum_type = xform->compress.chksum; 343 break; 344 case RTE_COMP_DECOMPRESS: 345 switch (xform->decompress.algo) { 346 case RTE_COMP_ALGO_NULL: 347 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 348 WQE_CSEG_OPC_MOD_OFFSET; 349 break; 350 case RTE_COMP_ALGO_DEFLATE: 351 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << 352 WQE_CSEG_OPC_MOD_OFFSET; 353 break; 354 default: 355 goto err; 356 } 357 xfrm->csum_type = xform->decompress.chksum; 358 break; 359 default: 360 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type); 361 goto err; 362 } 363 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum " 364 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type); 365 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1); 366 rte_spinlock_lock(&priv->xform_sl); 367 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next); 368 rte_spinlock_unlock(&priv->xform_sl); 369 *private_xform = xfrm; 370 return 0; 371 err: 372 rte_free(xfrm); 373 return -ENOTSUP; 374 } 375 376 static void 377 mlx5_compress_dev_stop(struct rte_compressdev *dev) 378 { 379 RTE_SET_USED(dev); 380 } 381 382 static int 383 mlx5_compress_dev_start(struct rte_compressdev *dev) 384 { 385 RTE_SET_USED(dev); 386 return 0; 387 } 388 389 static void 390 mlx5_compress_stats_get(struct rte_compressdev *dev, 391 struct rte_compressdev_stats *stats) 392 { 393 int qp_id; 394 395 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 396 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 397 398 stats->enqueued_count += qp->stats.enqueued_count; 399 stats->dequeued_count += qp->stats.dequeued_count; 400 stats->enqueue_err_count += qp->stats.enqueue_err_count; 401 stats->dequeue_err_count += qp->stats.dequeue_err_count; 402 } 403 } 404 405 static void 406 mlx5_compress_stats_reset(struct rte_compressdev *dev) 407 { 408 int qp_id; 409 410 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 411 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 412 413 memset(&qp->stats, 0, sizeof(qp->stats)); 414 } 415 } 416 417 static struct rte_compressdev_ops mlx5_compress_ops = { 418 .dev_configure = mlx5_compress_dev_configure, 419 .dev_start = mlx5_compress_dev_start, 420 .dev_stop = mlx5_compress_dev_stop, 421 .dev_close = mlx5_compress_dev_close, 422 .dev_infos_get = mlx5_compress_dev_info_get, 423 .stats_get = mlx5_compress_stats_get, 424 .stats_reset = mlx5_compress_stats_reset, 425 .queue_pair_setup = mlx5_compress_qp_setup, 426 .queue_pair_release = mlx5_compress_qp_release, 427 .private_xform_create = mlx5_compress_xform_create, 428 .private_xform_free = mlx5_compress_xform_free, 429 .stream_create = NULL, 430 .stream_free = NULL, 431 }; 432 433 /** 434 * Query LKey from a packet buffer for QP. If not found, add the mempool. 435 * 436 * @param priv 437 * Pointer to the priv object. 438 * @param addr 439 * Search key. 440 * @param mr_ctrl 441 * Pointer to per-queue MR control structure. 442 * @param ol_flags 443 * Mbuf offload features. 444 * 445 * @return 446 * Searched LKey on success, UINT32_MAX on no match. 447 */ 448 static __rte_always_inline uint32_t 449 mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr, 450 struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags) 451 { 452 uint32_t lkey; 453 454 /* Check generation bit to see if there's any change on existing MRs. */ 455 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 456 mlx5_mr_flush_local_cache(mr_ctrl); 457 /* Linear search on MR cache array. */ 458 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 459 MLX5_MR_CACHE_N, addr); 460 if (likely(lkey != UINT32_MAX)) 461 return lkey; 462 /* Take slower bottom-half on miss. */ 463 return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr, 464 !!(ol_flags & EXT_ATTACHED_MBUF)); 465 } 466 467 static __rte_always_inline uint32_t 468 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, 469 volatile struct mlx5_wqe_dseg *restrict dseg, 470 struct rte_mbuf *restrict mbuf, 471 uint32_t offset, uint32_t len) 472 { 473 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 474 475 dseg->bcount = rte_cpu_to_be_32(len); 476 dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl, 477 mbuf->ol_flags); 478 dseg->pbuf = rte_cpu_to_be_64(addr); 479 return dseg->lkey; 480 } 481 482 /* 483 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 484 * 64bit architectures. 485 */ 486 static __rte_always_inline void 487 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv) 488 { 489 #ifdef RTE_ARCH_64 490 *priv->uar_addr = val; 491 #else /* !RTE_ARCH_64 */ 492 rte_spinlock_lock(&priv->uar32_sl); 493 *(volatile uint32_t *)priv->uar_addr = val; 494 rte_io_wmb(); 495 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; 496 rte_spinlock_unlock(&priv->uar32_sl); 497 #endif 498 } 499 500 static uint16_t 501 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, 502 uint16_t nb_ops) 503 { 504 struct mlx5_compress_qp *qp = queue_pair; 505 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 506 qp->sq.wqes, *wqe; 507 struct mlx5_compress_xform *xform; 508 struct rte_comp_op *op; 509 uint16_t mask = qp->entries_n - 1; 510 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 511 uint16_t idx; 512 bool invalid; 513 514 if (remain < nb_ops) 515 nb_ops = remain; 516 else 517 remain = nb_ops; 518 if (unlikely(remain == 0)) 519 return 0; 520 do { 521 idx = qp->pi & mask; 522 wqe = &wqes[idx]; 523 rte_prefetch0(&wqes[(qp->pi + 1) & mask]); 524 op = *ops++; 525 xform = op->private_xform; 526 /* 527 * Check operation arguments and error cases: 528 * - Operation type must be state-less. 529 * - Compress operation flush flag must be FULL or FINAL. 530 * - Source and destination buffers must be mapped internally. 531 */ 532 invalid = op->op_type != RTE_COMP_OP_STATELESS || 533 (xform->type == RTE_COMP_COMPRESS && 534 op->flush_flag < RTE_COMP_FLUSH_FULL); 535 if (unlikely(invalid || 536 (mlx5_compress_dseg_set(qp, &wqe->gather, 537 op->m_src, 538 op->src.offset, 539 op->src.length) == 540 UINT32_MAX) || 541 (mlx5_compress_dseg_set(qp, &wqe->scatter, 542 op->m_dst, 543 op->dst.offset, 544 rte_pktmbuf_pkt_len(op->m_dst) - 545 op->dst.offset) == 546 UINT32_MAX))) { 547 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS : 548 RTE_COMP_OP_STATUS_ERROR; 549 nb_ops -= remain; 550 if (unlikely(nb_ops == 0)) 551 return 0; 552 break; 553 } 554 wqe->gga_ctrl1 = xform->gga_ctrl1; 555 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8)); 556 qp->ops[idx] = op; 557 qp->pi++; 558 } while (--remain); 559 qp->stats.enqueued_count += nb_ops; 560 rte_io_wmb(); 561 qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); 562 rte_wmb(); 563 mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv); 564 rte_wmb(); 565 return nb_ops; 566 } 567 568 static void 569 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, 570 volatile uint32_t *opaq) 571 { 572 size_t i; 573 574 DRV_LOG(ERR, "Error cqe:"); 575 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4) 576 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], 577 cqe[i + 2], cqe[i + 3]); 578 DRV_LOG(ERR, "\nError wqe:"); 579 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4) 580 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1], 581 wqe[i + 2], wqe[i + 3]); 582 DRV_LOG(ERR, "\nError opaq:"); 583 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4) 584 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1], 585 opaq[i + 2], opaq[i + 3]); 586 } 587 588 static void 589 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, 590 struct rte_comp_op *op) 591 { 592 const uint32_t idx = qp->ci & (qp->entries_n - 1); 593 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 594 &qp->cq.cqes[idx]; 595 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 596 qp->sq.wqes; 597 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 598 599 op->status = RTE_COMP_OP_STATUS_ERROR; 600 op->consumed = 0; 601 op->produced = 0; 602 op->output_chksum = 0; 603 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) | 604 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32); 605 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe, 606 (volatile uint32_t *)&wqes[idx], 607 (volatile uint32_t *)&opaq[idx]); 608 qp->stats.dequeue_err_count++; 609 } 610 611 static uint16_t 612 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, 613 uint16_t nb_ops) 614 { 615 struct mlx5_compress_qp *qp = queue_pair; 616 volatile struct mlx5_compress_xform *restrict xform; 617 volatile struct mlx5_cqe *restrict cqe; 618 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 619 struct rte_comp_op *restrict op; 620 const unsigned int cq_size = qp->entries_n; 621 const unsigned int mask = cq_size - 1; 622 uint32_t idx; 623 uint32_t next_idx = qp->ci & mask; 624 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 625 uint16_t i = 0; 626 int ret; 627 628 if (unlikely(max == 0)) 629 return 0; 630 do { 631 idx = next_idx; 632 next_idx = (qp->ci + 1) & mask; 633 rte_prefetch0(&qp->cq.cqes[next_idx]); 634 rte_prefetch0(qp->ops[next_idx]); 635 op = qp->ops[idx]; 636 cqe = &qp->cq.cqes[idx]; 637 ret = check_cqe(cqe, cq_size, qp->ci); 638 /* 639 * Be sure owner read is done before any other cookie field or 640 * opaque field. 641 */ 642 rte_io_rmb(); 643 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 644 if (likely(ret == MLX5_CQE_STATUS_HW_OWN)) 645 break; 646 mlx5_compress_cqe_err_handle(qp, op); 647 } else { 648 xform = op->private_xform; 649 op->status = RTE_COMP_OP_STATUS_SUCCESS; 650 op->consumed = op->src.length; 651 op->produced = rte_be_to_cpu_32(cqe->byte_cnt); 652 MLX5_ASSERT(cqe->byte_cnt == 653 opaq[idx].scattered_length); 654 switch (xform->csum_type) { 655 case RTE_COMP_CHECKSUM_CRC32: 656 op->output_chksum = (uint64_t)rte_be_to_cpu_32 657 (opaq[idx].crc32); 658 break; 659 case RTE_COMP_CHECKSUM_ADLER32: 660 op->output_chksum = (uint64_t)rte_be_to_cpu_32 661 (opaq[idx].adler32) << 32; 662 break; 663 case RTE_COMP_CHECKSUM_CRC32_ADLER32: 664 op->output_chksum = (uint64_t)rte_be_to_cpu_32 665 (opaq[idx].crc32) | 666 ((uint64_t)rte_be_to_cpu_32 667 (opaq[idx].adler32) << 32); 668 break; 669 default: 670 break; 671 } 672 } 673 ops[i++] = op; 674 qp->ci++; 675 } while (i < max); 676 if (likely(i != 0)) { 677 rte_io_wmb(); 678 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci); 679 qp->stats.dequeued_count += i; 680 } 681 return i; 682 } 683 684 static void 685 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv) 686 { 687 if (priv->pd != NULL) { 688 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 689 priv->pd = NULL; 690 } 691 if (priv->uar != NULL) { 692 mlx5_glue->devx_free_uar(priv->uar); 693 priv->uar = NULL; 694 } 695 } 696 697 static int 698 mlx5_compress_pd_create(struct mlx5_compress_priv *priv) 699 { 700 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 701 struct mlx5dv_obj obj; 702 struct mlx5dv_pd pd_info; 703 int ret; 704 705 priv->pd = mlx5_glue->alloc_pd(priv->ctx); 706 if (priv->pd == NULL) { 707 DRV_LOG(ERR, "Failed to allocate PD."); 708 return errno ? -errno : -ENOMEM; 709 } 710 obj.pd.in = priv->pd; 711 obj.pd.out = &pd_info; 712 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 713 if (ret != 0) { 714 DRV_LOG(ERR, "Fail to get PD object info."); 715 mlx5_glue->dealloc_pd(priv->pd); 716 priv->pd = NULL; 717 return -errno; 718 } 719 priv->pdn = pd_info.pdn; 720 return 0; 721 #else 722 (void)priv; 723 DRV_LOG(ERR, "Cannot get pdn - no DV support."); 724 return -ENOTSUP; 725 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 726 } 727 728 static int 729 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv) 730 { 731 if (mlx5_compress_pd_create(priv) != 0) 732 return -1; 733 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1); 734 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) == 735 NULL) { 736 rte_errno = errno; 737 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 738 DRV_LOG(ERR, "Failed to allocate UAR."); 739 return -1; 740 } 741 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); 742 MLX5_ASSERT(priv->uar_addr); 743 #ifndef RTE_ARCH_64 744 rte_spinlock_init(&priv->uar32_sl); 745 #endif /* RTE_ARCH_64 */ 746 return 0; 747 } 748 749 /** 750 * Callback for memory event. 751 * 752 * @param event_type 753 * Memory event type. 754 * @param addr 755 * Address of memory. 756 * @param len 757 * Size of memory. 758 */ 759 static void 760 mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, 761 size_t len, void *arg __rte_unused) 762 { 763 struct mlx5_compress_priv *priv; 764 765 /* Must be called from the primary process. */ 766 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 767 switch (event_type) { 768 case RTE_MEM_EVENT_FREE: 769 pthread_mutex_lock(&priv_list_lock); 770 /* Iterate all the existing mlx5 devices. */ 771 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 772 mlx5_free_mr_by_addr(&priv->mr_scache, 773 priv->ctx->device->name, 774 addr, len); 775 pthread_mutex_unlock(&priv_list_lock); 776 break; 777 case RTE_MEM_EVENT_ALLOC: 778 default: 779 break; 780 } 781 } 782 783 /** 784 * DPDK callback to register a PCI device. 785 * 786 * This function spawns compress device out of a given PCI device. 787 * 788 * @param[in] pci_drv 789 * PCI driver structure (mlx5_compress_driver). 790 * @param[in] pci_dev 791 * PCI device information. 792 * 793 * @return 794 * 0 on success, 1 to skip this driver, a negative errno value otherwise 795 * and rte_errno is set. 796 */ 797 static int 798 mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, 799 struct rte_pci_device *pci_dev) 800 { 801 struct ibv_device *ibv; 802 struct rte_compressdev *cdev; 803 struct ibv_context *ctx; 804 struct mlx5_compress_priv *priv; 805 struct mlx5_hca_attr att = { 0 }; 806 struct rte_compressdev_pmd_init_params init_params = { 807 .name = "", 808 .socket_id = pci_dev->device.numa_node, 809 }; 810 811 RTE_SET_USED(pci_drv); 812 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 813 DRV_LOG(ERR, "Non-primary process type is not supported."); 814 rte_errno = ENOTSUP; 815 return -rte_errno; 816 } 817 ibv = mlx5_os_get_ibv_device(&pci_dev->addr); 818 if (ibv == NULL) { 819 DRV_LOG(ERR, "No matching IB device for PCI slot " 820 PCI_PRI_FMT ".", pci_dev->addr.domain, 821 pci_dev->addr.bus, pci_dev->addr.devid, 822 pci_dev->addr.function); 823 return -rte_errno; 824 } 825 DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name); 826 ctx = mlx5_glue->dv_open_device(ibv); 827 if (ctx == NULL) { 828 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); 829 rte_errno = ENODEV; 830 return -rte_errno; 831 } 832 if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 || 833 att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 || 834 att.mmo_dma_en == 0) { 835 DRV_LOG(ERR, "Not enough capabilities to support compress " 836 "operations, maybe old FW/OFED version?"); 837 claim_zero(mlx5_glue->close_device(ctx)); 838 rte_errno = ENOTSUP; 839 return -ENOTSUP; 840 } 841 cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device, 842 sizeof(*priv), &init_params); 843 if (cdev == NULL) { 844 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); 845 claim_zero(mlx5_glue->close_device(ctx)); 846 return -ENODEV; 847 } 848 DRV_LOG(INFO, 849 "Compress device %s was created successfully.", ibv->name); 850 cdev->dev_ops = &mlx5_compress_ops; 851 cdev->dequeue_burst = mlx5_compress_dequeue_burst; 852 cdev->enqueue_burst = mlx5_compress_enqueue_burst; 853 cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 854 priv = cdev->data->dev_private; 855 priv->ctx = ctx; 856 priv->pci_dev = pci_dev; 857 priv->cdev = cdev; 858 priv->min_block_size = att.compress_min_block_size; 859 priv->sq_ts_format = att.sq_ts_format; 860 if (mlx5_compress_hw_global_prepare(priv) != 0) { 861 rte_compressdev_pmd_destroy(priv->cdev); 862 claim_zero(mlx5_glue->close_device(priv->ctx)); 863 return -1; 864 } 865 if (mlx5_mr_btree_init(&priv->mr_scache.cache, 866 MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) { 867 DRV_LOG(ERR, "Failed to allocate shared cache MR memory."); 868 mlx5_compress_hw_global_release(priv); 869 rte_compressdev_pmd_destroy(priv->cdev); 870 claim_zero(mlx5_glue->close_device(priv->ctx)); 871 rte_errno = ENOMEM; 872 return -rte_errno; 873 } 874 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; 875 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; 876 /* Register callback function for global shared MR cache management. */ 877 if (TAILQ_EMPTY(&mlx5_compress_priv_list)) 878 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 879 mlx5_compress_mr_mem_event_cb, 880 NULL); 881 pthread_mutex_lock(&priv_list_lock); 882 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next); 883 pthread_mutex_unlock(&priv_list_lock); 884 return 0; 885 } 886 887 /** 888 * DPDK callback to remove a PCI device. 889 * 890 * This function removes all compress devices belong to a given PCI device. 891 * 892 * @param[in] pci_dev 893 * Pointer to the PCI device. 894 * 895 * @return 896 * 0 on success, the function cannot fail. 897 */ 898 static int 899 mlx5_compress_pci_remove(struct rte_pci_device *pdev) 900 { 901 struct mlx5_compress_priv *priv = NULL; 902 903 pthread_mutex_lock(&priv_list_lock); 904 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 905 if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0) 906 break; 907 if (priv) 908 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); 909 pthread_mutex_unlock(&priv_list_lock); 910 if (priv) { 911 if (TAILQ_EMPTY(&mlx5_compress_priv_list)) 912 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", 913 NULL); 914 mlx5_mr_release_cache(&priv->mr_scache); 915 mlx5_compress_hw_global_release(priv); 916 rte_compressdev_pmd_destroy(priv->cdev); 917 claim_zero(mlx5_glue->close_device(priv->ctx)); 918 } 919 return 0; 920 } 921 922 static const struct rte_pci_id mlx5_compress_pci_id_map[] = { 923 { 924 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 925 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 926 }, 927 { 928 .vendor_id = 0 929 } 930 }; 931 932 static struct mlx5_pci_driver mlx5_compress_driver = { 933 .driver_class = MLX5_CLASS_COMPRESS, 934 .pci_driver = { 935 .driver = { 936 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), 937 }, 938 .id_table = mlx5_compress_pci_id_map, 939 .probe = mlx5_compress_pci_probe, 940 .remove = mlx5_compress_pci_remove, 941 .drv_flags = 0, 942 }, 943 }; 944 945 RTE_INIT(rte_mlx5_compress_init) 946 { 947 mlx5_common_init(); 948 if (mlx5_glue != NULL) 949 mlx5_pci_driver_register(&mlx5_compress_driver); 950 } 951 952 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) 953 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__); 954 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map); 955 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 956