1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <rte_pci.h> 9 #include <rte_spinlock.h> 10 #include <rte_comp.h> 11 #include <rte_compressdev.h> 12 #include <rte_compressdev_pmd.h> 13 14 #include <mlx5_glue.h> 15 #include <mlx5_common.h> 16 #include <mlx5_common_pci.h> 17 #include <mlx5_devx_cmds.h> 18 #include <mlx5_common_os.h> 19 #include <mlx5_common_devx.h> 20 #include <mlx5_common_mr.h> 21 #include <mlx5_prm.h> 22 23 #include "mlx5_compress_utils.h" 24 25 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress 26 #define MLX5_COMPRESS_MAX_QPS 1024 27 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u 28 29 struct mlx5_compress_xform { 30 LIST_ENTRY(mlx5_compress_xform) next; 31 enum rte_comp_xform_type type; 32 enum rte_comp_checksum_type csum_type; 33 uint32_t opcode; 34 uint32_t gga_ctrl1; /* BE. */ 35 }; 36 37 struct mlx5_compress_priv { 38 TAILQ_ENTRY(mlx5_compress_priv) next; 39 struct ibv_context *ctx; /* Device context. */ 40 struct rte_pci_device *pci_dev; 41 struct rte_compressdev *cdev; 42 void *uar; 43 uint32_t pdn; /* Protection Domain number. */ 44 uint8_t min_block_size; 45 uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ 46 /* Minimum huffman block size supported by the device. */ 47 struct ibv_pd *pd; 48 struct rte_compressdev_config dev_config; 49 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; 50 rte_spinlock_t xform_sl; 51 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 52 volatile uint64_t *uar_addr; 53 #ifndef RTE_ARCH_64 54 rte_spinlock_t uar32_sl; 55 #endif /* RTE_ARCH_64 */ 56 }; 57 58 struct mlx5_compress_qp { 59 uint16_t qp_id; 60 uint16_t entries_n; 61 uint16_t pi; 62 uint16_t ci; 63 struct mlx5_mr_ctrl mr_ctrl; 64 int socket_id; 65 struct mlx5_devx_cq cq; 66 struct mlx5_devx_sq sq; 67 struct mlx5_pmd_mr opaque_mr; 68 struct rte_comp_op **ops; 69 struct mlx5_compress_priv *priv; 70 struct rte_compressdev_stats stats; 71 }; 72 73 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list = 74 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list); 75 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 76 77 int mlx5_compress_logtype; 78 79 static const struct rte_compressdev_capabilities mlx5_caps[] = { 80 { 81 .algo = RTE_COMP_ALGO_NULL, 82 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 83 RTE_COMP_FF_CRC32_CHECKSUM | 84 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 85 RTE_COMP_FF_SHAREABLE_PRIV_XFORM, 86 }, 87 { 88 .algo = RTE_COMP_ALGO_DEFLATE, 89 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 90 RTE_COMP_FF_CRC32_CHECKSUM | 91 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 92 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 93 RTE_COMP_FF_HUFFMAN_FIXED | 94 RTE_COMP_FF_HUFFMAN_DYNAMIC, 95 .window_size = {.min = 10, .max = 15, .increment = 1}, 96 }, 97 { 98 .algo = RTE_COMP_ALGO_LIST_END, 99 } 100 }; 101 102 static void 103 mlx5_compress_dev_info_get(struct rte_compressdev *dev, 104 struct rte_compressdev_info *info) 105 { 106 RTE_SET_USED(dev); 107 if (info != NULL) { 108 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS; 109 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 110 info->capabilities = mlx5_caps; 111 } 112 } 113 114 static int 115 mlx5_compress_dev_configure(struct rte_compressdev *dev, 116 struct rte_compressdev_config *config) 117 { 118 struct mlx5_compress_priv *priv; 119 120 if (dev == NULL || config == NULL) 121 return -EINVAL; 122 priv = dev->data->dev_private; 123 priv->dev_config = *config; 124 return 0; 125 } 126 127 static int 128 mlx5_compress_dev_close(struct rte_compressdev *dev) 129 { 130 RTE_SET_USED(dev); 131 return 0; 132 } 133 134 static int 135 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) 136 { 137 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 138 139 if (qp->sq.sq != NULL) 140 mlx5_devx_sq_destroy(&qp->sq); 141 if (qp->cq.cq != NULL) 142 mlx5_devx_cq_destroy(&qp->cq); 143 if (qp->opaque_mr.obj != NULL) { 144 void *opaq = qp->opaque_mr.addr; 145 146 mlx5_common_verbs_dereg_mr(&qp->opaque_mr); 147 if (opaq != NULL) 148 rte_free(opaq); 149 } 150 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 151 rte_free(qp); 152 dev->data->queue_pairs[qp_id] = NULL; 153 return 0; 154 } 155 156 static void 157 mlx5_compress_init_sq(struct mlx5_compress_qp *qp) 158 { 159 volatile struct mlx5_gga_wqe *restrict wqe = 160 (volatile struct mlx5_gga_wqe *)qp->sq.wqes; 161 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 162 const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u); 163 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << 164 MLX5_COMP_MODE_OFFSET); 165 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey); 166 int i; 167 168 /* All the next fields state should stay constant. */ 169 for (i = 0; i < qp->entries_n; ++i, ++wqe) { 170 wqe->sq_ds = sq_ds; 171 wqe->flags = flags; 172 wqe->opaque_lkey = opaq_lkey; 173 wqe->opaque_vaddr = rte_cpu_to_be_64 174 ((uint64_t)(uintptr_t)&opaq[i]); 175 } 176 } 177 178 static int 179 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, 180 uint32_t max_inflight_ops, int socket_id) 181 { 182 struct mlx5_compress_priv *priv = dev->data->dev_private; 183 struct mlx5_compress_qp *qp; 184 struct mlx5_devx_cq_attr cq_attr = { 185 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), 186 }; 187 struct mlx5_devx_create_sq_attr sq_attr = { 188 .user_index = qp_id, 189 .wq_attr = (struct mlx5_devx_wq_attr){ 190 .pd = priv->pdn, 191 .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar), 192 }, 193 }; 194 struct mlx5_devx_modify_sq_attr modify_attr = { 195 .state = MLX5_SQC_STATE_RDY, 196 }; 197 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); 198 uint32_t alloc_size = sizeof(*qp); 199 void *opaq_buf; 200 int ret; 201 202 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 203 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n); 204 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 205 socket_id); 206 if (qp == NULL) { 207 DRV_LOG(ERR, "Failed to allocate qp memory."); 208 rte_errno = ENOMEM; 209 return -rte_errno; 210 } 211 dev->data->queue_pairs[qp_id] = qp; 212 opaq_buf = rte_calloc(__func__, 1u << log_ops_n, 213 sizeof(struct mlx5_gga_compress_opaque), 214 sizeof(struct mlx5_gga_compress_opaque)); 215 if (opaq_buf == NULL) { 216 DRV_LOG(ERR, "Failed to allocate opaque memory."); 217 rte_errno = ENOMEM; 218 goto err; 219 } 220 if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N, 221 priv->dev_config.socket_id)) { 222 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 223 (uint32_t)qp_id); 224 rte_errno = ENOMEM; 225 goto err; 226 } 227 qp->entries_n = 1 << log_ops_n; 228 qp->socket_id = socket_id; 229 qp->qp_id = qp_id; 230 qp->priv = priv; 231 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), 232 RTE_CACHE_LINE_SIZE); 233 if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n * 234 sizeof(struct mlx5_gga_compress_opaque), 235 &qp->opaque_mr) != 0) { 236 rte_free(opaq_buf); 237 DRV_LOG(ERR, "Failed to register opaque MR."); 238 rte_errno = ENOMEM; 239 goto err; 240 } 241 ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr, 242 socket_id); 243 if (ret != 0) { 244 DRV_LOG(ERR, "Failed to create CQ."); 245 goto err; 246 } 247 sq_attr.cqn = qp->cq.cq->id; 248 sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format); 249 ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr, 250 socket_id); 251 if (ret != 0) { 252 DRV_LOG(ERR, "Failed to create SQ."); 253 goto err; 254 } 255 mlx5_compress_init_sq(qp); 256 ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr); 257 if (ret != 0) { 258 DRV_LOG(ERR, "Can't change SQ state to ready."); 259 goto err; 260 } 261 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", 262 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n); 263 return 0; 264 err: 265 mlx5_compress_qp_release(dev, qp_id); 266 return -1; 267 } 268 269 static int 270 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform) 271 { 272 struct mlx5_compress_priv *priv = dev->data->dev_private; 273 274 rte_spinlock_lock(&priv->xform_sl); 275 LIST_REMOVE((struct mlx5_compress_xform *)xform, next); 276 rte_spinlock_unlock(&priv->xform_sl); 277 rte_free(xform); 278 return 0; 279 } 280 281 static int 282 mlx5_compress_xform_create(struct rte_compressdev *dev, 283 const struct rte_comp_xform *xform, 284 void **private_xform) 285 { 286 struct mlx5_compress_priv *priv = dev->data->dev_private; 287 struct mlx5_compress_xform *xfrm; 288 uint32_t size; 289 290 if (xform->type == RTE_COMP_COMPRESS && xform->compress.level == 291 RTE_COMP_LEVEL_NONE) { 292 DRV_LOG(ERR, "Non-compressed block is not supported."); 293 return -ENOTSUP; 294 } 295 if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo != 296 RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS && 297 xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) { 298 DRV_LOG(ERR, "SHA is not supported."); 299 return -ENOTSUP; 300 } 301 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0, 302 priv->dev_config.socket_id); 303 if (xfrm == NULL) 304 return -ENOMEM; 305 xfrm->opcode = MLX5_OPCODE_MMO; 306 xfrm->type = xform->type; 307 switch (xform->type) { 308 case RTE_COMP_COMPRESS: 309 switch (xform->compress.algo) { 310 case RTE_COMP_ALGO_NULL: 311 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 312 WQE_CSEG_OPC_MOD_OFFSET; 313 break; 314 case RTE_COMP_ALGO_DEFLATE: 315 size = 1 << xform->compress.window_size; 316 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS; 317 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), 318 MLX5_COMP_MAX_WIN_SIZE_CONF) << 319 WQE_GGA_COMP_WIN_SIZE_OFFSET; 320 if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT) 321 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 322 else 323 size = priv->min_block_size - 1 + 324 xform->compress.level; 325 xfrm->gga_ctrl1 += RTE_MIN(size, 326 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) << 327 WQE_GGA_COMP_BLOCK_SIZE_OFFSET; 328 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << 329 WQE_CSEG_OPC_MOD_OFFSET; 330 size = xform->compress.deflate.huffman == 331 RTE_COMP_HUFFMAN_DYNAMIC ? 332 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX : 333 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN; 334 xfrm->gga_ctrl1 += size << 335 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET; 336 break; 337 default: 338 goto err; 339 } 340 xfrm->csum_type = xform->compress.chksum; 341 break; 342 case RTE_COMP_DECOMPRESS: 343 switch (xform->decompress.algo) { 344 case RTE_COMP_ALGO_NULL: 345 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 346 WQE_CSEG_OPC_MOD_OFFSET; 347 break; 348 case RTE_COMP_ALGO_DEFLATE: 349 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << 350 WQE_CSEG_OPC_MOD_OFFSET; 351 break; 352 default: 353 goto err; 354 } 355 xfrm->csum_type = xform->decompress.chksum; 356 break; 357 default: 358 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type); 359 goto err; 360 } 361 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum " 362 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type); 363 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1); 364 rte_spinlock_lock(&priv->xform_sl); 365 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next); 366 rte_spinlock_unlock(&priv->xform_sl); 367 *private_xform = xfrm; 368 return 0; 369 err: 370 rte_free(xfrm); 371 return -ENOTSUP; 372 } 373 374 static void 375 mlx5_compress_dev_stop(struct rte_compressdev *dev) 376 { 377 RTE_SET_USED(dev); 378 } 379 380 static int 381 mlx5_compress_dev_start(struct rte_compressdev *dev) 382 { 383 RTE_SET_USED(dev); 384 return 0; 385 } 386 387 static void 388 mlx5_compress_stats_get(struct rte_compressdev *dev, 389 struct rte_compressdev_stats *stats) 390 { 391 int qp_id; 392 393 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 394 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 395 396 stats->enqueued_count += qp->stats.enqueued_count; 397 stats->dequeued_count += qp->stats.dequeued_count; 398 stats->enqueue_err_count += qp->stats.enqueue_err_count; 399 stats->dequeue_err_count += qp->stats.dequeue_err_count; 400 } 401 } 402 403 static void 404 mlx5_compress_stats_reset(struct rte_compressdev *dev) 405 { 406 int qp_id; 407 408 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 409 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 410 411 memset(&qp->stats, 0, sizeof(qp->stats)); 412 } 413 } 414 415 static struct rte_compressdev_ops mlx5_compress_ops = { 416 .dev_configure = mlx5_compress_dev_configure, 417 .dev_start = mlx5_compress_dev_start, 418 .dev_stop = mlx5_compress_dev_stop, 419 .dev_close = mlx5_compress_dev_close, 420 .dev_infos_get = mlx5_compress_dev_info_get, 421 .stats_get = mlx5_compress_stats_get, 422 .stats_reset = mlx5_compress_stats_reset, 423 .queue_pair_setup = mlx5_compress_qp_setup, 424 .queue_pair_release = mlx5_compress_qp_release, 425 .private_xform_create = mlx5_compress_xform_create, 426 .private_xform_free = mlx5_compress_xform_free, 427 .stream_create = NULL, 428 .stream_free = NULL, 429 }; 430 431 static __rte_always_inline uint32_t 432 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, 433 volatile struct mlx5_wqe_dseg *restrict dseg, 434 struct rte_mbuf *restrict mbuf, 435 uint32_t offset, uint32_t len) 436 { 437 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 438 439 dseg->bcount = rte_cpu_to_be_32(len); 440 dseg->lkey = mlx5_mr_addr2mr_bh(qp->priv->pd, 0, &qp->priv->mr_scache, 441 &qp->mr_ctrl, addr, 442 !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); 443 dseg->pbuf = rte_cpu_to_be_64(addr); 444 return dseg->lkey; 445 } 446 447 /* 448 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 449 * 64bit architectures. 450 */ 451 static __rte_always_inline void 452 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv) 453 { 454 #ifdef RTE_ARCH_64 455 *priv->uar_addr = val; 456 #else /* !RTE_ARCH_64 */ 457 rte_spinlock_lock(&priv->uar32_sl); 458 *(volatile uint32_t *)priv->uar_addr = val; 459 rte_io_wmb(); 460 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; 461 rte_spinlock_unlock(&priv->uar32_sl); 462 #endif 463 } 464 465 static uint16_t 466 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, 467 uint16_t nb_ops) 468 { 469 struct mlx5_compress_qp *qp = queue_pair; 470 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 471 qp->sq.wqes, *wqe; 472 struct mlx5_compress_xform *xform; 473 struct rte_comp_op *op; 474 uint16_t mask = qp->entries_n - 1; 475 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 476 uint16_t idx; 477 bool invalid; 478 479 if (remain < nb_ops) 480 nb_ops = remain; 481 else 482 remain = nb_ops; 483 if (unlikely(remain == 0)) 484 return 0; 485 do { 486 idx = qp->pi & mask; 487 wqe = &wqes[idx]; 488 rte_prefetch0(&wqes[(qp->pi + 1) & mask]); 489 op = *ops++; 490 xform = op->private_xform; 491 /* 492 * Check operation arguments and error cases: 493 * - Operation type must be state-less. 494 * - Compress operation flush flag must be FULL or FINAL. 495 * - Source and destination buffers must be mapped internally. 496 */ 497 invalid = op->op_type != RTE_COMP_OP_STATELESS || 498 (xform->type == RTE_COMP_COMPRESS && 499 op->flush_flag < RTE_COMP_FLUSH_FULL); 500 if (unlikely(invalid || 501 (mlx5_compress_dseg_set(qp, &wqe->gather, 502 op->m_src, 503 op->src.offset, 504 op->src.length) == 505 UINT32_MAX) || 506 (mlx5_compress_dseg_set(qp, &wqe->scatter, 507 op->m_dst, 508 op->dst.offset, 509 rte_pktmbuf_pkt_len(op->m_dst) - 510 op->dst.offset) == 511 UINT32_MAX))) { 512 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS : 513 RTE_COMP_OP_STATUS_ERROR; 514 nb_ops -= remain; 515 if (unlikely(nb_ops == 0)) 516 return 0; 517 break; 518 } 519 wqe->gga_ctrl1 = xform->gga_ctrl1; 520 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8)); 521 qp->ops[idx] = op; 522 qp->pi++; 523 } while (--remain); 524 qp->stats.enqueued_count += nb_ops; 525 rte_io_wmb(); 526 qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); 527 rte_wmb(); 528 mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv); 529 rte_wmb(); 530 return nb_ops; 531 } 532 533 static void 534 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, 535 volatile uint32_t *opaq) 536 { 537 size_t i; 538 539 DRV_LOG(ERR, "Error cqe:"); 540 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4) 541 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], 542 cqe[i + 2], cqe[i + 3]); 543 DRV_LOG(ERR, "\nError wqe:"); 544 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4) 545 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1], 546 wqe[i + 2], wqe[i + 3]); 547 DRV_LOG(ERR, "\nError opaq:"); 548 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4) 549 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1], 550 opaq[i + 2], opaq[i + 3]); 551 } 552 553 static void 554 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, 555 struct rte_comp_op *op) 556 { 557 const uint32_t idx = qp->ci & (qp->entries_n - 1); 558 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 559 &qp->cq.cqes[idx]; 560 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 561 qp->sq.wqes; 562 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 563 564 op->status = RTE_COMP_OP_STATUS_ERROR; 565 op->consumed = 0; 566 op->produced = 0; 567 op->output_chksum = 0; 568 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) | 569 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32); 570 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe, 571 (volatile uint32_t *)&wqes[idx], 572 (volatile uint32_t *)&opaq[idx]); 573 qp->stats.dequeue_err_count++; 574 } 575 576 static uint16_t 577 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, 578 uint16_t nb_ops) 579 { 580 struct mlx5_compress_qp *qp = queue_pair; 581 volatile struct mlx5_compress_xform *restrict xform; 582 volatile struct mlx5_cqe *restrict cqe; 583 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 584 struct rte_comp_op *restrict op; 585 const unsigned int cq_size = qp->entries_n; 586 const unsigned int mask = cq_size - 1; 587 uint32_t idx; 588 uint32_t next_idx = qp->ci & mask; 589 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 590 uint16_t i = 0; 591 int ret; 592 593 if (unlikely(max == 0)) 594 return 0; 595 do { 596 idx = next_idx; 597 next_idx = (qp->ci + 1) & mask; 598 rte_prefetch0(&qp->cq.cqes[next_idx]); 599 rte_prefetch0(qp->ops[next_idx]); 600 op = qp->ops[idx]; 601 cqe = &qp->cq.cqes[idx]; 602 ret = check_cqe(cqe, cq_size, qp->ci); 603 /* 604 * Be sure owner read is done before any other cookie field or 605 * opaque field. 606 */ 607 rte_io_rmb(); 608 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 609 if (likely(ret == MLX5_CQE_STATUS_HW_OWN)) 610 break; 611 mlx5_compress_cqe_err_handle(qp, op); 612 } else { 613 xform = op->private_xform; 614 op->status = RTE_COMP_OP_STATUS_SUCCESS; 615 op->consumed = op->src.length; 616 op->produced = rte_be_to_cpu_32(cqe->byte_cnt); 617 MLX5_ASSERT(cqe->byte_cnt == 618 opaq[idx].scattered_length); 619 switch (xform->csum_type) { 620 case RTE_COMP_CHECKSUM_CRC32: 621 op->output_chksum = (uint64_t)rte_be_to_cpu_32 622 (opaq[idx].crc32); 623 break; 624 case RTE_COMP_CHECKSUM_ADLER32: 625 op->output_chksum = (uint64_t)rte_be_to_cpu_32 626 (opaq[idx].adler32) << 32; 627 break; 628 case RTE_COMP_CHECKSUM_CRC32_ADLER32: 629 op->output_chksum = (uint64_t)rte_be_to_cpu_32 630 (opaq[idx].crc32) | 631 ((uint64_t)rte_be_to_cpu_32 632 (opaq[idx].adler32) << 32); 633 break; 634 default: 635 break; 636 } 637 } 638 ops[i++] = op; 639 qp->ci++; 640 } while (i < max); 641 if (likely(i != 0)) { 642 rte_io_wmb(); 643 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci); 644 qp->stats.dequeued_count += i; 645 } 646 return i; 647 } 648 649 static void 650 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv) 651 { 652 if (priv->pd != NULL) { 653 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 654 priv->pd = NULL; 655 } 656 if (priv->uar != NULL) { 657 mlx5_glue->devx_free_uar(priv->uar); 658 priv->uar = NULL; 659 } 660 } 661 662 static int 663 mlx5_compress_pd_create(struct mlx5_compress_priv *priv) 664 { 665 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 666 struct mlx5dv_obj obj; 667 struct mlx5dv_pd pd_info; 668 int ret; 669 670 priv->pd = mlx5_glue->alloc_pd(priv->ctx); 671 if (priv->pd == NULL) { 672 DRV_LOG(ERR, "Failed to allocate PD."); 673 return errno ? -errno : -ENOMEM; 674 } 675 obj.pd.in = priv->pd; 676 obj.pd.out = &pd_info; 677 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 678 if (ret != 0) { 679 DRV_LOG(ERR, "Fail to get PD object info."); 680 mlx5_glue->dealloc_pd(priv->pd); 681 priv->pd = NULL; 682 return -errno; 683 } 684 priv->pdn = pd_info.pdn; 685 return 0; 686 #else 687 (void)priv; 688 DRV_LOG(ERR, "Cannot get pdn - no DV support."); 689 return -ENOTSUP; 690 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 691 } 692 693 static int 694 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv) 695 { 696 if (mlx5_compress_pd_create(priv) != 0) 697 return -1; 698 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1); 699 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) == 700 NULL) { 701 rte_errno = errno; 702 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 703 DRV_LOG(ERR, "Failed to allocate UAR."); 704 return -1; 705 } 706 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); 707 MLX5_ASSERT(priv->uar_addr); 708 #ifndef RTE_ARCH_64 709 rte_spinlock_init(&priv->uar32_sl); 710 #endif /* RTE_ARCH_64 */ 711 return 0; 712 } 713 714 /** 715 * DPDK callback to register a PCI device. 716 * 717 * This function spawns compress device out of a given PCI device. 718 * 719 * @param[in] pci_drv 720 * PCI driver structure (mlx5_compress_driver). 721 * @param[in] pci_dev 722 * PCI device information. 723 * 724 * @return 725 * 0 on success, 1 to skip this driver, a negative errno value otherwise 726 * and rte_errno is set. 727 */ 728 static int 729 mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, 730 struct rte_pci_device *pci_dev) 731 { 732 struct ibv_device *ibv; 733 struct rte_compressdev *cdev; 734 struct ibv_context *ctx; 735 struct mlx5_compress_priv *priv; 736 struct mlx5_hca_attr att = { 0 }; 737 struct rte_compressdev_pmd_init_params init_params = { 738 .name = "", 739 .socket_id = pci_dev->device.numa_node, 740 }; 741 742 RTE_SET_USED(pci_drv); 743 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 744 DRV_LOG(ERR, "Non-primary process type is not supported."); 745 rte_errno = ENOTSUP; 746 return -rte_errno; 747 } 748 ibv = mlx5_os_get_ibv_device(&pci_dev->addr); 749 if (ibv == NULL) { 750 DRV_LOG(ERR, "No matching IB device for PCI slot " 751 PCI_PRI_FMT ".", pci_dev->addr.domain, 752 pci_dev->addr.bus, pci_dev->addr.devid, 753 pci_dev->addr.function); 754 return -rte_errno; 755 } 756 DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name); 757 ctx = mlx5_glue->dv_open_device(ibv); 758 if (ctx == NULL) { 759 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); 760 rte_errno = ENODEV; 761 return -rte_errno; 762 } 763 if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 || 764 att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 || 765 att.mmo_dma_en == 0) { 766 DRV_LOG(ERR, "Not enough capabilities to support compress " 767 "operations, maybe old FW/OFED version?"); 768 claim_zero(mlx5_glue->close_device(ctx)); 769 rte_errno = ENOTSUP; 770 return -ENOTSUP; 771 } 772 cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device, 773 sizeof(*priv), &init_params); 774 if (cdev == NULL) { 775 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); 776 claim_zero(mlx5_glue->close_device(ctx)); 777 return -ENODEV; 778 } 779 DRV_LOG(INFO, 780 "Compress device %s was created successfully.", ibv->name); 781 cdev->dev_ops = &mlx5_compress_ops; 782 cdev->dequeue_burst = mlx5_compress_dequeue_burst; 783 cdev->enqueue_burst = mlx5_compress_enqueue_burst; 784 cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 785 priv = cdev->data->dev_private; 786 priv->ctx = ctx; 787 priv->pci_dev = pci_dev; 788 priv->cdev = cdev; 789 priv->min_block_size = att.compress_min_block_size; 790 priv->sq_ts_format = att.sq_ts_format; 791 if (mlx5_compress_hw_global_prepare(priv) != 0) { 792 rte_compressdev_pmd_destroy(priv->cdev); 793 claim_zero(mlx5_glue->close_device(priv->ctx)); 794 return -1; 795 } 796 if (mlx5_mr_btree_init(&priv->mr_scache.cache, 797 MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) { 798 DRV_LOG(ERR, "Failed to allocate shared cache MR memory."); 799 mlx5_compress_hw_global_release(priv); 800 rte_compressdev_pmd_destroy(priv->cdev); 801 claim_zero(mlx5_glue->close_device(priv->ctx)); 802 rte_errno = ENOMEM; 803 return -rte_errno; 804 } 805 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; 806 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; 807 pthread_mutex_lock(&priv_list_lock); 808 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next); 809 pthread_mutex_unlock(&priv_list_lock); 810 return 0; 811 } 812 813 /** 814 * DPDK callback to remove a PCI device. 815 * 816 * This function removes all compress devices belong to a given PCI device. 817 * 818 * @param[in] pci_dev 819 * Pointer to the PCI device. 820 * 821 * @return 822 * 0 on success, the function cannot fail. 823 */ 824 static int 825 mlx5_compress_pci_remove(struct rte_pci_device *pdev) 826 { 827 struct mlx5_compress_priv *priv = NULL; 828 829 pthread_mutex_lock(&priv_list_lock); 830 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 831 if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0) 832 break; 833 if (priv) 834 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); 835 pthread_mutex_unlock(&priv_list_lock); 836 if (priv) { 837 mlx5_mr_release_cache(&priv->mr_scache); 838 mlx5_compress_hw_global_release(priv); 839 rte_compressdev_pmd_destroy(priv->cdev); 840 claim_zero(mlx5_glue->close_device(priv->ctx)); 841 } 842 return 0; 843 } 844 845 static const struct rte_pci_id mlx5_compress_pci_id_map[] = { 846 { 847 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 848 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 849 }, 850 { 851 .vendor_id = 0 852 } 853 }; 854 855 static struct mlx5_pci_driver mlx5_compress_driver = { 856 .driver_class = MLX5_CLASS_COMPRESS, 857 .pci_driver = { 858 .driver = { 859 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), 860 }, 861 .id_table = mlx5_compress_pci_id_map, 862 .probe = mlx5_compress_pci_probe, 863 .remove = mlx5_compress_pci_remove, 864 .drv_flags = 0, 865 }, 866 }; 867 868 RTE_INIT(rte_mlx5_compress_init) 869 { 870 mlx5_common_init(); 871 if (mlx5_glue != NULL) 872 mlx5_pci_driver_register(&mlx5_compress_driver); 873 } 874 875 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) 876 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__); 877 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map); 878 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 879