1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <bus_pci_driver.h> 9 #include <rte_spinlock.h> 10 #include <rte_comp.h> 11 #include <rte_compressdev.h> 12 #include <rte_compressdev_pmd.h> 13 14 #include <mlx5_glue.h> 15 #include <mlx5_common.h> 16 #include <mlx5_devx_cmds.h> 17 #include <mlx5_common_os.h> 18 #include <mlx5_common_devx.h> 19 #include <mlx5_common_mr.h> 20 #include <mlx5_prm.h> 21 22 #include "mlx5_compress_utils.h" 23 24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress 25 #define MLX5_COMPRESS_MAX_QPS 1024 26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u 27 28 struct mlx5_compress_devarg_params { 29 uint32_t log_block_sz; 30 }; 31 32 struct mlx5_compress_xform { 33 LIST_ENTRY(mlx5_compress_xform) next; 34 enum rte_comp_xform_type type; 35 enum rte_comp_checksum_type csum_type; 36 uint32_t opcode; 37 uint32_t gga_ctrl1; /* BE. */ 38 }; 39 40 struct mlx5_compress_priv { 41 TAILQ_ENTRY(mlx5_compress_priv) next; 42 struct rte_compressdev *compressdev; 43 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 44 struct mlx5_uar uar; 45 uint8_t min_block_size; 46 /* Minimum huffman block size supported by the device. */ 47 struct rte_compressdev_config dev_config; 48 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; 49 rte_spinlock_t xform_sl; 50 /* HCA caps */ 51 uint32_t mmo_decomp_sq:1; 52 uint32_t mmo_decomp_qp:1; 53 uint32_t mmo_comp_sq:1; 54 uint32_t mmo_comp_qp:1; 55 uint32_t mmo_dma_sq:1; 56 uint32_t mmo_dma_qp:1; 57 uint32_t log_block_sz; 58 uint32_t crc32_opaq_offs; 59 }; 60 61 struct mlx5_compress_qp { 62 uint16_t qp_id; 63 uint16_t entries_n; 64 uint16_t pi; 65 uint16_t ci; 66 struct mlx5_mr_ctrl mr_ctrl; 67 int socket_id; 68 struct mlx5_devx_cq cq; 69 struct mlx5_devx_qp qp; 70 struct mlx5_pmd_mr opaque_mr; 71 struct rte_comp_op **ops; 72 struct mlx5_compress_priv *priv; 73 struct rte_compressdev_stats stats; 74 }; 75 76 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list = 77 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list); 78 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 79 80 int mlx5_compress_logtype; 81 82 static const struct rte_compressdev_capabilities mlx5_caps[] = { 83 { 84 .algo = RTE_COMP_ALGO_NULL, 85 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 86 RTE_COMP_FF_CRC32_CHECKSUM | 87 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 88 RTE_COMP_FF_SHAREABLE_PRIV_XFORM, 89 }, 90 { 91 .algo = RTE_COMP_ALGO_DEFLATE, 92 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 93 RTE_COMP_FF_CRC32_CHECKSUM | 94 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 95 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 96 RTE_COMP_FF_HUFFMAN_FIXED | 97 RTE_COMP_FF_HUFFMAN_DYNAMIC, 98 .window_size = {.min = 10, .max = 15, .increment = 1}, 99 }, 100 RTE_COMP_END_OF_CAPABILITIES_LIST() 101 }; 102 103 static void 104 mlx5_compress_dev_info_get(struct rte_compressdev *dev, 105 struct rte_compressdev_info *info) 106 { 107 RTE_SET_USED(dev); 108 if (info != NULL) { 109 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS; 110 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 111 info->capabilities = mlx5_caps; 112 } 113 } 114 115 static int 116 mlx5_compress_dev_configure(struct rte_compressdev *dev, 117 struct rte_compressdev_config *config) 118 { 119 struct mlx5_compress_priv *priv; 120 121 if (dev == NULL || config == NULL) 122 return -EINVAL; 123 priv = dev->data->dev_private; 124 priv->dev_config = *config; 125 return 0; 126 } 127 128 static int 129 mlx5_compress_dev_close(struct rte_compressdev *dev) 130 { 131 RTE_SET_USED(dev); 132 return 0; 133 } 134 135 static int 136 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) 137 { 138 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 139 140 if (qp->qp.qp != NULL) 141 mlx5_devx_qp_destroy(&qp->qp); 142 if (qp->cq.cq != NULL) 143 mlx5_devx_cq_destroy(&qp->cq); 144 if (qp->opaque_mr.obj != NULL) { 145 void *opaq = qp->opaque_mr.addr; 146 147 mlx5_common_verbs_dereg_mr(&qp->opaque_mr); 148 rte_free(opaq); 149 } 150 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 151 rte_free(qp); 152 dev->data->queue_pairs[qp_id] = NULL; 153 return 0; 154 } 155 156 static void 157 mlx5_compress_init_qp(struct mlx5_compress_qp *qp) 158 { 159 volatile struct mlx5_gga_wqe *restrict wqe = 160 (volatile struct mlx5_gga_wqe *)qp->qp.wqes; 161 volatile union mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 162 const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u); 163 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << 164 MLX5_COMP_MODE_OFFSET); 165 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey); 166 int i; 167 168 /* All the next fields state should stay constant. */ 169 for (i = 0; i < qp->entries_n; ++i, ++wqe) { 170 wqe->sq_ds = sq_ds; 171 wqe->flags = flags; 172 wqe->opaque_lkey = opaq_lkey; 173 wqe->opaque_vaddr = rte_cpu_to_be_64 174 ((uint64_t)(uintptr_t)&opaq[i]); 175 } 176 } 177 178 static int 179 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, 180 uint32_t max_inflight_ops, int socket_id) 181 { 182 struct mlx5_compress_priv *priv = dev->data->dev_private; 183 struct mlx5_compress_qp *qp; 184 struct mlx5_devx_cq_attr cq_attr = { 185 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj), 186 }; 187 struct mlx5_devx_qp_attr qp_attr = { 188 .pd = priv->cdev->pdn, 189 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj), 190 .user_index = qp_id, 191 }; 192 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); 193 uint32_t alloc_size = sizeof(*qp); 194 void *opaq_buf; 195 int ret; 196 197 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 198 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n); 199 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 200 socket_id); 201 if (qp == NULL) { 202 DRV_LOG(ERR, "Failed to allocate qp memory."); 203 rte_errno = ENOMEM; 204 return -rte_errno; 205 } 206 dev->data->queue_pairs[qp_id] = qp; 207 if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen, 208 priv->dev_config.socket_id)) { 209 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 210 (uint32_t)qp_id); 211 rte_errno = ENOMEM; 212 goto err; 213 } 214 opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n, 215 sizeof(union mlx5_gga_compress_opaque), 216 sizeof(union mlx5_gga_compress_opaque)); 217 if (opaq_buf == NULL) { 218 DRV_LOG(ERR, "Failed to allocate opaque memory."); 219 rte_errno = ENOMEM; 220 goto err; 221 } 222 qp->entries_n = 1 << log_ops_n; 223 qp->socket_id = socket_id; 224 qp->qp_id = qp_id; 225 qp->priv = priv; 226 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), 227 RTE_CACHE_LINE_SIZE); 228 if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n * 229 sizeof(union mlx5_gga_compress_opaque), 230 &qp->opaque_mr) != 0) { 231 rte_free(opaq_buf); 232 DRV_LOG(ERR, "Failed to register opaque MR."); 233 rte_errno = ENOMEM; 234 goto err; 235 } 236 ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr, 237 socket_id); 238 if (ret != 0) { 239 DRV_LOG(ERR, "Failed to create CQ."); 240 goto err; 241 } 242 qp_attr.cqn = qp->cq.cq->id; 243 qp_attr.ts_format = 244 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); 245 qp_attr.num_of_receive_wqes = 0; 246 qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n); 247 qp_attr.mmo = priv->mmo_decomp_qp || priv->mmo_comp_qp || 248 priv->mmo_dma_qp; 249 ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, 250 qp_attr.num_of_send_wqbbs * 251 MLX5_WQE_SIZE, &qp_attr, socket_id); 252 if (ret != 0) { 253 DRV_LOG(ERR, "Failed to create QP."); 254 goto err; 255 } 256 mlx5_compress_init_qp(qp); 257 ret = mlx5_devx_qp2rts(&qp->qp, 0); 258 if (ret) 259 goto err; 260 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", 261 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n); 262 return 0; 263 err: 264 mlx5_compress_qp_release(dev, qp_id); 265 return -1; 266 } 267 268 static int 269 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform) 270 { 271 struct mlx5_compress_priv *priv = dev->data->dev_private; 272 273 rte_spinlock_lock(&priv->xform_sl); 274 LIST_REMOVE((struct mlx5_compress_xform *)xform, next); 275 rte_spinlock_unlock(&priv->xform_sl); 276 rte_free(xform); 277 return 0; 278 } 279 280 static int 281 mlx5_compress_xform_create(struct rte_compressdev *dev, 282 const struct rte_comp_xform *xform, 283 void **private_xform) 284 { 285 struct mlx5_compress_priv *priv = dev->data->dev_private; 286 struct mlx5_compress_xform *xfrm; 287 uint32_t size; 288 289 switch (xform->type) { 290 case RTE_COMP_COMPRESS: 291 if (xform->compress.algo == RTE_COMP_ALGO_NULL && 292 !priv->mmo_dma_qp && !priv->mmo_dma_sq) { 293 DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); 294 return -ENOTSUP; 295 } else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) { 296 DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?"); 297 return -ENOTSUP; 298 } 299 if (xform->compress.level == RTE_COMP_LEVEL_NONE) { 300 DRV_LOG(ERR, "Non-compressed block is not supported."); 301 return -ENOTSUP; 302 } 303 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { 304 DRV_LOG(ERR, "SHA is not supported."); 305 return -ENOTSUP; 306 } 307 break; 308 case RTE_COMP_DECOMPRESS: 309 if (xform->decompress.algo == RTE_COMP_ALGO_NULL && 310 !priv->mmo_dma_qp && !priv->mmo_dma_sq) { 311 DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); 312 return -ENOTSUP; 313 } else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) { 314 DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?"); 315 return -ENOTSUP; 316 } 317 if (xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { 318 DRV_LOG(ERR, "SHA is not supported."); 319 return -ENOTSUP; 320 } 321 break; 322 default: 323 DRV_LOG(ERR, "Xform type should be compress/decompress"); 324 return -ENOTSUP; 325 } 326 327 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0, 328 priv->dev_config.socket_id); 329 if (xfrm == NULL) 330 return -ENOMEM; 331 xfrm->opcode = MLX5_OPCODE_MMO; 332 xfrm->type = xform->type; 333 switch (xform->type) { 334 case RTE_COMP_COMPRESS: 335 switch (xform->compress.algo) { 336 case RTE_COMP_ALGO_NULL: 337 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 338 WQE_CSEG_OPC_MOD_OFFSET; 339 break; 340 case RTE_COMP_ALGO_DEFLATE: 341 size = 1 << xform->compress.window_size; 342 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS; 343 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), 344 MLX5_COMP_MAX_WIN_SIZE_CONF) << 345 WQE_GGA_COMP_WIN_SIZE_OFFSET; 346 size = priv->log_block_sz; 347 xfrm->gga_ctrl1 += size << 348 WQE_GGA_COMP_BLOCK_SIZE_OFFSET; 349 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << 350 WQE_CSEG_OPC_MOD_OFFSET; 351 size = xform->compress.deflate.huffman == 352 RTE_COMP_HUFFMAN_DYNAMIC ? 353 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX : 354 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN; 355 xfrm->gga_ctrl1 += size << 356 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET; 357 break; 358 default: 359 goto err; 360 } 361 xfrm->csum_type = xform->compress.chksum; 362 break; 363 case RTE_COMP_DECOMPRESS: 364 switch (xform->decompress.algo) { 365 case RTE_COMP_ALGO_NULL: 366 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 367 WQE_CSEG_OPC_MOD_OFFSET; 368 break; 369 case RTE_COMP_ALGO_DEFLATE: 370 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << 371 WQE_CSEG_OPC_MOD_OFFSET; 372 break; 373 default: 374 goto err; 375 } 376 xfrm->csum_type = xform->decompress.chksum; 377 break; 378 default: 379 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type); 380 goto err; 381 } 382 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum " 383 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type); 384 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1); 385 rte_spinlock_lock(&priv->xform_sl); 386 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next); 387 rte_spinlock_unlock(&priv->xform_sl); 388 *private_xform = xfrm; 389 return 0; 390 err: 391 rte_free(xfrm); 392 return -ENOTSUP; 393 } 394 395 static void 396 mlx5_compress_dev_stop(struct rte_compressdev *dev) 397 { 398 RTE_SET_USED(dev); 399 } 400 401 static int 402 mlx5_compress_dev_start(struct rte_compressdev *dev) 403 { 404 struct mlx5_compress_priv *priv = dev->data->dev_private; 405 406 return mlx5_dev_mempool_subscribe(priv->cdev); 407 } 408 409 static void 410 mlx5_compress_stats_get(struct rte_compressdev *dev, 411 struct rte_compressdev_stats *stats) 412 { 413 int qp_id; 414 415 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 416 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 417 418 stats->enqueued_count += qp->stats.enqueued_count; 419 stats->dequeued_count += qp->stats.dequeued_count; 420 stats->enqueue_err_count += qp->stats.enqueue_err_count; 421 stats->dequeue_err_count += qp->stats.dequeue_err_count; 422 } 423 } 424 425 static void 426 mlx5_compress_stats_reset(struct rte_compressdev *dev) 427 { 428 int qp_id; 429 430 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 431 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 432 433 memset(&qp->stats, 0, sizeof(qp->stats)); 434 } 435 } 436 437 static struct rte_compressdev_ops mlx5_compress_ops = { 438 .dev_configure = mlx5_compress_dev_configure, 439 .dev_start = mlx5_compress_dev_start, 440 .dev_stop = mlx5_compress_dev_stop, 441 .dev_close = mlx5_compress_dev_close, 442 .dev_infos_get = mlx5_compress_dev_info_get, 443 .stats_get = mlx5_compress_stats_get, 444 .stats_reset = mlx5_compress_stats_reset, 445 .queue_pair_setup = mlx5_compress_qp_setup, 446 .queue_pair_release = mlx5_compress_qp_release, 447 .private_xform_create = mlx5_compress_xform_create, 448 .private_xform_free = mlx5_compress_xform_free, 449 .stream_create = NULL, 450 .stream_free = NULL, 451 }; 452 453 static __rte_always_inline uint32_t 454 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, 455 volatile struct mlx5_wqe_dseg *restrict dseg, 456 struct rte_mbuf *restrict mbuf, 457 uint32_t offset, uint32_t len) 458 { 459 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 460 461 dseg->bcount = rte_cpu_to_be_32(len); 462 dseg->lkey = mlx5_mr_mb2mr(&qp->mr_ctrl, mbuf); 463 dseg->pbuf = rte_cpu_to_be_64(addr); 464 return dseg->lkey; 465 } 466 467 static uint16_t 468 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, 469 uint16_t nb_ops) 470 { 471 struct mlx5_compress_qp *qp = queue_pair; 472 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 473 qp->qp.wqes, *wqe; 474 struct mlx5_compress_xform *xform; 475 struct rte_comp_op *op; 476 uint16_t mask = qp->entries_n - 1; 477 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 478 uint16_t idx; 479 bool invalid; 480 481 if (remain < nb_ops) 482 nb_ops = remain; 483 else 484 remain = nb_ops; 485 if (unlikely(remain == 0)) 486 return 0; 487 do { 488 idx = qp->pi & mask; 489 wqe = &wqes[idx]; 490 rte_prefetch0(&wqes[(qp->pi + 1) & mask]); 491 op = *ops++; 492 xform = op->private_xform; 493 /* 494 * Check operation arguments and error cases: 495 * - Operation type must be state-less. 496 * - Compress operation flush flag must be FULL or FINAL. 497 * - Source and destination buffers must be mapped internally. 498 */ 499 invalid = op->op_type != RTE_COMP_OP_STATELESS || 500 (xform->type == RTE_COMP_COMPRESS && 501 op->flush_flag < RTE_COMP_FLUSH_FULL); 502 if (unlikely(invalid || 503 (mlx5_compress_dseg_set(qp, &wqe->gather, 504 op->m_src, 505 op->src.offset, 506 op->src.length) == 507 UINT32_MAX) || 508 (mlx5_compress_dseg_set(qp, &wqe->scatter, 509 op->m_dst, 510 op->dst.offset, 511 rte_pktmbuf_pkt_len(op->m_dst) - 512 op->dst.offset) == 513 UINT32_MAX))) { 514 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS : 515 RTE_COMP_OP_STATUS_ERROR; 516 nb_ops -= remain; 517 if (unlikely(nb_ops == 0)) 518 return 0; 519 break; 520 } 521 wqe->gga_ctrl1 = xform->gga_ctrl1; 522 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8)); 523 qp->ops[idx] = op; 524 qp->pi++; 525 } while (--remain); 526 qp->stats.enqueued_count += nb_ops; 527 mlx5_doorbell_ring(&qp->priv->uar.bf_db, *(volatile uint64_t *)wqe, 528 qp->pi, &qp->qp.db_rec[MLX5_SND_DBR], 529 !qp->priv->uar.dbnc); 530 return nb_ops; 531 } 532 533 static void 534 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, 535 volatile uint32_t *opaq) 536 { 537 size_t i; 538 539 DRV_LOG(ERR, "Error cqe:"); 540 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4) 541 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], 542 cqe[i + 2], cqe[i + 3]); 543 DRV_LOG(ERR, "\nError wqe:"); 544 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4) 545 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1], 546 wqe[i + 2], wqe[i + 3]); 547 DRV_LOG(ERR, "\nError opaq:"); 548 for (i = 0; i < sizeof(union mlx5_gga_compress_opaque) >> 2; i += 4) 549 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1], 550 opaq[i + 2], opaq[i + 3]); 551 } 552 553 static void 554 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, 555 struct rte_comp_op *op) 556 { 557 const uint32_t idx = qp->ci & (qp->entries_n - 1); 558 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 559 &qp->cq.cqes[idx]; 560 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 561 qp->qp.wqes; 562 volatile union mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 563 564 volatile uint32_t *synd_word = RTE_PTR_ADD(cqe, MLX5_ERROR_CQE_SYNDROME_OFFSET); 565 switch (*synd_word) { 566 case MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE: 567 op->status = RTE_COMP_OP_STATUS_OUT_OF_SPACE_TERMINATED; 568 DRV_LOG(DEBUG, "OUT OF SPACE error, output is bigger than dst buffer."); 569 break; 570 case MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE: 571 DRV_LOG(DEBUG, "The last compressed block missed the B-final flag; maybe the compressed data is not complete or garbaged?"); 572 /* fallthrough */ 573 default: 574 op->status = RTE_COMP_OP_STATUS_ERROR; 575 } 576 op->consumed = 0; 577 op->produced = 0; 578 op->output_chksum = 0; 579 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrome) | 580 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32); 581 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe, 582 (volatile uint32_t *)&wqes[idx], 583 (volatile uint32_t *)&opaq[idx]); 584 qp->stats.dequeue_err_count++; 585 } 586 587 static uint16_t 588 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, 589 uint16_t nb_ops) 590 { 591 struct mlx5_compress_qp *qp = queue_pair; 592 volatile struct mlx5_compress_xform *restrict xform; 593 volatile struct mlx5_cqe *restrict cqe; 594 volatile union mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 595 struct rte_comp_op *restrict op; 596 const unsigned int cq_size = qp->entries_n; 597 const unsigned int mask = cq_size - 1; 598 uint32_t idx; 599 uint32_t next_idx = qp->ci & mask; 600 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 601 uint32_t crc32_idx = qp->priv->crc32_opaq_offs; 602 uint16_t i = 0; 603 int ret; 604 605 if (unlikely(max == 0)) 606 return 0; 607 do { 608 idx = next_idx; 609 next_idx = (qp->ci + 1) & mask; 610 rte_prefetch0(&qp->cq.cqes[next_idx]); 611 rte_prefetch0(qp->ops[next_idx]); 612 op = qp->ops[idx]; 613 cqe = &qp->cq.cqes[idx]; 614 ret = check_cqe(cqe, cq_size, qp->ci); 615 /* 616 * Be sure owner read is done before any other cookie field or 617 * opaque field. 618 */ 619 rte_io_rmb(); 620 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 621 if (likely(ret == MLX5_CQE_STATUS_HW_OWN)) 622 break; 623 mlx5_compress_cqe_err_handle(qp, op); 624 } else { 625 xform = op->private_xform; 626 op->status = RTE_COMP_OP_STATUS_SUCCESS; 627 op->consumed = op->src.length; 628 op->produced = rte_be_to_cpu_32(cqe->byte_cnt); 629 MLX5_ASSERT(cqe->byte_cnt == 630 opaq[idx].scattered_length); 631 switch (xform->csum_type) { 632 case RTE_COMP_CHECKSUM_CRC32: 633 op->output_chksum = (uint64_t)rte_be_to_cpu_32 634 (opaq[idx].data[crc32_idx]); 635 break; 636 case RTE_COMP_CHECKSUM_ADLER32: 637 op->output_chksum = (uint64_t)rte_be_to_cpu_32 638 (opaq[idx].data[crc32_idx + 1]); 639 break; 640 case RTE_COMP_CHECKSUM_CRC32_ADLER32: 641 op->output_chksum = (uint64_t)rte_be_to_cpu_32 642 (opaq[idx].data[crc32_idx]) | 643 ((uint64_t)rte_be_to_cpu_32 644 (opaq[idx].data[crc32_idx + 1]) << 32); 645 break; 646 default: 647 break; 648 } 649 } 650 ops[i++] = op; 651 qp->ci++; 652 } while (i < max); 653 if (likely(i != 0)) { 654 rte_io_wmb(); 655 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci); 656 qp->stats.dequeued_count += i; 657 } 658 return i; 659 } 660 661 static int 662 mlx5_compress_args_check_handler(const char *key, const char *val, void *opaque) 663 { 664 struct mlx5_compress_devarg_params *devarg_prms = opaque; 665 666 if (strcmp(key, "log-block-size") == 0) { 667 errno = 0; 668 devarg_prms->log_block_sz = (uint32_t)strtoul(val, NULL, 10); 669 if (errno) { 670 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", 671 key, val); 672 return -errno; 673 } 674 } 675 return 0; 676 } 677 678 static int 679 mlx5_compress_handle_devargs(struct mlx5_kvargs_ctrl *mkvlist, 680 struct mlx5_compress_devarg_params *devarg_prms, 681 struct mlx5_hca_attr *att) 682 { 683 const char **params = (const char *[]){ 684 "log-block-size", 685 NULL, 686 }; 687 688 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 689 if (mkvlist == NULL) 690 return 0; 691 if (mlx5_kvargs_process(mkvlist, params, 692 mlx5_compress_args_check_handler, 693 devarg_prms) != 0) { 694 DRV_LOG(ERR, "Devargs handler function Failed."); 695 rte_errno = EINVAL; 696 return -1; 697 } 698 if (devarg_prms->log_block_sz > MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX || 699 devarg_prms->log_block_sz < att->compress_min_block_size) { 700 DRV_LOG(WARNING, "Log block size provided is out of range(" 701 "%u); default it to %u.", 702 devarg_prms->log_block_sz, 703 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX); 704 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 705 } 706 return 0; 707 } 708 709 static int 710 mlx5_compress_dev_probe(struct mlx5_common_device *cdev, 711 struct mlx5_kvargs_ctrl *mkvlist) 712 { 713 struct rte_compressdev *compressdev; 714 struct mlx5_compress_priv *priv; 715 struct mlx5_hca_attr *attr = &cdev->config.hca_attr; 716 struct mlx5_compress_devarg_params devarg_prms = {0}; 717 struct rte_compressdev_pmd_init_params init_params = { 718 .name = "", 719 .socket_id = cdev->dev->numa_node, 720 }; 721 const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 722 uint32_t crc32_opaq_offset; 723 724 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 725 DRV_LOG(ERR, "Non-primary process type is not supported."); 726 rte_errno = ENOTSUP; 727 return -rte_errno; 728 } 729 if (!attr->decomp_deflate_v1_en && !attr->decomp_deflate_v2_en && 730 !attr->mmo_decompress_sq_en && !attr->mmo_compress_qp_en && 731 !attr->mmo_compress_sq_en && !attr->mmo_dma_qp_en && 732 !attr->mmo_dma_sq_en) { 733 DRV_LOG(ERR, "Not enough capabilities to support compress operations, maybe old FW/OFED version?"); 734 rte_errno = ENOTSUP; 735 return -ENOTSUP; 736 } 737 mlx5_compress_handle_devargs(mkvlist, &devarg_prms, attr); 738 compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev, 739 sizeof(*priv), &init_params); 740 if (compressdev == NULL) { 741 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name); 742 return -ENODEV; 743 } 744 DRV_LOG(INFO, 745 "Compress device %s was created successfully.", ibdev_name); 746 compressdev->dev_ops = &mlx5_compress_ops; 747 compressdev->dequeue_burst = mlx5_compress_dequeue_burst; 748 compressdev->enqueue_burst = mlx5_compress_enqueue_burst; 749 compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 750 priv = compressdev->data->dev_private; 751 priv->log_block_sz = devarg_prms.log_block_sz; 752 priv->mmo_decomp_sq = attr->mmo_decompress_sq_en; 753 priv->mmo_decomp_qp = 754 attr->decomp_deflate_v1_en | attr->decomp_deflate_v2_en; 755 priv->mmo_comp_sq = attr->mmo_compress_sq_en; 756 priv->mmo_comp_qp = attr->mmo_compress_qp_en; 757 priv->mmo_dma_sq = attr->mmo_dma_sq_en; 758 priv->mmo_dma_qp = attr->mmo_dma_qp_en; 759 if (attr->decomp_deflate_v2_en) 760 crc32_opaq_offset = offsetof(union mlx5_gga_compress_opaque, 761 v2.crc32); 762 else 763 crc32_opaq_offset = offsetof(union mlx5_gga_compress_opaque, 764 v1.crc32); 765 MLX5_ASSERT((crc32_opaq_offset % 4) == 0); 766 priv->crc32_opaq_offs = crc32_opaq_offset / 4; 767 priv->cdev = cdev; 768 priv->compressdev = compressdev; 769 priv->min_block_size = attr->compress_min_block_size; 770 if (mlx5_devx_uar_prepare(cdev, &priv->uar) != 0) { 771 rte_compressdev_pmd_destroy(priv->compressdev); 772 return -1; 773 } 774 pthread_mutex_lock(&priv_list_lock); 775 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next); 776 pthread_mutex_unlock(&priv_list_lock); 777 return 0; 778 } 779 780 static int 781 mlx5_compress_dev_remove(struct mlx5_common_device *cdev) 782 { 783 struct mlx5_compress_priv *priv = NULL; 784 785 pthread_mutex_lock(&priv_list_lock); 786 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 787 if (priv->compressdev->device == cdev->dev) 788 break; 789 if (priv) 790 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); 791 pthread_mutex_unlock(&priv_list_lock); 792 if (priv) { 793 mlx5_devx_uar_release(&priv->uar); 794 rte_compressdev_pmd_destroy(priv->compressdev); 795 } 796 return 0; 797 } 798 799 static const struct rte_pci_id mlx5_compress_pci_id_map[] = { 800 { 801 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 802 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2) 803 }, 804 { 805 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 806 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3) 807 }, 808 { 809 .vendor_id = 0 810 } 811 }; 812 813 static struct mlx5_class_driver mlx5_compress_driver = { 814 .drv_class = MLX5_CLASS_COMPRESS, 815 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), 816 .id_table = mlx5_compress_pci_id_map, 817 .probe = mlx5_compress_dev_probe, 818 .remove = mlx5_compress_dev_remove, 819 }; 820 821 RTE_INIT(rte_mlx5_compress_init) 822 { 823 mlx5_common_init(); 824 if (mlx5_glue != NULL) 825 mlx5_class_driver_register(&mlx5_compress_driver); 826 } 827 828 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) 829 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__); 830 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map); 831 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 832