1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <rte_bus_pci.h> 9 #include <rte_spinlock.h> 10 #include <rte_comp.h> 11 #include <rte_compressdev.h> 12 #include <rte_compressdev_pmd.h> 13 14 #include <mlx5_glue.h> 15 #include <mlx5_common.h> 16 #include <mlx5_devx_cmds.h> 17 #include <mlx5_common_os.h> 18 #include <mlx5_common_devx.h> 19 #include <mlx5_common_mr.h> 20 #include <mlx5_prm.h> 21 22 #include "mlx5_compress_utils.h" 23 24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress 25 #define MLX5_COMPRESS_MAX_QPS 1024 26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u 27 28 struct mlx5_compress_xform { 29 LIST_ENTRY(mlx5_compress_xform) next; 30 enum rte_comp_xform_type type; 31 enum rte_comp_checksum_type csum_type; 32 uint32_t opcode; 33 uint32_t gga_ctrl1; /* BE. */ 34 }; 35 36 struct mlx5_compress_priv { 37 TAILQ_ENTRY(mlx5_compress_priv) next; 38 struct rte_compressdev *compressdev; 39 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 40 void *uar; 41 uint8_t min_block_size; 42 /* Minimum huffman block size supported by the device. */ 43 struct rte_compressdev_config dev_config; 44 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; 45 rte_spinlock_t xform_sl; 46 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 47 volatile uint64_t *uar_addr; 48 /* HCA caps*/ 49 uint32_t mmo_decomp_sq:1; 50 uint32_t mmo_decomp_qp:1; 51 uint32_t mmo_comp_sq:1; 52 uint32_t mmo_comp_qp:1; 53 uint32_t mmo_dma_sq:1; 54 uint32_t mmo_dma_qp:1; 55 #ifndef RTE_ARCH_64 56 rte_spinlock_t uar32_sl; 57 #endif /* RTE_ARCH_64 */ 58 }; 59 60 struct mlx5_compress_qp { 61 uint16_t qp_id; 62 uint16_t entries_n; 63 uint16_t pi; 64 uint16_t ci; 65 struct mlx5_mr_ctrl mr_ctrl; 66 int socket_id; 67 struct mlx5_devx_cq cq; 68 struct mlx5_devx_qp qp; 69 struct mlx5_pmd_mr opaque_mr; 70 struct rte_comp_op **ops; 71 struct mlx5_compress_priv *priv; 72 struct rte_compressdev_stats stats; 73 }; 74 75 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list = 76 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list); 77 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 78 79 int mlx5_compress_logtype; 80 81 static const struct rte_compressdev_capabilities mlx5_caps[] = { 82 { 83 .algo = RTE_COMP_ALGO_NULL, 84 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 85 RTE_COMP_FF_CRC32_CHECKSUM | 86 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 87 RTE_COMP_FF_SHAREABLE_PRIV_XFORM, 88 }, 89 { 90 .algo = RTE_COMP_ALGO_DEFLATE, 91 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 92 RTE_COMP_FF_CRC32_CHECKSUM | 93 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 94 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 95 RTE_COMP_FF_HUFFMAN_FIXED | 96 RTE_COMP_FF_HUFFMAN_DYNAMIC, 97 .window_size = {.min = 10, .max = 15, .increment = 1}, 98 }, 99 { 100 .algo = RTE_COMP_ALGO_LIST_END, 101 } 102 }; 103 104 static void 105 mlx5_compress_dev_info_get(struct rte_compressdev *dev, 106 struct rte_compressdev_info *info) 107 { 108 RTE_SET_USED(dev); 109 if (info != NULL) { 110 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS; 111 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 112 info->capabilities = mlx5_caps; 113 } 114 } 115 116 static int 117 mlx5_compress_dev_configure(struct rte_compressdev *dev, 118 struct rte_compressdev_config *config) 119 { 120 struct mlx5_compress_priv *priv; 121 122 if (dev == NULL || config == NULL) 123 return -EINVAL; 124 priv = dev->data->dev_private; 125 priv->dev_config = *config; 126 return 0; 127 } 128 129 static int 130 mlx5_compress_dev_close(struct rte_compressdev *dev) 131 { 132 RTE_SET_USED(dev); 133 return 0; 134 } 135 136 static int 137 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) 138 { 139 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 140 141 if (qp->qp.qp != NULL) 142 mlx5_devx_qp_destroy(&qp->qp); 143 if (qp->cq.cq != NULL) 144 mlx5_devx_cq_destroy(&qp->cq); 145 if (qp->opaque_mr.obj != NULL) { 146 void *opaq = qp->opaque_mr.addr; 147 148 mlx5_common_verbs_dereg_mr(&qp->opaque_mr); 149 if (opaq != NULL) 150 rte_free(opaq); 151 } 152 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 153 rte_free(qp); 154 dev->data->queue_pairs[qp_id] = NULL; 155 return 0; 156 } 157 158 static void 159 mlx5_compress_init_qp(struct mlx5_compress_qp *qp) 160 { 161 volatile struct mlx5_gga_wqe *restrict wqe = 162 (volatile struct mlx5_gga_wqe *)qp->qp.wqes; 163 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 164 const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u); 165 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << 166 MLX5_COMP_MODE_OFFSET); 167 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey); 168 int i; 169 170 /* All the next fields state should stay constant. */ 171 for (i = 0; i < qp->entries_n; ++i, ++wqe) { 172 wqe->sq_ds = sq_ds; 173 wqe->flags = flags; 174 wqe->opaque_lkey = opaq_lkey; 175 wqe->opaque_vaddr = rte_cpu_to_be_64 176 ((uint64_t)(uintptr_t)&opaq[i]); 177 } 178 } 179 180 static int 181 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, 182 uint32_t max_inflight_ops, int socket_id) 183 { 184 struct mlx5_compress_priv *priv = dev->data->dev_private; 185 struct mlx5_compress_qp *qp; 186 struct mlx5_devx_cq_attr cq_attr = { 187 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), 188 }; 189 struct mlx5_devx_qp_attr qp_attr = { 190 .pd = priv->cdev->pdn, 191 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar), 192 .user_index = qp_id, 193 }; 194 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); 195 uint32_t alloc_size = sizeof(*qp); 196 void *opaq_buf; 197 int ret; 198 199 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 200 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n); 201 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 202 socket_id); 203 if (qp == NULL) { 204 DRV_LOG(ERR, "Failed to allocate qp memory."); 205 rte_errno = ENOMEM; 206 return -rte_errno; 207 } 208 dev->data->queue_pairs[qp_id] = qp; 209 if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->mr_scache.dev_gen, 210 priv->dev_config.socket_id)) { 211 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 212 (uint32_t)qp_id); 213 rte_errno = ENOMEM; 214 goto err; 215 } 216 opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n, 217 sizeof(struct mlx5_gga_compress_opaque), 218 sizeof(struct mlx5_gga_compress_opaque)); 219 if (opaq_buf == NULL) { 220 DRV_LOG(ERR, "Failed to allocate opaque memory."); 221 rte_errno = ENOMEM; 222 goto err; 223 } 224 qp->entries_n = 1 << log_ops_n; 225 qp->socket_id = socket_id; 226 qp->qp_id = qp_id; 227 qp->priv = priv; 228 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), 229 RTE_CACHE_LINE_SIZE); 230 if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n * 231 sizeof(struct mlx5_gga_compress_opaque), 232 &qp->opaque_mr) != 0) { 233 rte_free(opaq_buf); 234 DRV_LOG(ERR, "Failed to register opaque MR."); 235 rte_errno = ENOMEM; 236 goto err; 237 } 238 ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr, 239 socket_id); 240 if (ret != 0) { 241 DRV_LOG(ERR, "Failed to create CQ."); 242 goto err; 243 } 244 qp_attr.cqn = qp->cq.cq->id; 245 qp_attr.ts_format = 246 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); 247 qp_attr.rq_size = 0; 248 qp_attr.sq_size = RTE_BIT32(log_ops_n); 249 qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp 250 && priv->mmo_dma_qp; 251 ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr, 252 socket_id); 253 if (ret != 0) { 254 DRV_LOG(ERR, "Failed to create QP."); 255 goto err; 256 } 257 mlx5_compress_init_qp(qp); 258 ret = mlx5_devx_qp2rts(&qp->qp, 0); 259 if (ret) 260 goto err; 261 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", 262 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n); 263 return 0; 264 err: 265 mlx5_compress_qp_release(dev, qp_id); 266 return -1; 267 } 268 269 static int 270 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform) 271 { 272 struct mlx5_compress_priv *priv = dev->data->dev_private; 273 274 rte_spinlock_lock(&priv->xform_sl); 275 LIST_REMOVE((struct mlx5_compress_xform *)xform, next); 276 rte_spinlock_unlock(&priv->xform_sl); 277 rte_free(xform); 278 return 0; 279 } 280 281 static int 282 mlx5_compress_xform_create(struct rte_compressdev *dev, 283 const struct rte_comp_xform *xform, 284 void **private_xform) 285 { 286 struct mlx5_compress_priv *priv = dev->data->dev_private; 287 struct mlx5_compress_xform *xfrm; 288 uint32_t size; 289 290 if (xform->type == RTE_COMP_COMPRESS && xform->compress.level == 291 RTE_COMP_LEVEL_NONE) { 292 DRV_LOG(ERR, "Non-compressed block is not supported."); 293 return -ENOTSUP; 294 } 295 if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo != 296 RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS && 297 xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) { 298 DRV_LOG(ERR, "SHA is not supported."); 299 return -ENOTSUP; 300 } 301 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0, 302 priv->dev_config.socket_id); 303 if (xfrm == NULL) 304 return -ENOMEM; 305 xfrm->opcode = MLX5_OPCODE_MMO; 306 xfrm->type = xform->type; 307 switch (xform->type) { 308 case RTE_COMP_COMPRESS: 309 switch (xform->compress.algo) { 310 case RTE_COMP_ALGO_NULL: 311 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 312 WQE_CSEG_OPC_MOD_OFFSET; 313 break; 314 case RTE_COMP_ALGO_DEFLATE: 315 size = 1 << xform->compress.window_size; 316 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS; 317 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), 318 MLX5_COMP_MAX_WIN_SIZE_CONF) << 319 WQE_GGA_COMP_WIN_SIZE_OFFSET; 320 switch (xform->compress.level) { 321 case RTE_COMP_LEVEL_PMD_DEFAULT: 322 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 323 break; 324 case RTE_COMP_LEVEL_MAX: 325 size = priv->min_block_size; 326 break; 327 default: 328 size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 329 + 1 - xform->compress.level, 330 priv->min_block_size); 331 } 332 xfrm->gga_ctrl1 += RTE_MIN(size, 333 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) << 334 WQE_GGA_COMP_BLOCK_SIZE_OFFSET; 335 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << 336 WQE_CSEG_OPC_MOD_OFFSET; 337 size = xform->compress.deflate.huffman == 338 RTE_COMP_HUFFMAN_DYNAMIC ? 339 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX : 340 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN; 341 xfrm->gga_ctrl1 += size << 342 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET; 343 break; 344 default: 345 goto err; 346 } 347 xfrm->csum_type = xform->compress.chksum; 348 break; 349 case RTE_COMP_DECOMPRESS: 350 switch (xform->decompress.algo) { 351 case RTE_COMP_ALGO_NULL: 352 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 353 WQE_CSEG_OPC_MOD_OFFSET; 354 break; 355 case RTE_COMP_ALGO_DEFLATE: 356 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << 357 WQE_CSEG_OPC_MOD_OFFSET; 358 break; 359 default: 360 goto err; 361 } 362 xfrm->csum_type = xform->decompress.chksum; 363 break; 364 default: 365 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type); 366 goto err; 367 } 368 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum " 369 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type); 370 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1); 371 rte_spinlock_lock(&priv->xform_sl); 372 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next); 373 rte_spinlock_unlock(&priv->xform_sl); 374 *private_xform = xfrm; 375 return 0; 376 err: 377 rte_free(xfrm); 378 return -ENOTSUP; 379 } 380 381 static void 382 mlx5_compress_dev_stop(struct rte_compressdev *dev) 383 { 384 RTE_SET_USED(dev); 385 } 386 387 static int 388 mlx5_compress_dev_start(struct rte_compressdev *dev) 389 { 390 RTE_SET_USED(dev); 391 return 0; 392 } 393 394 static void 395 mlx5_compress_stats_get(struct rte_compressdev *dev, 396 struct rte_compressdev_stats *stats) 397 { 398 int qp_id; 399 400 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 401 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 402 403 stats->enqueued_count += qp->stats.enqueued_count; 404 stats->dequeued_count += qp->stats.dequeued_count; 405 stats->enqueue_err_count += qp->stats.enqueue_err_count; 406 stats->dequeue_err_count += qp->stats.dequeue_err_count; 407 } 408 } 409 410 static void 411 mlx5_compress_stats_reset(struct rte_compressdev *dev) 412 { 413 int qp_id; 414 415 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 416 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 417 418 memset(&qp->stats, 0, sizeof(qp->stats)); 419 } 420 } 421 422 static struct rte_compressdev_ops mlx5_compress_ops = { 423 .dev_configure = mlx5_compress_dev_configure, 424 .dev_start = mlx5_compress_dev_start, 425 .dev_stop = mlx5_compress_dev_stop, 426 .dev_close = mlx5_compress_dev_close, 427 .dev_infos_get = mlx5_compress_dev_info_get, 428 .stats_get = mlx5_compress_stats_get, 429 .stats_reset = mlx5_compress_stats_reset, 430 .queue_pair_setup = mlx5_compress_qp_setup, 431 .queue_pair_release = mlx5_compress_qp_release, 432 .private_xform_create = mlx5_compress_xform_create, 433 .private_xform_free = mlx5_compress_xform_free, 434 .stream_create = NULL, 435 .stream_free = NULL, 436 }; 437 438 /** 439 * Query LKey from a packet buffer for QP. If not found, add the mempool. 440 * 441 * @param priv 442 * Pointer to the priv object. 443 * @param addr 444 * Search key. 445 * @param mr_ctrl 446 * Pointer to per-queue MR control structure. 447 * @param ol_flags 448 * Mbuf offload features. 449 * 450 * @return 451 * Searched LKey on success, UINT32_MAX on no match. 452 */ 453 static __rte_always_inline uint32_t 454 mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr, 455 struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags) 456 { 457 uint32_t lkey; 458 459 /* Check generation bit to see if there's any change on existing MRs. */ 460 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 461 mlx5_mr_flush_local_cache(mr_ctrl); 462 /* Linear search on MR cache array. */ 463 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 464 MLX5_MR_CACHE_N, addr); 465 if (likely(lkey != UINT32_MAX)) 466 return lkey; 467 /* Take slower bottom-half on miss. */ 468 return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl, 469 addr, !!(ol_flags & EXT_ATTACHED_MBUF)); 470 } 471 472 static __rte_always_inline uint32_t 473 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, 474 volatile struct mlx5_wqe_dseg *restrict dseg, 475 struct rte_mbuf *restrict mbuf, 476 uint32_t offset, uint32_t len) 477 { 478 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 479 480 dseg->bcount = rte_cpu_to_be_32(len); 481 dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl, 482 mbuf->ol_flags); 483 dseg->pbuf = rte_cpu_to_be_64(addr); 484 return dseg->lkey; 485 } 486 487 /* 488 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 489 * 64bit architectures. 490 */ 491 static __rte_always_inline void 492 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv) 493 { 494 #ifdef RTE_ARCH_64 495 *priv->uar_addr = val; 496 #else /* !RTE_ARCH_64 */ 497 rte_spinlock_lock(&priv->uar32_sl); 498 *(volatile uint32_t *)priv->uar_addr = val; 499 rte_io_wmb(); 500 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; 501 rte_spinlock_unlock(&priv->uar32_sl); 502 #endif 503 } 504 505 static uint16_t 506 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, 507 uint16_t nb_ops) 508 { 509 struct mlx5_compress_qp *qp = queue_pair; 510 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 511 qp->qp.wqes, *wqe; 512 struct mlx5_compress_xform *xform; 513 struct rte_comp_op *op; 514 uint16_t mask = qp->entries_n - 1; 515 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 516 uint16_t idx; 517 bool invalid; 518 519 if (remain < nb_ops) 520 nb_ops = remain; 521 else 522 remain = nb_ops; 523 if (unlikely(remain == 0)) 524 return 0; 525 do { 526 idx = qp->pi & mask; 527 wqe = &wqes[idx]; 528 rte_prefetch0(&wqes[(qp->pi + 1) & mask]); 529 op = *ops++; 530 xform = op->private_xform; 531 /* 532 * Check operation arguments and error cases: 533 * - Operation type must be state-less. 534 * - Compress operation flush flag must be FULL or FINAL. 535 * - Source and destination buffers must be mapped internally. 536 */ 537 invalid = op->op_type != RTE_COMP_OP_STATELESS || 538 (xform->type == RTE_COMP_COMPRESS && 539 op->flush_flag < RTE_COMP_FLUSH_FULL); 540 if (unlikely(invalid || 541 (mlx5_compress_dseg_set(qp, &wqe->gather, 542 op->m_src, 543 op->src.offset, 544 op->src.length) == 545 UINT32_MAX) || 546 (mlx5_compress_dseg_set(qp, &wqe->scatter, 547 op->m_dst, 548 op->dst.offset, 549 rte_pktmbuf_pkt_len(op->m_dst) - 550 op->dst.offset) == 551 UINT32_MAX))) { 552 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS : 553 RTE_COMP_OP_STATUS_ERROR; 554 nb_ops -= remain; 555 if (unlikely(nb_ops == 0)) 556 return 0; 557 break; 558 } 559 wqe->gga_ctrl1 = xform->gga_ctrl1; 560 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8)); 561 qp->ops[idx] = op; 562 qp->pi++; 563 } while (--remain); 564 qp->stats.enqueued_count += nb_ops; 565 rte_io_wmb(); 566 qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); 567 rte_wmb(); 568 mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv); 569 rte_wmb(); 570 return nb_ops; 571 } 572 573 static void 574 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, 575 volatile uint32_t *opaq) 576 { 577 size_t i; 578 579 DRV_LOG(ERR, "Error cqe:"); 580 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4) 581 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], 582 cqe[i + 2], cqe[i + 3]); 583 DRV_LOG(ERR, "\nError wqe:"); 584 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4) 585 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1], 586 wqe[i + 2], wqe[i + 3]); 587 DRV_LOG(ERR, "\nError opaq:"); 588 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4) 589 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1], 590 opaq[i + 2], opaq[i + 3]); 591 } 592 593 static void 594 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, 595 struct rte_comp_op *op) 596 { 597 const uint32_t idx = qp->ci & (qp->entries_n - 1); 598 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 599 &qp->cq.cqes[idx]; 600 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 601 qp->qp.wqes; 602 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 603 604 op->status = RTE_COMP_OP_STATUS_ERROR; 605 op->consumed = 0; 606 op->produced = 0; 607 op->output_chksum = 0; 608 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) | 609 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32); 610 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe, 611 (volatile uint32_t *)&wqes[idx], 612 (volatile uint32_t *)&opaq[idx]); 613 qp->stats.dequeue_err_count++; 614 } 615 616 static uint16_t 617 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, 618 uint16_t nb_ops) 619 { 620 struct mlx5_compress_qp *qp = queue_pair; 621 volatile struct mlx5_compress_xform *restrict xform; 622 volatile struct mlx5_cqe *restrict cqe; 623 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 624 struct rte_comp_op *restrict op; 625 const unsigned int cq_size = qp->entries_n; 626 const unsigned int mask = cq_size - 1; 627 uint32_t idx; 628 uint32_t next_idx = qp->ci & mask; 629 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 630 uint16_t i = 0; 631 int ret; 632 633 if (unlikely(max == 0)) 634 return 0; 635 do { 636 idx = next_idx; 637 next_idx = (qp->ci + 1) & mask; 638 rte_prefetch0(&qp->cq.cqes[next_idx]); 639 rte_prefetch0(qp->ops[next_idx]); 640 op = qp->ops[idx]; 641 cqe = &qp->cq.cqes[idx]; 642 ret = check_cqe(cqe, cq_size, qp->ci); 643 /* 644 * Be sure owner read is done before any other cookie field or 645 * opaque field. 646 */ 647 rte_io_rmb(); 648 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 649 if (likely(ret == MLX5_CQE_STATUS_HW_OWN)) 650 break; 651 mlx5_compress_cqe_err_handle(qp, op); 652 } else { 653 xform = op->private_xform; 654 op->status = RTE_COMP_OP_STATUS_SUCCESS; 655 op->consumed = op->src.length; 656 op->produced = rte_be_to_cpu_32(cqe->byte_cnt); 657 MLX5_ASSERT(cqe->byte_cnt == 658 opaq[idx].scattered_length); 659 switch (xform->csum_type) { 660 case RTE_COMP_CHECKSUM_CRC32: 661 op->output_chksum = (uint64_t)rte_be_to_cpu_32 662 (opaq[idx].crc32); 663 break; 664 case RTE_COMP_CHECKSUM_ADLER32: 665 op->output_chksum = (uint64_t)rte_be_to_cpu_32 666 (opaq[idx].adler32) << 32; 667 break; 668 case RTE_COMP_CHECKSUM_CRC32_ADLER32: 669 op->output_chksum = (uint64_t)rte_be_to_cpu_32 670 (opaq[idx].crc32) | 671 ((uint64_t)rte_be_to_cpu_32 672 (opaq[idx].adler32) << 32); 673 break; 674 default: 675 break; 676 } 677 } 678 ops[i++] = op; 679 qp->ci++; 680 } while (i < max); 681 if (likely(i != 0)) { 682 rte_io_wmb(); 683 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci); 684 qp->stats.dequeued_count += i; 685 } 686 return i; 687 } 688 689 static void 690 mlx5_compress_uar_release(struct mlx5_compress_priv *priv) 691 { 692 if (priv->uar != NULL) { 693 mlx5_glue->devx_free_uar(priv->uar); 694 priv->uar = NULL; 695 } 696 } 697 698 static int 699 mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv) 700 { 701 priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1); 702 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) == 703 NULL) { 704 rte_errno = errno; 705 DRV_LOG(ERR, "Failed to allocate UAR."); 706 return -1; 707 } 708 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); 709 MLX5_ASSERT(priv->uar_addr); 710 #ifndef RTE_ARCH_64 711 rte_spinlock_init(&priv->uar32_sl); 712 #endif /* RTE_ARCH_64 */ 713 return 0; 714 } 715 716 /** 717 * Callback for memory event. 718 * 719 * @param event_type 720 * Memory event type. 721 * @param addr 722 * Address of memory. 723 * @param len 724 * Size of memory. 725 */ 726 static void 727 mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, 728 size_t len, void *arg __rte_unused) 729 { 730 struct mlx5_compress_priv *priv; 731 732 /* Must be called from the primary process. */ 733 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 734 switch (event_type) { 735 case RTE_MEM_EVENT_FREE: 736 pthread_mutex_lock(&priv_list_lock); 737 /* Iterate all the existing mlx5 devices. */ 738 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 739 mlx5_free_mr_by_addr(&priv->mr_scache, 740 mlx5_os_get_ctx_device_name 741 (priv->cdev->ctx), 742 addr, len); 743 pthread_mutex_unlock(&priv_list_lock); 744 break; 745 case RTE_MEM_EVENT_ALLOC: 746 default: 747 break; 748 } 749 } 750 751 static int 752 mlx5_compress_dev_probe(struct mlx5_common_device *cdev) 753 { 754 struct rte_compressdev *compressdev; 755 struct mlx5_compress_priv *priv; 756 struct mlx5_hca_attr *attr = &cdev->config.hca_attr; 757 struct rte_compressdev_pmd_init_params init_params = { 758 .name = "", 759 .socket_id = cdev->dev->numa_node, 760 }; 761 const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 762 763 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 764 DRV_LOG(ERR, "Non-primary process type is not supported."); 765 rte_errno = ENOTSUP; 766 return -rte_errno; 767 } 768 if ((attr->mmo_compress_sq_en == 0 || attr->mmo_decompress_sq_en == 0 || 769 attr->mmo_dma_sq_en == 0) && (attr->mmo_compress_qp_en == 0 || 770 attr->mmo_decompress_qp_en == 0 || attr->mmo_dma_qp_en == 0)) { 771 DRV_LOG(ERR, "Not enough capabilities to support compress " 772 "operations, maybe old FW/OFED version?"); 773 rte_errno = ENOTSUP; 774 return -ENOTSUP; 775 } 776 compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev, 777 sizeof(*priv), &init_params); 778 if (compressdev == NULL) { 779 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name); 780 return -ENODEV; 781 } 782 DRV_LOG(INFO, 783 "Compress device %s was created successfully.", ibdev_name); 784 compressdev->dev_ops = &mlx5_compress_ops; 785 compressdev->dequeue_burst = mlx5_compress_dequeue_burst; 786 compressdev->enqueue_burst = mlx5_compress_enqueue_burst; 787 compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 788 priv = compressdev->data->dev_private; 789 priv->mmo_decomp_sq = attr->mmo_decompress_sq_en; 790 priv->mmo_decomp_qp = attr->mmo_decompress_qp_en; 791 priv->mmo_comp_sq = attr->mmo_compress_sq_en; 792 priv->mmo_comp_qp = attr->mmo_compress_qp_en; 793 priv->mmo_dma_sq = attr->mmo_dma_sq_en; 794 priv->mmo_dma_qp = attr->mmo_dma_qp_en; 795 priv->cdev = cdev; 796 priv->compressdev = compressdev; 797 priv->min_block_size = attr->compress_min_block_size; 798 if (mlx5_compress_uar_prepare(priv) != 0) { 799 rte_compressdev_pmd_destroy(priv->compressdev); 800 return -1; 801 } 802 if (mlx5_mr_btree_init(&priv->mr_scache.cache, 803 MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) { 804 DRV_LOG(ERR, "Failed to allocate shared cache MR memory."); 805 mlx5_compress_uar_release(priv); 806 rte_compressdev_pmd_destroy(priv->compressdev); 807 rte_errno = ENOMEM; 808 return -rte_errno; 809 } 810 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; 811 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; 812 /* Register callback function for global shared MR cache management. */ 813 if (TAILQ_EMPTY(&mlx5_compress_priv_list)) 814 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 815 mlx5_compress_mr_mem_event_cb, 816 NULL); 817 pthread_mutex_lock(&priv_list_lock); 818 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next); 819 pthread_mutex_unlock(&priv_list_lock); 820 return 0; 821 } 822 823 static int 824 mlx5_compress_dev_remove(struct mlx5_common_device *cdev) 825 { 826 struct mlx5_compress_priv *priv = NULL; 827 828 pthread_mutex_lock(&priv_list_lock); 829 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 830 if (priv->compressdev->device == cdev->dev) 831 break; 832 if (priv) 833 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); 834 pthread_mutex_unlock(&priv_list_lock); 835 if (priv) { 836 if (TAILQ_EMPTY(&mlx5_compress_priv_list)) 837 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", 838 NULL); 839 mlx5_mr_release_cache(&priv->mr_scache); 840 mlx5_compress_uar_release(priv); 841 rte_compressdev_pmd_destroy(priv->compressdev); 842 } 843 return 0; 844 } 845 846 static const struct rte_pci_id mlx5_compress_pci_id_map[] = { 847 { 848 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 849 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 850 }, 851 { 852 .vendor_id = 0 853 } 854 }; 855 856 static struct mlx5_class_driver mlx5_compress_driver = { 857 .drv_class = MLX5_CLASS_COMPRESS, 858 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), 859 .id_table = mlx5_compress_pci_id_map, 860 .probe = mlx5_compress_dev_probe, 861 .remove = mlx5_compress_dev_remove, 862 }; 863 864 RTE_INIT(rte_mlx5_compress_init) 865 { 866 mlx5_common_init(); 867 if (mlx5_glue != NULL) 868 mlx5_class_driver_register(&mlx5_compress_driver); 869 } 870 871 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) 872 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__); 873 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map); 874 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 875