1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <bus_pci_driver.h> 9 #include <rte_spinlock.h> 10 #include <rte_comp.h> 11 #include <rte_compressdev.h> 12 #include <rte_compressdev_pmd.h> 13 14 #include <mlx5_glue.h> 15 #include <mlx5_common.h> 16 #include <mlx5_devx_cmds.h> 17 #include <mlx5_common_os.h> 18 #include <mlx5_common_devx.h> 19 #include <mlx5_common_mr.h> 20 #include <mlx5_prm.h> 21 22 #include "mlx5_compress_utils.h" 23 24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress 25 #define MLX5_COMPRESS_MAX_QPS 1024 26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u 27 28 struct mlx5_compress_devarg_params { 29 uint32_t log_block_sz; 30 }; 31 32 struct mlx5_compress_xform { 33 LIST_ENTRY(mlx5_compress_xform) next; 34 enum rte_comp_xform_type type; 35 enum rte_comp_checksum_type csum_type; 36 uint32_t opcode; 37 uint32_t gga_ctrl1; /* BE. */ 38 }; 39 40 struct mlx5_compress_priv { 41 TAILQ_ENTRY(mlx5_compress_priv) next; 42 struct rte_compressdev *compressdev; 43 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 44 struct mlx5_uar uar; 45 uint8_t min_block_size; 46 /* Minimum huffman block size supported by the device. */ 47 struct rte_compressdev_config dev_config; 48 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; 49 rte_spinlock_t xform_sl; 50 /* HCA caps */ 51 uint32_t mmo_decomp_sq:1; 52 uint32_t mmo_decomp_qp:1; 53 uint32_t mmo_comp_sq:1; 54 uint32_t mmo_comp_qp:1; 55 uint32_t mmo_dma_sq:1; 56 uint32_t mmo_dma_qp:1; 57 uint32_t log_block_sz; 58 }; 59 60 struct mlx5_compress_qp { 61 uint16_t qp_id; 62 uint16_t entries_n; 63 uint16_t pi; 64 uint16_t ci; 65 struct mlx5_mr_ctrl mr_ctrl; 66 int socket_id; 67 struct mlx5_devx_cq cq; 68 struct mlx5_devx_qp qp; 69 struct mlx5_pmd_mr opaque_mr; 70 struct rte_comp_op **ops; 71 struct mlx5_compress_priv *priv; 72 struct rte_compressdev_stats stats; 73 }; 74 75 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list = 76 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list); 77 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 78 79 int mlx5_compress_logtype; 80 81 static const struct rte_compressdev_capabilities mlx5_caps[] = { 82 { 83 .algo = RTE_COMP_ALGO_NULL, 84 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 85 RTE_COMP_FF_CRC32_CHECKSUM | 86 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 87 RTE_COMP_FF_SHAREABLE_PRIV_XFORM, 88 }, 89 { 90 .algo = RTE_COMP_ALGO_DEFLATE, 91 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 92 RTE_COMP_FF_CRC32_CHECKSUM | 93 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 94 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 95 RTE_COMP_FF_HUFFMAN_FIXED | 96 RTE_COMP_FF_HUFFMAN_DYNAMIC, 97 .window_size = {.min = 10, .max = 15, .increment = 1}, 98 }, 99 RTE_COMP_END_OF_CAPABILITIES_LIST() 100 }; 101 102 static void 103 mlx5_compress_dev_info_get(struct rte_compressdev *dev, 104 struct rte_compressdev_info *info) 105 { 106 RTE_SET_USED(dev); 107 if (info != NULL) { 108 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS; 109 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 110 info->capabilities = mlx5_caps; 111 } 112 } 113 114 static int 115 mlx5_compress_dev_configure(struct rte_compressdev *dev, 116 struct rte_compressdev_config *config) 117 { 118 struct mlx5_compress_priv *priv; 119 120 if (dev == NULL || config == NULL) 121 return -EINVAL; 122 priv = dev->data->dev_private; 123 priv->dev_config = *config; 124 return 0; 125 } 126 127 static int 128 mlx5_compress_dev_close(struct rte_compressdev *dev) 129 { 130 RTE_SET_USED(dev); 131 return 0; 132 } 133 134 static int 135 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) 136 { 137 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 138 139 if (qp->qp.qp != NULL) 140 mlx5_devx_qp_destroy(&qp->qp); 141 if (qp->cq.cq != NULL) 142 mlx5_devx_cq_destroy(&qp->cq); 143 if (qp->opaque_mr.obj != NULL) { 144 void *opaq = qp->opaque_mr.addr; 145 146 mlx5_common_verbs_dereg_mr(&qp->opaque_mr); 147 rte_free(opaq); 148 } 149 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 150 rte_free(qp); 151 dev->data->queue_pairs[qp_id] = NULL; 152 return 0; 153 } 154 155 static void 156 mlx5_compress_init_qp(struct mlx5_compress_qp *qp) 157 { 158 volatile struct mlx5_gga_wqe *restrict wqe = 159 (volatile struct mlx5_gga_wqe *)qp->qp.wqes; 160 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 161 const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u); 162 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << 163 MLX5_COMP_MODE_OFFSET); 164 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey); 165 int i; 166 167 /* All the next fields state should stay constant. */ 168 for (i = 0; i < qp->entries_n; ++i, ++wqe) { 169 wqe->sq_ds = sq_ds; 170 wqe->flags = flags; 171 wqe->opaque_lkey = opaq_lkey; 172 wqe->opaque_vaddr = rte_cpu_to_be_64 173 ((uint64_t)(uintptr_t)&opaq[i]); 174 } 175 } 176 177 static int 178 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, 179 uint32_t max_inflight_ops, int socket_id) 180 { 181 struct mlx5_compress_priv *priv = dev->data->dev_private; 182 struct mlx5_compress_qp *qp; 183 struct mlx5_devx_cq_attr cq_attr = { 184 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj), 185 }; 186 struct mlx5_devx_qp_attr qp_attr = { 187 .pd = priv->cdev->pdn, 188 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj), 189 .user_index = qp_id, 190 }; 191 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); 192 uint32_t alloc_size = sizeof(*qp); 193 void *opaq_buf; 194 int ret; 195 196 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 197 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n); 198 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 199 socket_id); 200 if (qp == NULL) { 201 DRV_LOG(ERR, "Failed to allocate qp memory."); 202 rte_errno = ENOMEM; 203 return -rte_errno; 204 } 205 dev->data->queue_pairs[qp_id] = qp; 206 if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen, 207 priv->dev_config.socket_id)) { 208 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 209 (uint32_t)qp_id); 210 rte_errno = ENOMEM; 211 goto err; 212 } 213 opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n, 214 sizeof(struct mlx5_gga_compress_opaque), 215 sizeof(struct mlx5_gga_compress_opaque)); 216 if (opaq_buf == NULL) { 217 DRV_LOG(ERR, "Failed to allocate opaque memory."); 218 rte_errno = ENOMEM; 219 goto err; 220 } 221 qp->entries_n = 1 << log_ops_n; 222 qp->socket_id = socket_id; 223 qp->qp_id = qp_id; 224 qp->priv = priv; 225 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), 226 RTE_CACHE_LINE_SIZE); 227 if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n * 228 sizeof(struct mlx5_gga_compress_opaque), 229 &qp->opaque_mr) != 0) { 230 rte_free(opaq_buf); 231 DRV_LOG(ERR, "Failed to register opaque MR."); 232 rte_errno = ENOMEM; 233 goto err; 234 } 235 ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr, 236 socket_id); 237 if (ret != 0) { 238 DRV_LOG(ERR, "Failed to create CQ."); 239 goto err; 240 } 241 qp_attr.cqn = qp->cq.cq->id; 242 qp_attr.ts_format = 243 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); 244 qp_attr.num_of_receive_wqes = 0; 245 qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n); 246 qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp 247 && priv->mmo_dma_qp; 248 ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, 249 qp_attr.num_of_send_wqbbs * 250 MLX5_WQE_SIZE, &qp_attr, socket_id); 251 if (ret != 0) { 252 DRV_LOG(ERR, "Failed to create QP."); 253 goto err; 254 } 255 mlx5_compress_init_qp(qp); 256 ret = mlx5_devx_qp2rts(&qp->qp, 0); 257 if (ret) 258 goto err; 259 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", 260 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n); 261 return 0; 262 err: 263 mlx5_compress_qp_release(dev, qp_id); 264 return -1; 265 } 266 267 static int 268 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform) 269 { 270 struct mlx5_compress_priv *priv = dev->data->dev_private; 271 272 rte_spinlock_lock(&priv->xform_sl); 273 LIST_REMOVE((struct mlx5_compress_xform *)xform, next); 274 rte_spinlock_unlock(&priv->xform_sl); 275 rte_free(xform); 276 return 0; 277 } 278 279 static int 280 mlx5_compress_xform_create(struct rte_compressdev *dev, 281 const struct rte_comp_xform *xform, 282 void **private_xform) 283 { 284 struct mlx5_compress_priv *priv = dev->data->dev_private; 285 struct mlx5_compress_xform *xfrm; 286 uint32_t size; 287 288 switch (xform->type) { 289 case RTE_COMP_COMPRESS: 290 if (xform->compress.algo == RTE_COMP_ALGO_NULL && 291 !priv->mmo_dma_qp && !priv->mmo_dma_sq) { 292 DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); 293 return -ENOTSUP; 294 } else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) { 295 DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?"); 296 return -ENOTSUP; 297 } 298 if (xform->compress.level == RTE_COMP_LEVEL_NONE) { 299 DRV_LOG(ERR, "Non-compressed block is not supported."); 300 return -ENOTSUP; 301 } 302 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { 303 DRV_LOG(ERR, "SHA is not supported."); 304 return -ENOTSUP; 305 } 306 break; 307 case RTE_COMP_DECOMPRESS: 308 if (xform->decompress.algo == RTE_COMP_ALGO_NULL && 309 !priv->mmo_dma_qp && !priv->mmo_dma_sq) { 310 DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); 311 return -ENOTSUP; 312 } else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) { 313 DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?"); 314 return -ENOTSUP; 315 } 316 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { 317 DRV_LOG(ERR, "SHA is not supported."); 318 return -ENOTSUP; 319 } 320 break; 321 default: 322 DRV_LOG(ERR, "Xform type should be compress/decompress"); 323 return -ENOTSUP; 324 } 325 326 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0, 327 priv->dev_config.socket_id); 328 if (xfrm == NULL) 329 return -ENOMEM; 330 xfrm->opcode = MLX5_OPCODE_MMO; 331 xfrm->type = xform->type; 332 switch (xform->type) { 333 case RTE_COMP_COMPRESS: 334 switch (xform->compress.algo) { 335 case RTE_COMP_ALGO_NULL: 336 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 337 WQE_CSEG_OPC_MOD_OFFSET; 338 break; 339 case RTE_COMP_ALGO_DEFLATE: 340 size = 1 << xform->compress.window_size; 341 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS; 342 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), 343 MLX5_COMP_MAX_WIN_SIZE_CONF) << 344 WQE_GGA_COMP_WIN_SIZE_OFFSET; 345 size = priv->log_block_sz; 346 xfrm->gga_ctrl1 += size << 347 WQE_GGA_COMP_BLOCK_SIZE_OFFSET; 348 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << 349 WQE_CSEG_OPC_MOD_OFFSET; 350 size = xform->compress.deflate.huffman == 351 RTE_COMP_HUFFMAN_DYNAMIC ? 352 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX : 353 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN; 354 xfrm->gga_ctrl1 += size << 355 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET; 356 break; 357 default: 358 goto err; 359 } 360 xfrm->csum_type = xform->compress.chksum; 361 break; 362 case RTE_COMP_DECOMPRESS: 363 switch (xform->decompress.algo) { 364 case RTE_COMP_ALGO_NULL: 365 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 366 WQE_CSEG_OPC_MOD_OFFSET; 367 break; 368 case RTE_COMP_ALGO_DEFLATE: 369 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << 370 WQE_CSEG_OPC_MOD_OFFSET; 371 break; 372 default: 373 goto err; 374 } 375 xfrm->csum_type = xform->decompress.chksum; 376 break; 377 default: 378 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type); 379 goto err; 380 } 381 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum " 382 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type); 383 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1); 384 rte_spinlock_lock(&priv->xform_sl); 385 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next); 386 rte_spinlock_unlock(&priv->xform_sl); 387 *private_xform = xfrm; 388 return 0; 389 err: 390 rte_free(xfrm); 391 return -ENOTSUP; 392 } 393 394 static void 395 mlx5_compress_dev_stop(struct rte_compressdev *dev) 396 { 397 RTE_SET_USED(dev); 398 } 399 400 static int 401 mlx5_compress_dev_start(struct rte_compressdev *dev) 402 { 403 struct mlx5_compress_priv *priv = dev->data->dev_private; 404 405 return mlx5_dev_mempool_subscribe(priv->cdev); 406 } 407 408 static void 409 mlx5_compress_stats_get(struct rte_compressdev *dev, 410 struct rte_compressdev_stats *stats) 411 { 412 int qp_id; 413 414 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 415 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 416 417 stats->enqueued_count += qp->stats.enqueued_count; 418 stats->dequeued_count += qp->stats.dequeued_count; 419 stats->enqueue_err_count += qp->stats.enqueue_err_count; 420 stats->dequeue_err_count += qp->stats.dequeue_err_count; 421 } 422 } 423 424 static void 425 mlx5_compress_stats_reset(struct rte_compressdev *dev) 426 { 427 int qp_id; 428 429 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 430 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 431 432 memset(&qp->stats, 0, sizeof(qp->stats)); 433 } 434 } 435 436 static struct rte_compressdev_ops mlx5_compress_ops = { 437 .dev_configure = mlx5_compress_dev_configure, 438 .dev_start = mlx5_compress_dev_start, 439 .dev_stop = mlx5_compress_dev_stop, 440 .dev_close = mlx5_compress_dev_close, 441 .dev_infos_get = mlx5_compress_dev_info_get, 442 .stats_get = mlx5_compress_stats_get, 443 .stats_reset = mlx5_compress_stats_reset, 444 .queue_pair_setup = mlx5_compress_qp_setup, 445 .queue_pair_release = mlx5_compress_qp_release, 446 .private_xform_create = mlx5_compress_xform_create, 447 .private_xform_free = mlx5_compress_xform_free, 448 .stream_create = NULL, 449 .stream_free = NULL, 450 }; 451 452 static __rte_always_inline uint32_t 453 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, 454 volatile struct mlx5_wqe_dseg *restrict dseg, 455 struct rte_mbuf *restrict mbuf, 456 uint32_t offset, uint32_t len) 457 { 458 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 459 460 dseg->bcount = rte_cpu_to_be_32(len); 461 dseg->lkey = mlx5_mr_mb2mr(&qp->mr_ctrl, mbuf); 462 dseg->pbuf = rte_cpu_to_be_64(addr); 463 return dseg->lkey; 464 } 465 466 static uint16_t 467 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, 468 uint16_t nb_ops) 469 { 470 struct mlx5_compress_qp *qp = queue_pair; 471 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 472 qp->qp.wqes, *wqe; 473 struct mlx5_compress_xform *xform; 474 struct rte_comp_op *op; 475 uint16_t mask = qp->entries_n - 1; 476 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 477 uint16_t idx; 478 bool invalid; 479 480 if (remain < nb_ops) 481 nb_ops = remain; 482 else 483 remain = nb_ops; 484 if (unlikely(remain == 0)) 485 return 0; 486 do { 487 idx = qp->pi & mask; 488 wqe = &wqes[idx]; 489 rte_prefetch0(&wqes[(qp->pi + 1) & mask]); 490 op = *ops++; 491 xform = op->private_xform; 492 /* 493 * Check operation arguments and error cases: 494 * - Operation type must be state-less. 495 * - Compress operation flush flag must be FULL or FINAL. 496 * - Source and destination buffers must be mapped internally. 497 */ 498 invalid = op->op_type != RTE_COMP_OP_STATELESS || 499 (xform->type == RTE_COMP_COMPRESS && 500 op->flush_flag < RTE_COMP_FLUSH_FULL); 501 if (unlikely(invalid || 502 (mlx5_compress_dseg_set(qp, &wqe->gather, 503 op->m_src, 504 op->src.offset, 505 op->src.length) == 506 UINT32_MAX) || 507 (mlx5_compress_dseg_set(qp, &wqe->scatter, 508 op->m_dst, 509 op->dst.offset, 510 rte_pktmbuf_pkt_len(op->m_dst) - 511 op->dst.offset) == 512 UINT32_MAX))) { 513 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS : 514 RTE_COMP_OP_STATUS_ERROR; 515 nb_ops -= remain; 516 if (unlikely(nb_ops == 0)) 517 return 0; 518 break; 519 } 520 wqe->gga_ctrl1 = xform->gga_ctrl1; 521 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8)); 522 qp->ops[idx] = op; 523 qp->pi++; 524 } while (--remain); 525 qp->stats.enqueued_count += nb_ops; 526 mlx5_doorbell_ring(&qp->priv->uar.bf_db, *(volatile uint64_t *)wqe, 527 qp->pi, &qp->qp.db_rec[MLX5_SND_DBR], 528 !qp->priv->uar.dbnc); 529 return nb_ops; 530 } 531 532 static void 533 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, 534 volatile uint32_t *opaq) 535 { 536 size_t i; 537 538 DRV_LOG(ERR, "Error cqe:"); 539 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4) 540 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], 541 cqe[i + 2], cqe[i + 3]); 542 DRV_LOG(ERR, "\nError wqe:"); 543 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4) 544 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1], 545 wqe[i + 2], wqe[i + 3]); 546 DRV_LOG(ERR, "\nError opaq:"); 547 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4) 548 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1], 549 opaq[i + 2], opaq[i + 3]); 550 } 551 552 static void 553 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, 554 struct rte_comp_op *op) 555 { 556 const uint32_t idx = qp->ci & (qp->entries_n - 1); 557 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 558 &qp->cq.cqes[idx]; 559 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 560 qp->qp.wqes; 561 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 562 563 volatile uint32_t *synd_word = RTE_PTR_ADD(cqe, MLX5_ERROR_CQE_SYNDROME_OFFSET); 564 switch (*synd_word) { 565 case MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE: 566 op->status = RTE_COMP_OP_STATUS_OUT_OF_SPACE_TERMINATED; 567 DRV_LOG(DEBUG, "OUT OF SPACE error, output is bigger than dst buffer."); 568 break; 569 case MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE: 570 DRV_LOG(DEBUG, "The last compressed block missed the B-final flag; maybe the compressed data is not complete or garbaged?"); 571 /* fallthrough */ 572 default: 573 op->status = RTE_COMP_OP_STATUS_ERROR; 574 } 575 op->consumed = 0; 576 op->produced = 0; 577 op->output_chksum = 0; 578 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) | 579 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32); 580 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe, 581 (volatile uint32_t *)&wqes[idx], 582 (volatile uint32_t *)&opaq[idx]); 583 qp->stats.dequeue_err_count++; 584 } 585 586 static uint16_t 587 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, 588 uint16_t nb_ops) 589 { 590 struct mlx5_compress_qp *qp = queue_pair; 591 volatile struct mlx5_compress_xform *restrict xform; 592 volatile struct mlx5_cqe *restrict cqe; 593 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 594 struct rte_comp_op *restrict op; 595 const unsigned int cq_size = qp->entries_n; 596 const unsigned int mask = cq_size - 1; 597 uint32_t idx; 598 uint32_t next_idx = qp->ci & mask; 599 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 600 uint16_t i = 0; 601 int ret; 602 603 if (unlikely(max == 0)) 604 return 0; 605 do { 606 idx = next_idx; 607 next_idx = (qp->ci + 1) & mask; 608 rte_prefetch0(&qp->cq.cqes[next_idx]); 609 rte_prefetch0(qp->ops[next_idx]); 610 op = qp->ops[idx]; 611 cqe = &qp->cq.cqes[idx]; 612 ret = check_cqe(cqe, cq_size, qp->ci); 613 /* 614 * Be sure owner read is done before any other cookie field or 615 * opaque field. 616 */ 617 rte_io_rmb(); 618 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 619 if (likely(ret == MLX5_CQE_STATUS_HW_OWN)) 620 break; 621 mlx5_compress_cqe_err_handle(qp, op); 622 } else { 623 xform = op->private_xform; 624 op->status = RTE_COMP_OP_STATUS_SUCCESS; 625 op->consumed = op->src.length; 626 op->produced = rte_be_to_cpu_32(cqe->byte_cnt); 627 MLX5_ASSERT(cqe->byte_cnt == 628 opaq[idx].scattered_length); 629 switch (xform->csum_type) { 630 case RTE_COMP_CHECKSUM_CRC32: 631 op->output_chksum = (uint64_t)rte_be_to_cpu_32 632 (opaq[idx].crc32); 633 break; 634 case RTE_COMP_CHECKSUM_ADLER32: 635 op->output_chksum = (uint64_t)rte_be_to_cpu_32 636 (opaq[idx].adler32) << 32; 637 break; 638 case RTE_COMP_CHECKSUM_CRC32_ADLER32: 639 op->output_chksum = (uint64_t)rte_be_to_cpu_32 640 (opaq[idx].crc32) | 641 ((uint64_t)rte_be_to_cpu_32 642 (opaq[idx].adler32) << 32); 643 break; 644 default: 645 break; 646 } 647 } 648 ops[i++] = op; 649 qp->ci++; 650 } while (i < max); 651 if (likely(i != 0)) { 652 rte_io_wmb(); 653 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci); 654 qp->stats.dequeued_count += i; 655 } 656 return i; 657 } 658 659 static int 660 mlx5_compress_args_check_handler(const char *key, const char *val, void *opaque) 661 { 662 struct mlx5_compress_devarg_params *devarg_prms = opaque; 663 664 if (strcmp(key, "log-block-size") == 0) { 665 errno = 0; 666 devarg_prms->log_block_sz = (uint32_t)strtoul(val, NULL, 10); 667 if (errno) { 668 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", 669 key, val); 670 return -errno; 671 } 672 } 673 return 0; 674 } 675 676 static int 677 mlx5_compress_handle_devargs(struct mlx5_kvargs_ctrl *mkvlist, 678 struct mlx5_compress_devarg_params *devarg_prms, 679 struct mlx5_hca_attr *att) 680 { 681 const char **params = (const char *[]){ 682 "log-block-size", 683 NULL, 684 }; 685 686 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 687 if (mkvlist == NULL) 688 return 0; 689 if (mlx5_kvargs_process(mkvlist, params, 690 mlx5_compress_args_check_handler, 691 devarg_prms) != 0) { 692 DRV_LOG(ERR, "Devargs handler function Failed."); 693 rte_errno = EINVAL; 694 return -1; 695 } 696 if (devarg_prms->log_block_sz > MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX || 697 devarg_prms->log_block_sz < att->compress_min_block_size) { 698 DRV_LOG(WARNING, "Log block size provided is out of range(" 699 "%u); default it to %u.", 700 devarg_prms->log_block_sz, 701 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX); 702 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 703 } 704 return 0; 705 } 706 707 static int 708 mlx5_compress_dev_probe(struct mlx5_common_device *cdev, 709 struct mlx5_kvargs_ctrl *mkvlist) 710 { 711 struct rte_compressdev *compressdev; 712 struct mlx5_compress_priv *priv; 713 struct mlx5_hca_attr *attr = &cdev->config.hca_attr; 714 struct mlx5_compress_devarg_params devarg_prms = {0}; 715 struct rte_compressdev_pmd_init_params init_params = { 716 .name = "", 717 .socket_id = cdev->dev->numa_node, 718 }; 719 const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 720 721 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 722 DRV_LOG(ERR, "Non-primary process type is not supported."); 723 rte_errno = ENOTSUP; 724 return -rte_errno; 725 } 726 if (!attr->mmo_decompress_qp_en && !attr->mmo_decompress_sq_en 727 && !attr->mmo_compress_qp_en && !attr->mmo_compress_sq_en 728 && !attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) { 729 DRV_LOG(ERR, "Not enough capabilities to support compress operations, maybe old FW/OFED version?"); 730 rte_errno = ENOTSUP; 731 return -ENOTSUP; 732 } 733 mlx5_compress_handle_devargs(mkvlist, &devarg_prms, attr); 734 compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev, 735 sizeof(*priv), &init_params); 736 if (compressdev == NULL) { 737 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name); 738 return -ENODEV; 739 } 740 DRV_LOG(INFO, 741 "Compress device %s was created successfully.", ibdev_name); 742 compressdev->dev_ops = &mlx5_compress_ops; 743 compressdev->dequeue_burst = mlx5_compress_dequeue_burst; 744 compressdev->enqueue_burst = mlx5_compress_enqueue_burst; 745 compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 746 priv = compressdev->data->dev_private; 747 priv->log_block_sz = devarg_prms.log_block_sz; 748 priv->mmo_decomp_sq = attr->mmo_decompress_sq_en; 749 priv->mmo_decomp_qp = attr->mmo_decompress_qp_en; 750 priv->mmo_comp_sq = attr->mmo_compress_sq_en; 751 priv->mmo_comp_qp = attr->mmo_compress_qp_en; 752 priv->mmo_dma_sq = attr->mmo_dma_sq_en; 753 priv->mmo_dma_qp = attr->mmo_dma_qp_en; 754 priv->cdev = cdev; 755 priv->compressdev = compressdev; 756 priv->min_block_size = attr->compress_min_block_size; 757 if (mlx5_devx_uar_prepare(cdev, &priv->uar) != 0) { 758 rte_compressdev_pmd_destroy(priv->compressdev); 759 return -1; 760 } 761 pthread_mutex_lock(&priv_list_lock); 762 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next); 763 pthread_mutex_unlock(&priv_list_lock); 764 return 0; 765 } 766 767 static int 768 mlx5_compress_dev_remove(struct mlx5_common_device *cdev) 769 { 770 struct mlx5_compress_priv *priv = NULL; 771 772 pthread_mutex_lock(&priv_list_lock); 773 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 774 if (priv->compressdev->device == cdev->dev) 775 break; 776 if (priv) 777 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); 778 pthread_mutex_unlock(&priv_list_lock); 779 if (priv) { 780 mlx5_devx_uar_release(&priv->uar); 781 rte_compressdev_pmd_destroy(priv->compressdev); 782 } 783 return 0; 784 } 785 786 static const struct rte_pci_id mlx5_compress_pci_id_map[] = { 787 { 788 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 789 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2) 790 }, 791 { 792 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 793 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3) 794 }, 795 { 796 .vendor_id = 0 797 } 798 }; 799 800 static struct mlx5_class_driver mlx5_compress_driver = { 801 .drv_class = MLX5_CLASS_COMPRESS, 802 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), 803 .id_table = mlx5_compress_pci_id_map, 804 .probe = mlx5_compress_dev_probe, 805 .remove = mlx5_compress_dev_remove, 806 }; 807 808 RTE_INIT(rte_mlx5_compress_init) 809 { 810 mlx5_common_init(); 811 if (mlx5_glue != NULL) 812 mlx5_class_driver_register(&mlx5_compress_driver); 813 } 814 815 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) 816 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__); 817 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map); 818 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 819