1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <rte_bus_pci.h> 9 #include <rte_spinlock.h> 10 #include <rte_comp.h> 11 #include <rte_compressdev.h> 12 #include <rte_compressdev_pmd.h> 13 14 #include <mlx5_glue.h> 15 #include <mlx5_common.h> 16 #include <mlx5_devx_cmds.h> 17 #include <mlx5_common_os.h> 18 #include <mlx5_common_devx.h> 19 #include <mlx5_common_mr.h> 20 #include <mlx5_prm.h> 21 22 #include "mlx5_compress_utils.h" 23 24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress 25 #define MLX5_COMPRESS_MAX_QPS 1024 26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u 27 28 struct mlx5_compress_devarg_params { 29 uint32_t log_block_sz; 30 }; 31 32 struct mlx5_compress_xform { 33 LIST_ENTRY(mlx5_compress_xform) next; 34 enum rte_comp_xform_type type; 35 enum rte_comp_checksum_type csum_type; 36 uint32_t opcode; 37 uint32_t gga_ctrl1; /* BE. */ 38 }; 39 40 struct mlx5_compress_priv { 41 TAILQ_ENTRY(mlx5_compress_priv) next; 42 struct rte_compressdev *compressdev; 43 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 44 void *uar; 45 uint8_t min_block_size; 46 /* Minimum huffman block size supported by the device. */ 47 struct rte_compressdev_config dev_config; 48 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; 49 rte_spinlock_t xform_sl; 50 volatile uint64_t *uar_addr; 51 /* HCA caps*/ 52 uint32_t mmo_decomp_sq:1; 53 uint32_t mmo_decomp_qp:1; 54 uint32_t mmo_comp_sq:1; 55 uint32_t mmo_comp_qp:1; 56 uint32_t mmo_dma_sq:1; 57 uint32_t mmo_dma_qp:1; 58 uint32_t log_block_sz; 59 #ifndef RTE_ARCH_64 60 rte_spinlock_t uar32_sl; 61 #endif /* RTE_ARCH_64 */ 62 }; 63 64 struct mlx5_compress_qp { 65 uint16_t qp_id; 66 uint16_t entries_n; 67 uint16_t pi; 68 uint16_t ci; 69 struct mlx5_mr_ctrl mr_ctrl; 70 int socket_id; 71 struct mlx5_devx_cq cq; 72 struct mlx5_devx_qp qp; 73 struct mlx5_pmd_mr opaque_mr; 74 struct rte_comp_op **ops; 75 struct mlx5_compress_priv *priv; 76 struct rte_compressdev_stats stats; 77 }; 78 79 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list = 80 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list); 81 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; 82 83 int mlx5_compress_logtype; 84 85 static const struct rte_compressdev_capabilities mlx5_caps[] = { 86 { 87 .algo = RTE_COMP_ALGO_NULL, 88 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 89 RTE_COMP_FF_CRC32_CHECKSUM | 90 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 91 RTE_COMP_FF_SHAREABLE_PRIV_XFORM, 92 }, 93 { 94 .algo = RTE_COMP_ALGO_DEFLATE, 95 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | 96 RTE_COMP_FF_CRC32_CHECKSUM | 97 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | 98 RTE_COMP_FF_SHAREABLE_PRIV_XFORM | 99 RTE_COMP_FF_HUFFMAN_FIXED | 100 RTE_COMP_FF_HUFFMAN_DYNAMIC, 101 .window_size = {.min = 10, .max = 15, .increment = 1}, 102 }, 103 { 104 .algo = RTE_COMP_ALGO_LIST_END, 105 } 106 }; 107 108 static void 109 mlx5_compress_dev_info_get(struct rte_compressdev *dev, 110 struct rte_compressdev_info *info) 111 { 112 RTE_SET_USED(dev); 113 if (info != NULL) { 114 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS; 115 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 116 info->capabilities = mlx5_caps; 117 } 118 } 119 120 static int 121 mlx5_compress_dev_configure(struct rte_compressdev *dev, 122 struct rte_compressdev_config *config) 123 { 124 struct mlx5_compress_priv *priv; 125 126 if (dev == NULL || config == NULL) 127 return -EINVAL; 128 priv = dev->data->dev_private; 129 priv->dev_config = *config; 130 return 0; 131 } 132 133 static int 134 mlx5_compress_dev_close(struct rte_compressdev *dev) 135 { 136 RTE_SET_USED(dev); 137 return 0; 138 } 139 140 static int 141 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id) 142 { 143 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 144 145 if (qp->qp.qp != NULL) 146 mlx5_devx_qp_destroy(&qp->qp); 147 if (qp->cq.cq != NULL) 148 mlx5_devx_cq_destroy(&qp->cq); 149 if (qp->opaque_mr.obj != NULL) { 150 void *opaq = qp->opaque_mr.addr; 151 152 mlx5_common_verbs_dereg_mr(&qp->opaque_mr); 153 if (opaq != NULL) 154 rte_free(opaq); 155 } 156 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); 157 rte_free(qp); 158 dev->data->queue_pairs[qp_id] = NULL; 159 return 0; 160 } 161 162 static void 163 mlx5_compress_init_qp(struct mlx5_compress_qp *qp) 164 { 165 volatile struct mlx5_gga_wqe *restrict wqe = 166 (volatile struct mlx5_gga_wqe *)qp->qp.wqes; 167 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 168 const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u); 169 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << 170 MLX5_COMP_MODE_OFFSET); 171 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey); 172 int i; 173 174 /* All the next fields state should stay constant. */ 175 for (i = 0; i < qp->entries_n; ++i, ++wqe) { 176 wqe->sq_ds = sq_ds; 177 wqe->flags = flags; 178 wqe->opaque_lkey = opaq_lkey; 179 wqe->opaque_vaddr = rte_cpu_to_be_64 180 ((uint64_t)(uintptr_t)&opaq[i]); 181 } 182 } 183 184 static int 185 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, 186 uint32_t max_inflight_ops, int socket_id) 187 { 188 struct mlx5_compress_priv *priv = dev->data->dev_private; 189 struct mlx5_compress_qp *qp; 190 struct mlx5_devx_cq_attr cq_attr = { 191 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), 192 }; 193 struct mlx5_devx_qp_attr qp_attr = { 194 .pd = priv->cdev->pdn, 195 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar), 196 .user_index = qp_id, 197 }; 198 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); 199 uint32_t alloc_size = sizeof(*qp); 200 void *opaq_buf; 201 int ret; 202 203 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); 204 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n); 205 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, 206 socket_id); 207 if (qp == NULL) { 208 DRV_LOG(ERR, "Failed to allocate qp memory."); 209 rte_errno = ENOMEM; 210 return -rte_errno; 211 } 212 dev->data->queue_pairs[qp_id] = qp; 213 if (mlx5_mr_ctrl_init(&qp->mr_ctrl, priv->cdev, 214 priv->dev_config.socket_id)) { 215 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", 216 (uint32_t)qp_id); 217 rte_errno = ENOMEM; 218 goto err; 219 } 220 opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n, 221 sizeof(struct mlx5_gga_compress_opaque), 222 sizeof(struct mlx5_gga_compress_opaque)); 223 if (opaq_buf == NULL) { 224 DRV_LOG(ERR, "Failed to allocate opaque memory."); 225 rte_errno = ENOMEM; 226 goto err; 227 } 228 qp->entries_n = 1 << log_ops_n; 229 qp->socket_id = socket_id; 230 qp->qp_id = qp_id; 231 qp->priv = priv; 232 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), 233 RTE_CACHE_LINE_SIZE); 234 if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n * 235 sizeof(struct mlx5_gga_compress_opaque), 236 &qp->opaque_mr) != 0) { 237 rte_free(opaq_buf); 238 DRV_LOG(ERR, "Failed to register opaque MR."); 239 rte_errno = ENOMEM; 240 goto err; 241 } 242 ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr, 243 socket_id); 244 if (ret != 0) { 245 DRV_LOG(ERR, "Failed to create CQ."); 246 goto err; 247 } 248 qp_attr.cqn = qp->cq.cq->id; 249 qp_attr.ts_format = 250 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); 251 qp_attr.rq_size = 0; 252 qp_attr.sq_size = RTE_BIT32(log_ops_n); 253 qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp 254 && priv->mmo_dma_qp; 255 ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr, 256 socket_id); 257 if (ret != 0) { 258 DRV_LOG(ERR, "Failed to create QP."); 259 goto err; 260 } 261 mlx5_compress_init_qp(qp); 262 ret = mlx5_devx_qp2rts(&qp->qp, 0); 263 if (ret) 264 goto err; 265 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", 266 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n); 267 return 0; 268 err: 269 mlx5_compress_qp_release(dev, qp_id); 270 return -1; 271 } 272 273 static int 274 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform) 275 { 276 struct mlx5_compress_priv *priv = dev->data->dev_private; 277 278 rte_spinlock_lock(&priv->xform_sl); 279 LIST_REMOVE((struct mlx5_compress_xform *)xform, next); 280 rte_spinlock_unlock(&priv->xform_sl); 281 rte_free(xform); 282 return 0; 283 } 284 285 static int 286 mlx5_compress_xform_create(struct rte_compressdev *dev, 287 const struct rte_comp_xform *xform, 288 void **private_xform) 289 { 290 struct mlx5_compress_priv *priv = dev->data->dev_private; 291 struct mlx5_compress_xform *xfrm; 292 uint32_t size; 293 294 switch (xform->type) { 295 case RTE_COMP_COMPRESS: 296 if (xform->compress.algo == RTE_COMP_ALGO_NULL && 297 !priv->mmo_dma_qp && !priv->mmo_dma_sq) { 298 DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); 299 return -ENOTSUP; 300 } else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) { 301 DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?"); 302 return -ENOTSUP; 303 } 304 if (xform->compress.level == RTE_COMP_LEVEL_NONE) { 305 DRV_LOG(ERR, "Non-compressed block is not supported."); 306 return -ENOTSUP; 307 } 308 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { 309 DRV_LOG(ERR, "SHA is not supported."); 310 return -ENOTSUP; 311 } 312 break; 313 case RTE_COMP_DECOMPRESS: 314 if (xform->decompress.algo == RTE_COMP_ALGO_NULL && 315 !priv->mmo_dma_qp && !priv->mmo_dma_sq) { 316 DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?"); 317 return -ENOTSUP; 318 } else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) { 319 DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?"); 320 return -ENOTSUP; 321 } 322 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) { 323 DRV_LOG(ERR, "SHA is not supported."); 324 return -ENOTSUP; 325 } 326 break; 327 default: 328 DRV_LOG(ERR, "Xform type should be compress/decompress"); 329 return -ENOTSUP; 330 } 331 332 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0, 333 priv->dev_config.socket_id); 334 if (xfrm == NULL) 335 return -ENOMEM; 336 xfrm->opcode = MLX5_OPCODE_MMO; 337 xfrm->type = xform->type; 338 switch (xform->type) { 339 case RTE_COMP_COMPRESS: 340 switch (xform->compress.algo) { 341 case RTE_COMP_ALGO_NULL: 342 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 343 WQE_CSEG_OPC_MOD_OFFSET; 344 break; 345 case RTE_COMP_ALGO_DEFLATE: 346 size = 1 << xform->compress.window_size; 347 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS; 348 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), 349 MLX5_COMP_MAX_WIN_SIZE_CONF) << 350 WQE_GGA_COMP_WIN_SIZE_OFFSET; 351 size = priv->log_block_sz; 352 xfrm->gga_ctrl1 += size << 353 WQE_GGA_COMP_BLOCK_SIZE_OFFSET; 354 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << 355 WQE_CSEG_OPC_MOD_OFFSET; 356 size = xform->compress.deflate.huffman == 357 RTE_COMP_HUFFMAN_DYNAMIC ? 358 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX : 359 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN; 360 xfrm->gga_ctrl1 += size << 361 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET; 362 break; 363 default: 364 goto err; 365 } 366 xfrm->csum_type = xform->compress.chksum; 367 break; 368 case RTE_COMP_DECOMPRESS: 369 switch (xform->decompress.algo) { 370 case RTE_COMP_ALGO_NULL: 371 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA << 372 WQE_CSEG_OPC_MOD_OFFSET; 373 break; 374 case RTE_COMP_ALGO_DEFLATE: 375 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << 376 WQE_CSEG_OPC_MOD_OFFSET; 377 break; 378 default: 379 goto err; 380 } 381 xfrm->csum_type = xform->decompress.chksum; 382 break; 383 default: 384 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type); 385 goto err; 386 } 387 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum " 388 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type); 389 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1); 390 rte_spinlock_lock(&priv->xform_sl); 391 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next); 392 rte_spinlock_unlock(&priv->xform_sl); 393 *private_xform = xfrm; 394 return 0; 395 err: 396 rte_free(xfrm); 397 return -ENOTSUP; 398 } 399 400 static void 401 mlx5_compress_dev_stop(struct rte_compressdev *dev) 402 { 403 RTE_SET_USED(dev); 404 } 405 406 static int 407 mlx5_compress_dev_start(struct rte_compressdev *dev) 408 { 409 struct mlx5_compress_priv *priv = dev->data->dev_private; 410 411 return mlx5_dev_mempool_subscribe(priv->cdev); 412 } 413 414 static void 415 mlx5_compress_stats_get(struct rte_compressdev *dev, 416 struct rte_compressdev_stats *stats) 417 { 418 int qp_id; 419 420 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 421 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 422 423 stats->enqueued_count += qp->stats.enqueued_count; 424 stats->dequeued_count += qp->stats.dequeued_count; 425 stats->enqueue_err_count += qp->stats.enqueue_err_count; 426 stats->dequeue_err_count += qp->stats.dequeue_err_count; 427 } 428 } 429 430 static void 431 mlx5_compress_stats_reset(struct rte_compressdev *dev) 432 { 433 int qp_id; 434 435 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) { 436 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id]; 437 438 memset(&qp->stats, 0, sizeof(qp->stats)); 439 } 440 } 441 442 static struct rte_compressdev_ops mlx5_compress_ops = { 443 .dev_configure = mlx5_compress_dev_configure, 444 .dev_start = mlx5_compress_dev_start, 445 .dev_stop = mlx5_compress_dev_stop, 446 .dev_close = mlx5_compress_dev_close, 447 .dev_infos_get = mlx5_compress_dev_info_get, 448 .stats_get = mlx5_compress_stats_get, 449 .stats_reset = mlx5_compress_stats_reset, 450 .queue_pair_setup = mlx5_compress_qp_setup, 451 .queue_pair_release = mlx5_compress_qp_release, 452 .private_xform_create = mlx5_compress_xform_create, 453 .private_xform_free = mlx5_compress_xform_free, 454 .stream_create = NULL, 455 .stream_free = NULL, 456 }; 457 458 static __rte_always_inline uint32_t 459 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, 460 volatile struct mlx5_wqe_dseg *restrict dseg, 461 struct rte_mbuf *restrict mbuf, 462 uint32_t offset, uint32_t len) 463 { 464 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); 465 466 dseg->bcount = rte_cpu_to_be_32(len); 467 dseg->lkey = mlx5_mr_mb2mr(&qp->mr_ctrl, mbuf, 0); 468 dseg->pbuf = rte_cpu_to_be_64(addr); 469 return dseg->lkey; 470 } 471 472 /* 473 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and 474 * 64bit architectures. 475 */ 476 static __rte_always_inline void 477 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv) 478 { 479 #ifdef RTE_ARCH_64 480 *priv->uar_addr = val; 481 #else /* !RTE_ARCH_64 */ 482 rte_spinlock_lock(&priv->uar32_sl); 483 *(volatile uint32_t *)priv->uar_addr = val; 484 rte_io_wmb(); 485 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; 486 rte_spinlock_unlock(&priv->uar32_sl); 487 #endif 488 } 489 490 static uint16_t 491 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, 492 uint16_t nb_ops) 493 { 494 struct mlx5_compress_qp *qp = queue_pair; 495 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 496 qp->qp.wqes, *wqe; 497 struct mlx5_compress_xform *xform; 498 struct rte_comp_op *op; 499 uint16_t mask = qp->entries_n - 1; 500 uint16_t remain = qp->entries_n - (qp->pi - qp->ci); 501 uint16_t idx; 502 bool invalid; 503 504 if (remain < nb_ops) 505 nb_ops = remain; 506 else 507 remain = nb_ops; 508 if (unlikely(remain == 0)) 509 return 0; 510 do { 511 idx = qp->pi & mask; 512 wqe = &wqes[idx]; 513 rte_prefetch0(&wqes[(qp->pi + 1) & mask]); 514 op = *ops++; 515 xform = op->private_xform; 516 /* 517 * Check operation arguments and error cases: 518 * - Operation type must be state-less. 519 * - Compress operation flush flag must be FULL or FINAL. 520 * - Source and destination buffers must be mapped internally. 521 */ 522 invalid = op->op_type != RTE_COMP_OP_STATELESS || 523 (xform->type == RTE_COMP_COMPRESS && 524 op->flush_flag < RTE_COMP_FLUSH_FULL); 525 if (unlikely(invalid || 526 (mlx5_compress_dseg_set(qp, &wqe->gather, 527 op->m_src, 528 op->src.offset, 529 op->src.length) == 530 UINT32_MAX) || 531 (mlx5_compress_dseg_set(qp, &wqe->scatter, 532 op->m_dst, 533 op->dst.offset, 534 rte_pktmbuf_pkt_len(op->m_dst) - 535 op->dst.offset) == 536 UINT32_MAX))) { 537 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS : 538 RTE_COMP_OP_STATUS_ERROR; 539 nb_ops -= remain; 540 if (unlikely(nb_ops == 0)) 541 return 0; 542 break; 543 } 544 wqe->gga_ctrl1 = xform->gga_ctrl1; 545 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8)); 546 qp->ops[idx] = op; 547 qp->pi++; 548 } while (--remain); 549 qp->stats.enqueued_count += nb_ops; 550 rte_io_wmb(); 551 qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); 552 rte_wmb(); 553 mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv); 554 rte_wmb(); 555 return nb_ops; 556 } 557 558 static void 559 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, 560 volatile uint32_t *opaq) 561 { 562 size_t i; 563 564 DRV_LOG(ERR, "Error cqe:"); 565 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4) 566 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], 567 cqe[i + 2], cqe[i + 3]); 568 DRV_LOG(ERR, "\nError wqe:"); 569 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4) 570 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1], 571 wqe[i + 2], wqe[i + 3]); 572 DRV_LOG(ERR, "\nError opaq:"); 573 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4) 574 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1], 575 opaq[i + 2], opaq[i + 3]); 576 } 577 578 static void 579 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, 580 struct rte_comp_op *op) 581 { 582 const uint32_t idx = qp->ci & (qp->entries_n - 1); 583 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) 584 &qp->cq.cqes[idx]; 585 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) 586 qp->qp.wqes; 587 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 588 589 op->status = RTE_COMP_OP_STATUS_ERROR; 590 op->consumed = 0; 591 op->produced = 0; 592 op->output_chksum = 0; 593 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) | 594 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32); 595 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe, 596 (volatile uint32_t *)&wqes[idx], 597 (volatile uint32_t *)&opaq[idx]); 598 qp->stats.dequeue_err_count++; 599 } 600 601 static uint16_t 602 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, 603 uint16_t nb_ops) 604 { 605 struct mlx5_compress_qp *qp = queue_pair; 606 volatile struct mlx5_compress_xform *restrict xform; 607 volatile struct mlx5_cqe *restrict cqe; 608 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; 609 struct rte_comp_op *restrict op; 610 const unsigned int cq_size = qp->entries_n; 611 const unsigned int mask = cq_size - 1; 612 uint32_t idx; 613 uint32_t next_idx = qp->ci & mask; 614 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops); 615 uint16_t i = 0; 616 int ret; 617 618 if (unlikely(max == 0)) 619 return 0; 620 do { 621 idx = next_idx; 622 next_idx = (qp->ci + 1) & mask; 623 rte_prefetch0(&qp->cq.cqes[next_idx]); 624 rte_prefetch0(qp->ops[next_idx]); 625 op = qp->ops[idx]; 626 cqe = &qp->cq.cqes[idx]; 627 ret = check_cqe(cqe, cq_size, qp->ci); 628 /* 629 * Be sure owner read is done before any other cookie field or 630 * opaque field. 631 */ 632 rte_io_rmb(); 633 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { 634 if (likely(ret == MLX5_CQE_STATUS_HW_OWN)) 635 break; 636 mlx5_compress_cqe_err_handle(qp, op); 637 } else { 638 xform = op->private_xform; 639 op->status = RTE_COMP_OP_STATUS_SUCCESS; 640 op->consumed = op->src.length; 641 op->produced = rte_be_to_cpu_32(cqe->byte_cnt); 642 MLX5_ASSERT(cqe->byte_cnt == 643 opaq[idx].scattered_length); 644 switch (xform->csum_type) { 645 case RTE_COMP_CHECKSUM_CRC32: 646 op->output_chksum = (uint64_t)rte_be_to_cpu_32 647 (opaq[idx].crc32); 648 break; 649 case RTE_COMP_CHECKSUM_ADLER32: 650 op->output_chksum = (uint64_t)rte_be_to_cpu_32 651 (opaq[idx].adler32) << 32; 652 break; 653 case RTE_COMP_CHECKSUM_CRC32_ADLER32: 654 op->output_chksum = (uint64_t)rte_be_to_cpu_32 655 (opaq[idx].crc32) | 656 ((uint64_t)rte_be_to_cpu_32 657 (opaq[idx].adler32) << 32); 658 break; 659 default: 660 break; 661 } 662 } 663 ops[i++] = op; 664 qp->ci++; 665 } while (i < max); 666 if (likely(i != 0)) { 667 rte_io_wmb(); 668 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci); 669 qp->stats.dequeued_count += i; 670 } 671 return i; 672 } 673 674 static void 675 mlx5_compress_uar_release(struct mlx5_compress_priv *priv) 676 { 677 if (priv->uar != NULL) { 678 mlx5_glue->devx_free_uar(priv->uar); 679 priv->uar = NULL; 680 } 681 } 682 683 static int 684 mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv) 685 { 686 priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1); 687 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) == 688 NULL) { 689 rte_errno = errno; 690 DRV_LOG(ERR, "Failed to allocate UAR."); 691 return -1; 692 } 693 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); 694 MLX5_ASSERT(priv->uar_addr); 695 #ifndef RTE_ARCH_64 696 rte_spinlock_init(&priv->uar32_sl); 697 #endif /* RTE_ARCH_64 */ 698 return 0; 699 } 700 701 static int 702 mlx5_compress_args_check_handler(const char *key, const char *val, void *opaque) 703 { 704 struct mlx5_compress_devarg_params *devarg_prms = opaque; 705 706 if (strcmp(key, "log-block-size") == 0) { 707 errno = 0; 708 devarg_prms->log_block_sz = (uint32_t)strtoul(val, NULL, 10); 709 if (errno) { 710 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer." 711 , key, val); 712 return -errno; 713 } 714 return 0; 715 } 716 return 0; 717 } 718 719 static int 720 mlx5_compress_handle_devargs(struct rte_devargs *devargs, 721 struct mlx5_compress_devarg_params *devarg_prms, 722 struct mlx5_hca_attr *att) 723 { 724 struct rte_kvargs *kvlist; 725 726 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 727 if (devargs == NULL) 728 return 0; 729 kvlist = rte_kvargs_parse(devargs->args, NULL); 730 if (kvlist == NULL) { 731 DRV_LOG(ERR, "Failed to parse devargs."); 732 rte_errno = EINVAL; 733 return -1; 734 } 735 if (rte_kvargs_process(kvlist, NULL, mlx5_compress_args_check_handler, 736 devarg_prms) != 0) { 737 DRV_LOG(ERR, "Devargs handler function Failed."); 738 rte_kvargs_free(kvlist); 739 rte_errno = EINVAL; 740 return -1; 741 } 742 rte_kvargs_free(kvlist); 743 if (devarg_prms->log_block_sz > MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX || 744 devarg_prms->log_block_sz < att->compress_min_block_size) { 745 DRV_LOG(WARNING, "Log block size provided is out of range(" 746 "%u); default it to %u.", 747 devarg_prms->log_block_sz, 748 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX); 749 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; 750 } 751 return 0; 752 } 753 754 static int 755 mlx5_compress_dev_probe(struct mlx5_common_device *cdev) 756 { 757 struct rte_compressdev *compressdev; 758 struct mlx5_compress_priv *priv; 759 struct mlx5_hca_attr *attr = &cdev->config.hca_attr; 760 struct mlx5_compress_devarg_params devarg_prms = {0}; 761 struct rte_compressdev_pmd_init_params init_params = { 762 .name = "", 763 .socket_id = cdev->dev->numa_node, 764 }; 765 const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 766 767 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 768 DRV_LOG(ERR, "Non-primary process type is not supported."); 769 rte_errno = ENOTSUP; 770 return -rte_errno; 771 } 772 if (!attr->mmo_decompress_qp_en && !attr->mmo_decompress_sq_en 773 && !attr->mmo_compress_qp_en && !attr->mmo_compress_sq_en 774 && !attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) { 775 DRV_LOG(ERR, "Not enough capabilities to support compress operations, maybe old FW/OFED version?"); 776 claim_zero(mlx5_glue->close_device(cdev->ctx)); 777 rte_errno = ENOTSUP; 778 return -ENOTSUP; 779 } 780 mlx5_compress_handle_devargs(cdev->dev->devargs, &devarg_prms, attr); 781 compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev, 782 sizeof(*priv), &init_params); 783 if (compressdev == NULL) { 784 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name); 785 return -ENODEV; 786 } 787 DRV_LOG(INFO, 788 "Compress device %s was created successfully.", ibdev_name); 789 compressdev->dev_ops = &mlx5_compress_ops; 790 compressdev->dequeue_burst = mlx5_compress_dequeue_burst; 791 compressdev->enqueue_burst = mlx5_compress_enqueue_burst; 792 compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; 793 priv = compressdev->data->dev_private; 794 priv->log_block_sz = devarg_prms.log_block_sz; 795 priv->mmo_decomp_sq = attr->mmo_decompress_sq_en; 796 priv->mmo_decomp_qp = attr->mmo_decompress_qp_en; 797 priv->mmo_comp_sq = attr->mmo_compress_sq_en; 798 priv->mmo_comp_qp = attr->mmo_compress_qp_en; 799 priv->mmo_dma_sq = attr->mmo_dma_sq_en; 800 priv->mmo_dma_qp = attr->mmo_dma_qp_en; 801 priv->cdev = cdev; 802 priv->compressdev = compressdev; 803 priv->min_block_size = attr->compress_min_block_size; 804 if (mlx5_compress_uar_prepare(priv) != 0) { 805 rte_compressdev_pmd_destroy(priv->compressdev); 806 return -1; 807 } 808 pthread_mutex_lock(&priv_list_lock); 809 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next); 810 pthread_mutex_unlock(&priv_list_lock); 811 return 0; 812 } 813 814 static int 815 mlx5_compress_dev_remove(struct mlx5_common_device *cdev) 816 { 817 struct mlx5_compress_priv *priv = NULL; 818 819 pthread_mutex_lock(&priv_list_lock); 820 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) 821 if (priv->compressdev->device == cdev->dev) 822 break; 823 if (priv) 824 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); 825 pthread_mutex_unlock(&priv_list_lock); 826 if (priv) { 827 mlx5_compress_uar_release(priv); 828 rte_compressdev_pmd_destroy(priv->compressdev); 829 } 830 return 0; 831 } 832 833 static const struct rte_pci_id mlx5_compress_pci_id_map[] = { 834 { 835 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 836 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 837 }, 838 { 839 .vendor_id = 0 840 } 841 }; 842 843 static struct mlx5_class_driver mlx5_compress_driver = { 844 .drv_class = MLX5_CLASS_COMPRESS, 845 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), 846 .id_table = mlx5_compress_pci_id_map, 847 .probe = mlx5_compress_dev_probe, 848 .remove = mlx5_compress_dev_remove, 849 }; 850 851 RTE_INIT(rte_mlx5_compress_init) 852 { 853 mlx5_common_init(); 854 if (mlx5_glue != NULL) 855 mlx5_class_driver_register(&mlx5_compress_driver); 856 } 857 858 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) 859 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__); 860 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map); 861 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 862