1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2009-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 10 #if EFSYS_OPT_SIENA 11 12 __checkReturn efx_rc_t 13 siena_mac_poll( 14 __in efx_nic_t *enp, 15 __out efx_link_mode_t *link_modep) 16 { 17 efx_port_t *epp = &(enp->en_port); 18 siena_link_state_t sls; 19 efx_rc_t rc; 20 21 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 22 goto fail1; 23 24 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; 25 epp->ep_fcntl = sls.sls_fcntl; 26 27 *link_modep = sls.sls_link_mode; 28 29 return (0); 30 31 fail1: 32 EFSYS_PROBE1(fail1, efx_rc_t, rc); 33 34 *link_modep = EFX_LINK_UNKNOWN; 35 36 return (rc); 37 } 38 39 __checkReturn efx_rc_t 40 siena_mac_up( 41 __in efx_nic_t *enp, 42 __out boolean_t *mac_upp) 43 { 44 siena_link_state_t sls; 45 efx_rc_t rc; 46 47 /* 48 * Because Siena doesn't *require* polling, we can't rely on 49 * siena_mac_poll() being executed to populate epp->ep_mac_up. 50 */ 51 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 52 goto fail1; 53 54 *mac_upp = sls.sls_mac_up; 55 56 return (0); 57 58 fail1: 59 EFSYS_PROBE1(fail1, efx_rc_t, rc); 60 61 return (rc); 62 } 63 64 __checkReturn efx_rc_t 65 siena_mac_reconfigure( 66 __in efx_nic_t *enp) 67 { 68 efx_port_t *epp = &(enp->en_port); 69 efx_oword_t multicast_hash[2]; 70 efx_mcdi_req_t req; 71 EFX_MCDI_DECLARE_BUF(payload, 72 MAX(MC_CMD_SET_MAC_IN_LEN, MC_CMD_SET_MCAST_HASH_IN_LEN), 73 MAX(MC_CMD_SET_MAC_OUT_LEN, MC_CMD_SET_MCAST_HASH_OUT_LEN)); 74 75 unsigned int fcntl; 76 efx_rc_t rc; 77 78 req.emr_cmd = MC_CMD_SET_MAC; 79 req.emr_in_buf = payload; 80 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN; 81 req.emr_out_buf = payload; 82 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN; 83 84 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); 85 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); 86 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR), 87 epp->ep_mac_addr); 88 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT, 89 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst, 90 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); 91 92 if (epp->ep_fcntl_autoneg) 93 /* efx_fcntl_set() has already set the phy capabilities */ 94 fcntl = MC_CMD_FCNTL_AUTO; 95 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND) 96 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE) 97 ? MC_CMD_FCNTL_BIDIR 98 : MC_CMD_FCNTL_RESPOND; 99 else 100 fcntl = MC_CMD_FCNTL_OFF; 101 102 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl); 103 104 efx_mcdi_execute(enp, &req); 105 106 if (req.emr_rc != 0) { 107 rc = req.emr_rc; 108 goto fail1; 109 } 110 epp->ep_all_unicst_inserted = epp->ep_all_unicst; 111 112 /* Push multicast hash */ 113 114 if (epp->ep_all_mulcst) { 115 /* A hash matching all multicast is all 1s */ 116 EFX_SET_OWORD(multicast_hash[0]); 117 EFX_SET_OWORD(multicast_hash[1]); 118 } else if (epp->ep_mulcst) { 119 /* Use the hash set by the multicast list */ 120 multicast_hash[0] = epp->ep_multicst_hash[0]; 121 multicast_hash[1] = epp->ep_multicst_hash[1]; 122 } else { 123 /* A hash matching no traffic is simply 0 */ 124 EFX_ZERO_OWORD(multicast_hash[0]); 125 EFX_ZERO_OWORD(multicast_hash[1]); 126 } 127 128 /* 129 * Broadcast packets go through the multicast hash filter. 130 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff 131 * so we always add bit 0xff to the mask (bit 0x7f in the 132 * second octword). 133 */ 134 if (epp->ep_brdcst) { 135 /* 136 * NOTE: due to constant folding, some of this evaluates 137 * to null expressions, giving E_EXPR_NULL_EFFECT during 138 * lint on Illumos. No good way to fix this without 139 * explicit coding the individual word/bit setting. 140 * So just suppress lint for this one line. 141 */ 142 /* LINTED */ 143 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f); 144 } 145 146 (void) memset(payload, 0, sizeof (payload)); 147 req.emr_cmd = MC_CMD_SET_MCAST_HASH; 148 req.emr_in_buf = payload; 149 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN; 150 req.emr_out_buf = payload; 151 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN; 152 153 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0), 154 multicast_hash, sizeof (multicast_hash)); 155 156 efx_mcdi_execute(enp, &req); 157 158 if (req.emr_rc != 0) { 159 rc = req.emr_rc; 160 goto fail2; 161 } 162 epp->ep_all_mulcst_inserted = epp->ep_all_mulcst; 163 164 return (0); 165 166 fail2: 167 EFSYS_PROBE(fail2); 168 fail1: 169 EFSYS_PROBE1(fail1, efx_rc_t, rc); 170 171 return (rc); 172 } 173 174 #if EFSYS_OPT_LOOPBACK 175 176 __checkReturn efx_rc_t 177 siena_mac_loopback_set( 178 __in efx_nic_t *enp, 179 __in efx_link_mode_t link_mode, 180 __in efx_loopback_type_t loopback_type) 181 { 182 efx_port_t *epp = &(enp->en_port); 183 const efx_phy_ops_t *epop = epp->ep_epop; 184 efx_loopback_type_t old_loopback_type; 185 efx_link_mode_t old_loopback_link_mode; 186 efx_rc_t rc; 187 188 /* The PHY object handles this on Siena */ 189 old_loopback_type = epp->ep_loopback_type; 190 old_loopback_link_mode = epp->ep_loopback_link_mode; 191 epp->ep_loopback_type = loopback_type; 192 epp->ep_loopback_link_mode = link_mode; 193 194 if ((rc = epop->epo_reconfigure(enp)) != 0) 195 goto fail1; 196 197 return (0); 198 199 fail1: 200 EFSYS_PROBE1(fail1, efx_rc_t, rc); 201 202 epp->ep_loopback_type = old_loopback_type; 203 epp->ep_loopback_link_mode = old_loopback_link_mode; 204 205 return (rc); 206 } 207 208 #endif /* EFSYS_OPT_LOOPBACK */ 209 210 #if EFSYS_OPT_MAC_STATS 211 212 __checkReturn efx_rc_t 213 siena_mac_stats_get_mask( 214 __in efx_nic_t *enp, 215 __inout_bcount(mask_size) uint32_t *maskp, 216 __in size_t mask_size) 217 { 218 const struct efx_mac_stats_range siena_stats[] = { 219 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS }, 220 /* EFX_MAC_RX_ERRORS is not supported */ 221 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS }, 222 }; 223 efx_rc_t rc; 224 225 _NOTE(ARGUNUSED(enp)) 226 227 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size, 228 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0) 229 goto fail1; 230 231 return (0); 232 233 fail1: 234 EFSYS_PROBE1(fail1, efx_rc_t, rc); 235 236 return (rc); 237 } 238 239 #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \ 240 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) 241 242 __checkReturn efx_rc_t 243 siena_mac_stats_update( 244 __in efx_nic_t *enp, 245 __in efsys_mem_t *esmp, 246 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 247 __inout_opt uint32_t *generationp) 248 { 249 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; 250 efx_qword_t generation_start; 251 efx_qword_t generation_end; 252 efx_qword_t value; 253 efx_rc_t rc; 254 255 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) { 256 /* MAC stats count too small */ 257 rc = ENOSPC; 258 goto fail1; 259 } 260 if (EFSYS_MEM_SIZE(esmp) < 261 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) { 262 /* DMA buffer too small */ 263 rc = ENOSPC; 264 goto fail2; 265 } 266 267 /* Read END first so we don't race with the MC */ 268 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp)); 269 SIENA_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1), 270 &generation_end); 271 EFSYS_MEM_READ_BARRIER(); 272 273 /* TX */ 274 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value); 275 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 276 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value); 277 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 278 279 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value); 280 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value); 281 282 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value); 283 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value); 284 285 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value); 286 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value); 287 288 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value); 289 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value); 290 291 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value); 292 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value); 293 294 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value); 295 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 296 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value); 297 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 298 299 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value); 300 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value); 301 302 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value); 303 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value); 304 305 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value); 306 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value); 307 308 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value); 309 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value); 310 311 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value); 312 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value); 313 314 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value); 315 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 316 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value); 317 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 318 319 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value); 320 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value); 321 322 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value); 323 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value); 324 325 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS, 326 &value); 327 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value); 328 329 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS, 330 &value); 331 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value); 332 333 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value); 334 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value); 335 336 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value); 337 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value); 338 339 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS, 340 &value); 341 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value); 342 343 /* RX */ 344 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value); 345 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value); 346 347 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value); 348 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value); 349 350 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value); 351 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value); 352 353 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value); 354 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value); 355 356 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value); 357 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value); 358 359 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value); 360 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value); 361 362 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value); 363 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 364 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value); 365 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 366 367 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value); 368 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value); 369 370 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value); 371 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value); 372 373 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value); 374 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value); 375 376 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value); 377 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value); 378 379 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value); 380 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value); 381 382 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value); 383 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 384 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value); 385 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 386 387 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value); 388 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value); 389 390 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value); 391 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value); 392 393 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value); 394 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value); 395 396 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value); 397 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value); 398 399 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value); 400 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value); 401 402 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value); 403 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value); 404 405 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value); 406 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value); 407 408 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value); 409 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]), 410 &(value.eq_dword[0])); 411 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]), 412 &(value.eq_dword[1])); 413 414 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value); 415 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]), 416 &(value.eq_dword[0])); 417 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]), 418 &(value.eq_dword[1])); 419 420 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value); 421 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]), 422 &(value.eq_dword[0])); 423 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]), 424 &(value.eq_dword[1])); 425 426 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value); 427 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]), 428 &(value.eq_dword[0])); 429 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]), 430 &(value.eq_dword[1])); 431 432 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value); 433 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value); 434 435 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value); 436 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value); 437 438 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp)); 439 EFSYS_MEM_READ_BARRIER(); 440 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START, 441 &generation_start); 442 443 /* Check that we didn't read the stats in the middle of a DMA */ 444 /* Not a good enough check ? */ 445 if (memcmp(&generation_start, &generation_end, 446 sizeof (generation_start))) 447 return (EAGAIN); 448 449 if (generationp) 450 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0); 451 452 return (0); 453 454 fail2: 455 EFSYS_PROBE(fail2); 456 fail1: 457 EFSYS_PROBE1(fail1, efx_rc_t, rc); 458 459 return (rc); 460 } 461 462 #endif /* EFSYS_OPT_MAC_STATS */ 463 464 __checkReturn efx_rc_t 465 siena_mac_pdu_get( 466 __in efx_nic_t *enp, 467 __out size_t *pdu) 468 { 469 return (ENOTSUP); 470 } 471 472 #endif /* EFSYS_OPT_SIENA */ 473