1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2015-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 10 11 #if EFSYS_OPT_MEDFORD2 12 13 static __checkReturn efx_rc_t 14 medford2_nic_get_required_pcie_bandwidth( 15 __in efx_nic_t *enp, 16 __out uint32_t *bandwidth_mbpsp) 17 { 18 uint32_t bandwidth; 19 efx_rc_t rc; 20 21 /* FIXME: support new Medford2 dynamic port modes */ 22 23 if ((rc = ef10_nic_get_port_mode_bandwidth(enp, 24 &bandwidth)) != 0) 25 goto fail1; 26 27 *bandwidth_mbpsp = bandwidth; 28 29 return (0); 30 31 fail1: 32 EFSYS_PROBE1(fail1, efx_rc_t, rc); 33 34 return (rc); 35 } 36 37 __checkReturn efx_rc_t 38 medford2_board_cfg( 39 __in efx_nic_t *enp) 40 { 41 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 42 uint32_t sysclk, dpcpu_clk; 43 uint32_t end_padding; 44 uint32_t bandwidth; 45 efx_rc_t rc; 46 47 /* 48 * Event queue creation is complete when an 49 * EVQ_INIT_DONE_EV event is received. 50 */ 51 encp->enc_evq_init_done_ev_supported = B_TRUE; 52 53 /* 54 * Enable firmware workarounds for hardware errata. 55 * Expected responses are: 56 * - 0 (zero): 57 * Success: workaround enabled or disabled as requested. 58 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): 59 * Firmware does not support the MC_CMD_WORKAROUND request. 60 * (assume that the workaround is not supported). 61 * - MC_CMD_ERR_ENOENT (reported as ENOENT): 62 * Firmware does not support the requested workaround. 63 * - MC_CMD_ERR_EPERM (reported as EACCES): 64 * Unprivileged function cannot enable/disable workarounds. 65 * 66 * See efx_mcdi_request_errcode() for MCDI error translations. 67 */ 68 69 70 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 71 /* 72 * Interrupt testing does not work for VFs on Medford2. 73 * See bug50084 and bug71432 comment 21. 74 */ 75 encp->enc_bug41750_workaround = B_TRUE; 76 } 77 78 /* 79 * If the bug61265 workaround is enabled, then interrupt holdoff timers 80 * cannot be controlled by timer table writes, so MCDI must be used 81 * (timer table writes can still be used for wakeup timers). 82 */ 83 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE, 84 NULL); 85 if ((rc == 0) || (rc == EACCES)) 86 encp->enc_bug61265_workaround = B_TRUE; 87 else if ((rc == ENOTSUP) || (rc == ENOENT)) 88 encp->enc_bug61265_workaround = B_FALSE; 89 else 90 goto fail1; 91 92 /* Checksums for TSO sends should always be correct on Medford2. */ 93 encp->enc_bug61297_workaround = B_FALSE; 94 95 /* Get clock frequencies (in MHz). */ 96 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) 97 goto fail2; 98 99 /* 100 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for 101 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 102 */ 103 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */ 104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 105 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 106 107 encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE; 108 encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; 109 encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; 110 111 /* Alignment for receive packet DMA buffers */ 112 encp->enc_rx_buf_align_start = 1; 113 114 /* Get the RX DMA end padding alignment configuration */ 115 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { 116 if (rc != EACCES) 117 goto fail3; 118 119 /* Assume largest tail padding size supported by hardware */ 120 end_padding = 256; 121 } 122 encp->enc_rx_buf_align_end = end_padding; 123 124 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; 125 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS; 126 127 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; 128 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; 129 130 /* 131 * The maximum supported transmit queue size is 2048. TXQs with 4096 132 * descriptors are not supported as the top bit is used for vfifo 133 * stuffing. 134 */ 135 encp->enc_txq_max_ndescs = MEDFORD2_TXQ_MAXNDESCS; 136 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; 137 138 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); 139 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS; 140 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE; 141 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE; 142 143 /* 144 * Medford2 stores a single global copy of VPD, not per-PF as on 145 * Huntington. 146 */ 147 encp->enc_vpd_is_global = B_TRUE; 148 149 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth); 150 if (rc != 0) 151 goto fail4; 152 encp->enc_required_pcie_bandwidth_mbps = bandwidth; 153 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; 154 155 return (0); 156 157 fail4: 158 EFSYS_PROBE(fail4); 159 fail3: 160 EFSYS_PROBE(fail3); 161 fail2: 162 EFSYS_PROBE(fail2); 163 fail1: 164 EFSYS_PROBE1(fail1, efx_rc_t, rc); 165 166 return (rc); 167 } 168 169 #endif /* EFSYS_OPT_MEDFORD2 */ 170