1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2012-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 #if EFSYS_OPT_MON_MCDI 10 #include "mcdi_mon.h" 11 #endif 12 13 #if EFSYS_OPT_HUNTINGTON 14 15 #include "ef10_tlv_layout.h" 16 17 static __checkReturn efx_rc_t 18 hunt_nic_get_required_pcie_bandwidth( 19 __in efx_nic_t *enp, 20 __out uint32_t *bandwidth_mbpsp) 21 { 22 uint32_t port_modes; 23 uint32_t bandwidth; 24 efx_rc_t rc; 25 26 /* 27 * On Huntington, the firmware may not give us the current port mode, so 28 * we need to go by the set of available port modes and assume the most 29 * capable mode is in use. 30 */ 31 32 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, 33 NULL, NULL)) != 0) { 34 /* No port mode info available */ 35 bandwidth = 0; 36 goto out; 37 } 38 39 if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) { 40 /* 41 * This needs the full PCIe bandwidth (and could use 42 * more) - roughly 64 Gbit/s for 8 lanes of Gen3. 43 */ 44 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8, 45 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0) 46 goto fail1; 47 } else { 48 if (port_modes & (1U << TLV_PORT_MODE_40G)) { 49 bandwidth = 40000; 50 } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) { 51 bandwidth = 4 * 10000; 52 } else { 53 /* Assume two 10G ports */ 54 bandwidth = 2 * 10000; 55 } 56 } 57 58 out: 59 *bandwidth_mbpsp = bandwidth; 60 61 return (0); 62 63 fail1: 64 EFSYS_PROBE1(fail1, efx_rc_t, rc); 65 66 return (rc); 67 } 68 69 __checkReturn efx_rc_t 70 hunt_board_cfg( 71 __in efx_nic_t *enp) 72 { 73 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 74 efx_port_t *epp = &(enp->en_port); 75 uint32_t sysclk, dpcpu_clk; 76 uint32_t bandwidth; 77 efx_rc_t rc; 78 79 /* 80 * Event queue creation is complete when an 81 * EVQ_INIT_DONE_EV event is received. 82 */ 83 encp->enc_evq_init_done_ev_supported = B_TRUE; 84 85 /* 86 * Enable firmware workarounds for hardware errata. 87 * Expected responses are: 88 * - 0 (zero): 89 * Success: workaround enabled or disabled as requested. 90 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): 91 * Firmware does not support the MC_CMD_WORKAROUND request. 92 * (assume that the workaround is not supported). 93 * - MC_CMD_ERR_ENOENT (reported as ENOENT): 94 * Firmware does not support the requested workaround. 95 * - MC_CMD_ERR_EPERM (reported as EACCES): 96 * Unprivileged function cannot enable/disable workarounds. 97 * 98 * See efx_mcdi_request_errcode() for MCDI error translations. 99 */ 100 101 /* 102 * If the bug35388 workaround is enabled, then use an indirect access 103 * method to avoid unsafe EVQ writes. 104 */ 105 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE, 106 NULL); 107 if ((rc == 0) || (rc == EACCES)) 108 encp->enc_bug35388_workaround = B_TRUE; 109 else if ((rc == ENOTSUP) || (rc == ENOENT)) 110 encp->enc_bug35388_workaround = B_FALSE; 111 else 112 goto fail1; 113 114 /* 115 * If the bug41750 workaround is enabled, then do not test interrupts, 116 * as the test will fail (seen with Greenport controllers). 117 */ 118 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE, 119 NULL); 120 if (rc == 0) { 121 encp->enc_bug41750_workaround = B_TRUE; 122 } else if (rc == EACCES) { 123 /* Assume a controller with 40G ports needs the workaround. */ 124 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX) 125 encp->enc_bug41750_workaround = B_TRUE; 126 else 127 encp->enc_bug41750_workaround = B_FALSE; 128 } else if ((rc == ENOTSUP) || (rc == ENOENT)) { 129 encp->enc_bug41750_workaround = B_FALSE; 130 } else { 131 goto fail2; 132 } 133 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 134 /* Interrupt testing does not work for VFs. See bug50084. */ 135 encp->enc_bug41750_workaround = B_TRUE; 136 } 137 138 /* Get clock frequencies (in MHz). */ 139 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) 140 goto fail3; 141 142 /* 143 * The Huntington timer quantum is 1536 sysclk cycles, documented for 144 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 145 */ 146 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ 147 if (encp->enc_bug35388_workaround) { 148 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 149 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000; 150 } else { 151 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 152 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 153 } 154 155 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */ 156 157 /* Checksums for TSO sends can be incorrect on Huntington. */ 158 encp->enc_bug61297_workaround = B_TRUE; 159 160 encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE; 161 encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; 162 encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; 163 164 /* Alignment for receive packet DMA buffers */ 165 encp->enc_rx_buf_align_start = 1; 166 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ 167 168 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; 169 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS; 170 171 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; 172 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; 173 174 /* 175 * The workaround for bug35388 uses the top bit of transmit queue 176 * descriptor writes, preventing the use of 4096 descriptor TXQs. 177 */ 178 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 179 HUNT_TXQ_MAXNDESCS_BUG35388_WORKAROUND : 180 HUNT_TXQ_MAXNDESCS; 181 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; 182 183 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); 184 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; 185 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE; 186 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE; 187 188 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) 189 goto fail4; 190 encp->enc_required_pcie_bandwidth_mbps = bandwidth; 191 192 /* All Huntington devices have a PCIe Gen3, 8 lane connector */ 193 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; 194 195 return (0); 196 197 fail4: 198 EFSYS_PROBE(fail4); 199 fail3: 200 EFSYS_PROBE(fail3); 201 fail2: 202 EFSYS_PROBE(fail2); 203 fail1: 204 EFSYS_PROBE1(fail1, efx_rc_t, rc); 205 206 return (rc); 207 } 208 209 210 #endif /* EFSYS_OPT_HUNTINGTON */ 211