1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 10 11 #if EFSYS_OPT_SIENA 12 13 static __checkReturn efx_rc_t 14 siena_rx_init( 15 __in efx_nic_t *enp); 16 17 static void 18 siena_rx_fini( 19 __in efx_nic_t *enp); 20 21 #if EFSYS_OPT_RX_SCATTER 22 static __checkReturn efx_rc_t 23 siena_rx_scatter_enable( 24 __in efx_nic_t *enp, 25 __in unsigned int buf_size); 26 #endif /* EFSYS_OPT_RX_SCATTER */ 27 28 #if EFSYS_OPT_RX_SCALE 29 static __checkReturn efx_rc_t 30 siena_rx_scale_mode_set( 31 __in efx_nic_t *enp, 32 __in uint32_t rss_context, 33 __in efx_rx_hash_alg_t alg, 34 __in efx_rx_hash_type_t type, 35 __in boolean_t insert); 36 37 static __checkReturn efx_rc_t 38 siena_rx_scale_key_set( 39 __in efx_nic_t *enp, 40 __in uint32_t rss_context, 41 __in_ecount(n) uint8_t *key, 42 __in size_t n); 43 44 static __checkReturn efx_rc_t 45 siena_rx_scale_tbl_set( 46 __in efx_nic_t *enp, 47 __in uint32_t rss_context, 48 __in_ecount(nentries) unsigned int *table, 49 __in size_t nentries); 50 51 static __checkReturn uint32_t 52 siena_rx_prefix_hash( 53 __in efx_nic_t *enp, 54 __in efx_rx_hash_alg_t func, 55 __in uint8_t *buffer); 56 57 #endif /* EFSYS_OPT_RX_SCALE */ 58 59 static __checkReturn efx_rc_t 60 siena_rx_prefix_pktlen( 61 __in efx_nic_t *enp, 62 __in uint8_t *buffer, 63 __out uint16_t *lengthp); 64 65 static void 66 siena_rx_qpost( 67 __in efx_rxq_t *erp, 68 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 69 __in size_t size, 70 __in unsigned int ndescs, 71 __in unsigned int completed, 72 __in unsigned int added); 73 74 static void 75 siena_rx_qpush( 76 __in efx_rxq_t *erp, 77 __in unsigned int added, 78 __inout unsigned int *pushedp); 79 80 #if EFSYS_OPT_RX_PACKED_STREAM 81 static void 82 siena_rx_qpush_ps_credits( 83 __in efx_rxq_t *erp); 84 85 static __checkReturn uint8_t * 86 siena_rx_qps_packet_info( 87 __in efx_rxq_t *erp, 88 __in uint8_t *buffer, 89 __in uint32_t buffer_length, 90 __in uint32_t current_offset, 91 __out uint16_t *lengthp, 92 __out uint32_t *next_offsetp, 93 __out uint32_t *timestamp); 94 #endif 95 96 static __checkReturn efx_rc_t 97 siena_rx_qflush( 98 __in efx_rxq_t *erp); 99 100 static void 101 siena_rx_qenable( 102 __in efx_rxq_t *erp); 103 104 static __checkReturn efx_rc_t 105 siena_rx_qcreate( 106 __in efx_nic_t *enp, 107 __in unsigned int index, 108 __in unsigned int label, 109 __in efx_rxq_type_t type, 110 __in_opt const efx_rxq_type_data_t *type_data, 111 __in efsys_mem_t *esmp, 112 __in size_t ndescs, 113 __in uint32_t id, 114 __in unsigned int flags, 115 __in efx_evq_t *eep, 116 __in efx_rxq_t *erp); 117 118 static void 119 siena_rx_qdestroy( 120 __in efx_rxq_t *erp); 121 122 #endif /* EFSYS_OPT_SIENA */ 123 124 125 #if EFSYS_OPT_SIENA 126 static const efx_rx_ops_t __efx_rx_siena_ops = { 127 siena_rx_init, /* erxo_init */ 128 siena_rx_fini, /* erxo_fini */ 129 #if EFSYS_OPT_RX_SCATTER 130 siena_rx_scatter_enable, /* erxo_scatter_enable */ 131 #endif 132 #if EFSYS_OPT_RX_SCALE 133 NULL, /* erxo_scale_context_alloc */ 134 NULL, /* erxo_scale_context_free */ 135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */ 136 siena_rx_scale_key_set, /* erxo_scale_key_set */ 137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */ 138 siena_rx_prefix_hash, /* erxo_prefix_hash */ 139 #endif 140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */ 141 siena_rx_qpost, /* erxo_qpost */ 142 siena_rx_qpush, /* erxo_qpush */ 143 #if EFSYS_OPT_RX_PACKED_STREAM 144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */ 145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */ 146 #endif 147 siena_rx_qflush, /* erxo_qflush */ 148 siena_rx_qenable, /* erxo_qenable */ 149 siena_rx_qcreate, /* erxo_qcreate */ 150 siena_rx_qdestroy, /* erxo_qdestroy */ 151 }; 152 #endif /* EFSYS_OPT_SIENA */ 153 154 #if EFX_OPTS_EF10() 155 static const efx_rx_ops_t __efx_rx_ef10_ops = { 156 ef10_rx_init, /* erxo_init */ 157 ef10_rx_fini, /* erxo_fini */ 158 #if EFSYS_OPT_RX_SCATTER 159 ef10_rx_scatter_enable, /* erxo_scatter_enable */ 160 #endif 161 #if EFSYS_OPT_RX_SCALE 162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */ 163 ef10_rx_scale_context_free, /* erxo_scale_context_free */ 164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */ 165 ef10_rx_scale_key_set, /* erxo_scale_key_set */ 166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */ 167 ef10_rx_prefix_hash, /* erxo_prefix_hash */ 168 #endif 169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */ 170 ef10_rx_qpost, /* erxo_qpost */ 171 ef10_rx_qpush, /* erxo_qpush */ 172 #if EFSYS_OPT_RX_PACKED_STREAM 173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */ 174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */ 175 #endif 176 ef10_rx_qflush, /* erxo_qflush */ 177 ef10_rx_qenable, /* erxo_qenable */ 178 ef10_rx_qcreate, /* erxo_qcreate */ 179 ef10_rx_qdestroy, /* erxo_qdestroy */ 180 }; 181 #endif /* EFX_OPTS_EF10() */ 182 183 #if EFSYS_OPT_RIVERHEAD 184 static const efx_rx_ops_t __efx_rx_rhead_ops = { 185 rhead_rx_init, /* erxo_init */ 186 rhead_rx_fini, /* erxo_fini */ 187 #if EFSYS_OPT_RX_SCATTER 188 rhead_rx_scatter_enable, /* erxo_scatter_enable */ 189 #endif 190 #if EFSYS_OPT_RX_SCALE 191 rhead_rx_scale_context_alloc, /* erxo_scale_context_alloc */ 192 rhead_rx_scale_context_free, /* erxo_scale_context_free */ 193 rhead_rx_scale_mode_set, /* erxo_scale_mode_set */ 194 rhead_rx_scale_key_set, /* erxo_scale_key_set */ 195 rhead_rx_scale_tbl_set, /* erxo_scale_tbl_set */ 196 rhead_rx_prefix_hash, /* erxo_prefix_hash */ 197 #endif 198 rhead_rx_prefix_pktlen, /* erxo_prefix_pktlen */ 199 rhead_rx_qpost, /* erxo_qpost */ 200 rhead_rx_qpush, /* erxo_qpush */ 201 #if EFSYS_OPT_RX_PACKED_STREAM 202 NULL, /* erxo_qpush_ps_credits */ 203 NULL, /* erxo_qps_packet_info */ 204 #endif 205 rhead_rx_qflush, /* erxo_qflush */ 206 rhead_rx_qenable, /* erxo_qenable */ 207 rhead_rx_qcreate, /* erxo_qcreate */ 208 rhead_rx_qdestroy, /* erxo_qdestroy */ 209 }; 210 #endif /* EFSYS_OPT_RIVERHEAD */ 211 212 213 __checkReturn efx_rc_t 214 efx_rx_init( 215 __inout efx_nic_t *enp) 216 { 217 const efx_rx_ops_t *erxop; 218 efx_rc_t rc; 219 220 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 221 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 222 223 if (!(enp->en_mod_flags & EFX_MOD_EV)) { 224 rc = EINVAL; 225 goto fail1; 226 } 227 228 if (enp->en_mod_flags & EFX_MOD_RX) { 229 rc = EINVAL; 230 goto fail2; 231 } 232 233 switch (enp->en_family) { 234 #if EFSYS_OPT_SIENA 235 case EFX_FAMILY_SIENA: 236 erxop = &__efx_rx_siena_ops; 237 break; 238 #endif /* EFSYS_OPT_SIENA */ 239 240 #if EFSYS_OPT_HUNTINGTON 241 case EFX_FAMILY_HUNTINGTON: 242 erxop = &__efx_rx_ef10_ops; 243 break; 244 #endif /* EFSYS_OPT_HUNTINGTON */ 245 246 #if EFSYS_OPT_MEDFORD 247 case EFX_FAMILY_MEDFORD: 248 erxop = &__efx_rx_ef10_ops; 249 break; 250 #endif /* EFSYS_OPT_MEDFORD */ 251 252 #if EFSYS_OPT_MEDFORD2 253 case EFX_FAMILY_MEDFORD2: 254 erxop = &__efx_rx_ef10_ops; 255 break; 256 #endif /* EFSYS_OPT_MEDFORD2 */ 257 258 #if EFSYS_OPT_RIVERHEAD 259 case EFX_FAMILY_RIVERHEAD: 260 erxop = &__efx_rx_rhead_ops; 261 break; 262 #endif /* EFSYS_OPT_RIVERHEAD */ 263 264 default: 265 EFSYS_ASSERT(0); 266 rc = ENOTSUP; 267 goto fail3; 268 } 269 270 if ((rc = erxop->erxo_init(enp)) != 0) 271 goto fail4; 272 273 enp->en_erxop = erxop; 274 enp->en_mod_flags |= EFX_MOD_RX; 275 return (0); 276 277 fail4: 278 EFSYS_PROBE(fail4); 279 fail3: 280 EFSYS_PROBE(fail3); 281 fail2: 282 EFSYS_PROBE(fail2); 283 fail1: 284 EFSYS_PROBE1(fail1, efx_rc_t, rc); 285 286 enp->en_erxop = NULL; 287 enp->en_mod_flags &= ~EFX_MOD_RX; 288 return (rc); 289 } 290 291 void 292 efx_rx_fini( 293 __in efx_nic_t *enp) 294 { 295 const efx_rx_ops_t *erxop = enp->en_erxop; 296 297 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 298 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 299 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 300 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0); 301 302 erxop->erxo_fini(enp); 303 304 enp->en_erxop = NULL; 305 enp->en_mod_flags &= ~EFX_MOD_RX; 306 } 307 308 #if EFSYS_OPT_RX_SCATTER 309 __checkReturn efx_rc_t 310 efx_rx_scatter_enable( 311 __in efx_nic_t *enp, 312 __in unsigned int buf_size) 313 { 314 const efx_rx_ops_t *erxop = enp->en_erxop; 315 efx_rc_t rc; 316 317 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 318 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 319 320 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0) 321 goto fail1; 322 323 return (0); 324 325 fail1: 326 EFSYS_PROBE1(fail1, efx_rc_t, rc); 327 return (rc); 328 } 329 #endif /* EFSYS_OPT_RX_SCATTER */ 330 331 #if EFSYS_OPT_RX_SCALE 332 __checkReturn efx_rc_t 333 efx_rx_scale_hash_flags_get( 334 __in efx_nic_t *enp, 335 __in efx_rx_hash_alg_t hash_alg, 336 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 337 __in unsigned int max_nflags, 338 __out unsigned int *nflagsp) 339 { 340 efx_nic_cfg_t *encp = &enp->en_nic_cfg; 341 unsigned int nflags = 0; 342 efx_rc_t rc; 343 344 if (flagsp == NULL || nflagsp == NULL) { 345 rc = EINVAL; 346 goto fail1; 347 } 348 349 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) { 350 nflags = 0; 351 goto done; 352 } 353 354 /* Helper to add flags word to flags array without buffer overflow */ 355 #define INSERT_FLAGS(_flags) \ 356 do { \ 357 if (nflags >= max_nflags) { \ 358 rc = E2BIG; \ 359 goto fail2; \ 360 } \ 361 *(flagsp + nflags) = (_flags); \ 362 nflags++; \ 363 \ 364 _NOTE(CONSTANTCONDITION) \ 365 } while (B_FALSE) 366 367 if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) { 368 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE)); 369 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE)); 370 } 371 372 if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) && 373 (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) { 374 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST)); 375 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC)); 376 377 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST)); 378 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC)); 379 380 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE)); 381 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST)); 382 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC)); 383 384 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE)); 385 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST)); 386 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC)); 387 } 388 389 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE)); 390 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE)); 391 392 INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE)); 393 INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE)); 394 395 if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) { 396 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST)); 397 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC)); 398 399 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST)); 400 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC)); 401 402 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE)); 403 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST)); 404 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC)); 405 406 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE)); 407 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST)); 408 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC)); 409 410 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST)); 411 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC)); 412 413 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST)); 414 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC)); 415 } 416 417 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE)); 418 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE)); 419 420 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE)); 421 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE)); 422 423 INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE)); 424 INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE)); 425 426 #undef INSERT_FLAGS 427 428 done: 429 *nflagsp = nflags; 430 return (0); 431 432 fail2: 433 EFSYS_PROBE(fail2); 434 fail1: 435 EFSYS_PROBE1(fail1, efx_rc_t, rc); 436 437 return (rc); 438 } 439 440 __checkReturn efx_rc_t 441 efx_rx_hash_default_support_get( 442 __in efx_nic_t *enp, 443 __out efx_rx_hash_support_t *supportp) 444 { 445 efx_rc_t rc; 446 447 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 448 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 449 450 if (supportp == NULL) { 451 rc = EINVAL; 452 goto fail1; 453 } 454 455 /* 456 * Report the hashing support the client gets by default if it 457 * does not allocate an RSS context itself. 458 */ 459 *supportp = enp->en_hash_support; 460 461 return (0); 462 463 fail1: 464 EFSYS_PROBE1(fail1, efx_rc_t, rc); 465 466 return (rc); 467 } 468 469 __checkReturn efx_rc_t 470 efx_rx_scale_default_support_get( 471 __in efx_nic_t *enp, 472 __out efx_rx_scale_context_type_t *typep) 473 { 474 efx_rc_t rc; 475 476 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 477 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 478 479 if (typep == NULL) { 480 rc = EINVAL; 481 goto fail1; 482 } 483 484 /* 485 * Report the RSS support the client gets by default if it 486 * does not allocate an RSS context itself. 487 */ 488 *typep = enp->en_rss_context_type; 489 490 return (0); 491 492 fail1: 493 EFSYS_PROBE1(fail1, efx_rc_t, rc); 494 495 return (rc); 496 } 497 #endif /* EFSYS_OPT_RX_SCALE */ 498 499 #if EFSYS_OPT_RX_SCALE 500 __checkReturn efx_rc_t 501 efx_rx_scale_context_alloc( 502 __in efx_nic_t *enp, 503 __in efx_rx_scale_context_type_t type, 504 __in uint32_t num_queues, 505 __out uint32_t *rss_contextp) 506 { 507 uint32_t table_nentries = EFX_RSS_TBL_SIZE; 508 const efx_rx_ops_t *erxop = enp->en_erxop; 509 efx_rc_t rc; 510 511 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 512 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 513 514 if (erxop->erxo_scale_context_alloc == NULL) { 515 rc = ENOTSUP; 516 goto fail1; 517 } 518 519 if (type == EFX_RX_SCALE_EVEN_SPREAD) 520 table_nentries = 0; 521 522 if ((rc = erxop->erxo_scale_context_alloc(enp, type, num_queues, 523 table_nentries, rss_contextp)) != 0) { 524 goto fail2; 525 } 526 527 return (0); 528 529 fail2: 530 EFSYS_PROBE(fail2); 531 fail1: 532 EFSYS_PROBE1(fail1, efx_rc_t, rc); 533 return (rc); 534 } 535 #endif /* EFSYS_OPT_RX_SCALE */ 536 537 #if EFSYS_OPT_RX_SCALE 538 __checkReturn efx_rc_t 539 efx_rx_scale_context_alloc_v2( 540 __in efx_nic_t *enp, 541 __in efx_rx_scale_context_type_t type, 542 __in uint32_t num_queues, 543 __in uint32_t table_nentries, 544 __out uint32_t *rss_contextp) 545 { 546 const efx_rx_ops_t *erxop = enp->en_erxop; 547 efx_rc_t rc; 548 549 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 550 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 551 552 if (erxop->erxo_scale_context_alloc == NULL) { 553 rc = ENOTSUP; 554 goto fail1; 555 } 556 557 if ((rc = erxop->erxo_scale_context_alloc(enp, type, 558 num_queues, table_nentries, rss_contextp)) != 0) { 559 goto fail2; 560 } 561 562 return (0); 563 564 fail2: 565 EFSYS_PROBE(fail2); 566 fail1: 567 EFSYS_PROBE1(fail1, efx_rc_t, rc); 568 return (rc); 569 } 570 #endif /* EFSYS_OPT_RX_SCALE */ 571 572 #if EFSYS_OPT_RX_SCALE 573 __checkReturn efx_rc_t 574 efx_rx_scale_context_free( 575 __in efx_nic_t *enp, 576 __in uint32_t rss_context) 577 { 578 const efx_rx_ops_t *erxop = enp->en_erxop; 579 efx_rc_t rc; 580 581 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 582 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 583 584 if (erxop->erxo_scale_context_free == NULL) { 585 rc = ENOTSUP; 586 goto fail1; 587 } 588 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0) 589 goto fail2; 590 591 return (0); 592 593 fail2: 594 EFSYS_PROBE(fail2); 595 fail1: 596 EFSYS_PROBE1(fail1, efx_rc_t, rc); 597 return (rc); 598 } 599 #endif /* EFSYS_OPT_RX_SCALE */ 600 601 #if EFSYS_OPT_RX_SCALE 602 __checkReturn efx_rc_t 603 efx_rx_scale_mode_set( 604 __in efx_nic_t *enp, 605 __in uint32_t rss_context, 606 __in efx_rx_hash_alg_t alg, 607 __in efx_rx_hash_type_t type, 608 __in boolean_t insert) 609 { 610 efx_nic_cfg_t *encp = &enp->en_nic_cfg; 611 const efx_rx_ops_t *erxop = enp->en_erxop; 612 efx_rx_hash_type_t type_check; 613 unsigned int i; 614 efx_rc_t rc; 615 616 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 617 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 618 619 /* 620 * Legacy flags and modern bits cannot be 621 * used at the same time in the hash type. 622 */ 623 if ((type & EFX_RX_HASH_LEGACY_MASK) && 624 (type & ~EFX_RX_HASH_LEGACY_MASK)) { 625 rc = EINVAL; 626 goto fail1; 627 } 628 629 /* 630 * If RSS hash type is represented by additional bits 631 * in the value, the latter need to be verified since 632 * not all bit combinations are valid RSS modes. Also, 633 * depending on the firmware, some valid combinations 634 * may be unsupported. Discern additional bits in the 635 * type value and try to recognise valid combinations. 636 * If some bits remain unrecognised, report the error. 637 */ 638 type_check = type & ~EFX_RX_HASH_LEGACY_MASK; 639 if (type_check != 0) { 640 unsigned int type_flags[EFX_RX_HASH_NFLAGS]; 641 unsigned int type_nflags; 642 643 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags, 644 EFX_ARRAY_SIZE(type_flags), &type_nflags); 645 if (rc != 0) 646 goto fail2; 647 648 for (i = 0; i < type_nflags; ++i) { 649 if ((type_check & type_flags[i]) == type_flags[i]) 650 type_check &= ~(type_flags[i]); 651 } 652 653 if (type_check != 0) { 654 rc = EINVAL; 655 goto fail3; 656 } 657 } 658 659 /* 660 * Translate EFX_RX_HASH() flags to their legacy counterparts 661 * provided that the FW claims no support for additional modes. 662 */ 663 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE) { 664 efx_rx_hash_type_t t_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE) | 665 EFX_RX_HASH(IPV4_TCP, 2TUPLE); 666 efx_rx_hash_type_t t_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE) | 667 EFX_RX_HASH(IPV6_TCP, 2TUPLE); 668 efx_rx_hash_type_t t_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE); 669 efx_rx_hash_type_t t_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE); 670 671 if ((type & t_ipv4) == t_ipv4) 672 type |= EFX_RX_HASH_IPV4; 673 if ((type & t_ipv6) == t_ipv6) 674 type |= EFX_RX_HASH_IPV6; 675 676 if (encp->enc_rx_scale_l4_hash_supported == B_TRUE) { 677 if ((type & t_ipv4_tcp) == t_ipv4_tcp) 678 type |= EFX_RX_HASH_TCPIPV4; 679 if ((type & t_ipv6_tcp) == t_ipv6_tcp) 680 type |= EFX_RX_HASH_TCPIPV6; 681 } 682 683 type &= EFX_RX_HASH_LEGACY_MASK; 684 } 685 686 if (erxop->erxo_scale_mode_set != NULL) { 687 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg, 688 type, insert)) != 0) 689 goto fail4; 690 } 691 692 return (0); 693 694 fail4: 695 EFSYS_PROBE(fail4); 696 fail3: 697 EFSYS_PROBE(fail3); 698 fail2: 699 EFSYS_PROBE(fail2); 700 fail1: 701 EFSYS_PROBE1(fail1, efx_rc_t, rc); 702 return (rc); 703 } 704 #endif /* EFSYS_OPT_RX_SCALE */ 705 706 #if EFSYS_OPT_RX_SCALE 707 __checkReturn efx_rc_t 708 efx_rx_scale_key_set( 709 __in efx_nic_t *enp, 710 __in uint32_t rss_context, 711 __in_ecount(n) uint8_t *key, 712 __in size_t n) 713 { 714 const efx_rx_ops_t *erxop = enp->en_erxop; 715 efx_rc_t rc; 716 717 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 718 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 719 720 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0) 721 goto fail1; 722 723 return (0); 724 725 fail1: 726 EFSYS_PROBE1(fail1, efx_rc_t, rc); 727 728 return (rc); 729 } 730 #endif /* EFSYS_OPT_RX_SCALE */ 731 732 #if EFSYS_OPT_RX_SCALE 733 __checkReturn efx_rc_t 734 efx_rx_scale_tbl_set( 735 __in efx_nic_t *enp, 736 __in uint32_t rss_context, 737 __in_ecount(nentries) unsigned int *table, 738 __in size_t nentries) 739 { 740 const efx_rx_ops_t *erxop = enp->en_erxop; 741 efx_rc_t rc; 742 743 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 744 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 745 746 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, 747 nentries)) != 0) 748 goto fail1; 749 750 return (0); 751 752 fail1: 753 EFSYS_PROBE1(fail1, efx_rc_t, rc); 754 755 return (rc); 756 } 757 #endif /* EFSYS_OPT_RX_SCALE */ 758 759 void 760 efx_rx_qpost( 761 __in efx_rxq_t *erp, 762 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 763 __in size_t size, 764 __in unsigned int ndescs, 765 __in unsigned int completed, 766 __in unsigned int added) 767 { 768 efx_nic_t *enp = erp->er_enp; 769 const efx_rx_ops_t *erxop = enp->en_erxop; 770 771 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 772 EFSYS_ASSERT(erp->er_buf_size == 0 || size == erp->er_buf_size); 773 774 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added); 775 } 776 777 #if EFSYS_OPT_RX_PACKED_STREAM 778 779 void 780 efx_rx_qpush_ps_credits( 781 __in efx_rxq_t *erp) 782 { 783 efx_nic_t *enp = erp->er_enp; 784 const efx_rx_ops_t *erxop = enp->en_erxop; 785 786 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 787 788 erxop->erxo_qpush_ps_credits(erp); 789 } 790 791 __checkReturn uint8_t * 792 efx_rx_qps_packet_info( 793 __in efx_rxq_t *erp, 794 __in uint8_t *buffer, 795 __in uint32_t buffer_length, 796 __in uint32_t current_offset, 797 __out uint16_t *lengthp, 798 __out uint32_t *next_offsetp, 799 __out uint32_t *timestamp) 800 { 801 efx_nic_t *enp = erp->er_enp; 802 const efx_rx_ops_t *erxop = enp->en_erxop; 803 804 return (erxop->erxo_qps_packet_info(erp, buffer, 805 buffer_length, current_offset, lengthp, 806 next_offsetp, timestamp)); 807 } 808 809 #endif /* EFSYS_OPT_RX_PACKED_STREAM */ 810 811 void 812 efx_rx_qpush( 813 __in efx_rxq_t *erp, 814 __in unsigned int added, 815 __inout unsigned int *pushedp) 816 { 817 efx_nic_t *enp = erp->er_enp; 818 const efx_rx_ops_t *erxop = enp->en_erxop; 819 820 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 821 822 erxop->erxo_qpush(erp, added, pushedp); 823 } 824 825 __checkReturn efx_rc_t 826 efx_rx_qflush( 827 __in efx_rxq_t *erp) 828 { 829 efx_nic_t *enp = erp->er_enp; 830 const efx_rx_ops_t *erxop = enp->en_erxop; 831 efx_rc_t rc; 832 833 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 834 835 if ((rc = erxop->erxo_qflush(erp)) != 0) 836 goto fail1; 837 838 return (0); 839 840 fail1: 841 EFSYS_PROBE1(fail1, efx_rc_t, rc); 842 843 return (rc); 844 } 845 846 __checkReturn size_t 847 efx_rxq_size( 848 __in const efx_nic_t *enp, 849 __in unsigned int ndescs) 850 { 851 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); 852 853 return (ndescs * encp->enc_rx_desc_size); 854 } 855 856 __checkReturn unsigned int 857 efx_rxq_nbufs( 858 __in const efx_nic_t *enp, 859 __in unsigned int ndescs) 860 { 861 return (EFX_DIV_ROUND_UP(efx_rxq_size(enp, ndescs), EFX_BUF_SIZE)); 862 } 863 864 void 865 efx_rx_qenable( 866 __in efx_rxq_t *erp) 867 { 868 efx_nic_t *enp = erp->er_enp; 869 const efx_rx_ops_t *erxop = enp->en_erxop; 870 871 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 872 873 erxop->erxo_qenable(erp); 874 } 875 876 static __checkReturn efx_rc_t 877 efx_rx_qcreate_internal( 878 __in efx_nic_t *enp, 879 __in unsigned int index, 880 __in unsigned int label, 881 __in efx_rxq_type_t type, 882 __in_opt const efx_rxq_type_data_t *type_data, 883 __in efsys_mem_t *esmp, 884 __in size_t ndescs, 885 __in uint32_t id, 886 __in unsigned int flags, 887 __in efx_evq_t *eep, 888 __deref_out efx_rxq_t **erpp) 889 { 890 const efx_rx_ops_t *erxop = enp->en_erxop; 891 efx_rxq_t *erp; 892 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); 893 efx_rc_t rc; 894 895 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 896 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 897 898 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit); 899 900 EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs)); 901 EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs)); 902 903 if (index >= encp->enc_rxq_limit) { 904 rc = EINVAL; 905 goto fail1; 906 } 907 908 if (!ISP2(ndescs) || 909 ndescs < encp->enc_rxq_min_ndescs || 910 ndescs > encp->enc_rxq_max_ndescs) { 911 rc = EINVAL; 912 goto fail2; 913 } 914 915 /* Allocate an RXQ object */ 916 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp); 917 918 if (erp == NULL) { 919 rc = ENOMEM; 920 goto fail3; 921 } 922 923 erp->er_magic = EFX_RXQ_MAGIC; 924 erp->er_enp = enp; 925 erp->er_index = index; 926 erp->er_mask = ndescs - 1; 927 erp->er_esmp = esmp; 928 929 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp, 930 ndescs, id, flags, eep, erp)) != 0) 931 goto fail4; 932 933 /* Sanity check queue creation result */ 934 if (flags & EFX_RXQ_FLAG_RSS_HASH) { 935 const efx_rx_prefix_layout_t *erplp = &erp->er_prefix_layout; 936 const efx_rx_prefix_field_info_t *rss_hash_field; 937 938 rss_hash_field = 939 &erplp->erpl_fields[EFX_RX_PREFIX_FIELD_RSS_HASH]; 940 if (rss_hash_field->erpfi_width_bits == 0) 941 goto fail5; 942 } 943 944 enp->en_rx_qcount++; 945 *erpp = erp; 946 947 return (0); 948 949 fail5: 950 EFSYS_PROBE(fail5); 951 952 erxop->erxo_qdestroy(erp); 953 fail4: 954 EFSYS_PROBE(fail4); 955 956 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); 957 fail3: 958 EFSYS_PROBE(fail3); 959 fail2: 960 EFSYS_PROBE(fail2); 961 fail1: 962 EFSYS_PROBE1(fail1, efx_rc_t, rc); 963 964 return (rc); 965 } 966 967 __checkReturn efx_rc_t 968 efx_rx_qcreate( 969 __in efx_nic_t *enp, 970 __in unsigned int index, 971 __in unsigned int label, 972 __in efx_rxq_type_t type, 973 __in size_t buf_size, 974 __in efsys_mem_t *esmp, 975 __in size_t ndescs, 976 __in uint32_t id, 977 __in unsigned int flags, 978 __in efx_evq_t *eep, 979 __deref_out efx_rxq_t **erpp) 980 { 981 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); 982 efx_rxq_type_data_t type_data; 983 efx_rc_t rc; 984 985 if (buf_size > encp->enc_rx_dma_desc_size_max) { 986 rc = EINVAL; 987 goto fail1; 988 } 989 990 memset(&type_data, 0, sizeof (type_data)); 991 992 type_data.ertd_default.ed_buf_size = buf_size; 993 994 return efx_rx_qcreate_internal(enp, index, label, type, &type_data, 995 esmp, ndescs, id, flags, eep, erpp); 996 997 fail1: 998 EFSYS_PROBE1(fail1, efx_rc_t, rc); 999 1000 return (rc); 1001 } 1002 1003 #if EFSYS_OPT_RX_PACKED_STREAM 1004 1005 __checkReturn efx_rc_t 1006 efx_rx_qcreate_packed_stream( 1007 __in efx_nic_t *enp, 1008 __in unsigned int index, 1009 __in unsigned int label, 1010 __in uint32_t ps_buf_size, 1011 __in efsys_mem_t *esmp, 1012 __in size_t ndescs, 1013 __in efx_evq_t *eep, 1014 __deref_out efx_rxq_t **erpp) 1015 { 1016 efx_rxq_type_data_t type_data; 1017 1018 memset(&type_data, 0, sizeof (type_data)); 1019 1020 type_data.ertd_packed_stream.eps_buf_size = ps_buf_size; 1021 1022 return efx_rx_qcreate_internal(enp, index, label, 1023 EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs, 1024 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp); 1025 } 1026 1027 #endif 1028 1029 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 1030 1031 __checkReturn efx_rc_t 1032 efx_rx_qcreate_es_super_buffer( 1033 __in efx_nic_t *enp, 1034 __in unsigned int index, 1035 __in unsigned int label, 1036 __in uint32_t n_bufs_per_desc, 1037 __in uint32_t max_dma_len, 1038 __in uint32_t buf_stride, 1039 __in uint32_t hol_block_timeout, 1040 __in efsys_mem_t *esmp, 1041 __in size_t ndescs, 1042 __in unsigned int flags, 1043 __in efx_evq_t *eep, 1044 __deref_out efx_rxq_t **erpp) 1045 { 1046 efx_rc_t rc; 1047 efx_rxq_type_data_t type_data; 1048 1049 if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) { 1050 rc = EINVAL; 1051 goto fail1; 1052 } 1053 1054 memset(&type_data, 0, sizeof (type_data)); 1055 1056 type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc; 1057 type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len; 1058 type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride; 1059 type_data.ertd_es_super_buffer.eessb_hol_block_timeout = 1060 hol_block_timeout; 1061 1062 rc = efx_rx_qcreate_internal(enp, index, label, 1063 EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs, 1064 0 /* id unused on EF10 */, flags, eep, erpp); 1065 if (rc != 0) 1066 goto fail2; 1067 1068 return (0); 1069 1070 fail2: 1071 EFSYS_PROBE(fail2); 1072 fail1: 1073 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1074 1075 return (rc); 1076 } 1077 1078 #endif 1079 1080 1081 void 1082 efx_rx_qdestroy( 1083 __in efx_rxq_t *erp) 1084 { 1085 efx_nic_t *enp = erp->er_enp; 1086 const efx_rx_ops_t *erxop = enp->en_erxop; 1087 1088 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 1089 1090 EFSYS_ASSERT(enp->en_rx_qcount != 0); 1091 --enp->en_rx_qcount; 1092 1093 erxop->erxo_qdestroy(erp); 1094 1095 /* Free the RXQ object */ 1096 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); 1097 } 1098 1099 __checkReturn efx_rc_t 1100 efx_pseudo_hdr_pkt_length_get( 1101 __in efx_rxq_t *erp, 1102 __in uint8_t *buffer, 1103 __out uint16_t *lengthp) 1104 { 1105 efx_nic_t *enp = erp->er_enp; 1106 const efx_rx_ops_t *erxop = enp->en_erxop; 1107 1108 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 1109 1110 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp)); 1111 } 1112 1113 #if EFSYS_OPT_RX_SCALE 1114 __checkReturn uint32_t 1115 efx_pseudo_hdr_hash_get( 1116 __in efx_rxq_t *erp, 1117 __in efx_rx_hash_alg_t func, 1118 __in uint8_t *buffer) 1119 { 1120 efx_nic_t *enp = erp->er_enp; 1121 const efx_rx_ops_t *erxop = enp->en_erxop; 1122 1123 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 1124 1125 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE); 1126 return (erxop->erxo_prefix_hash(enp, func, buffer)); 1127 } 1128 #endif /* EFSYS_OPT_RX_SCALE */ 1129 1130 __checkReturn efx_rc_t 1131 efx_rx_prefix_get_layout( 1132 __in const efx_rxq_t *erp, 1133 __out efx_rx_prefix_layout_t *erplp) 1134 { 1135 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 1136 1137 *erplp = erp->er_prefix_layout; 1138 1139 return (0); 1140 } 1141 1142 #if EFSYS_OPT_SIENA 1143 1144 static __checkReturn efx_rc_t 1145 siena_rx_init( 1146 __in efx_nic_t *enp) 1147 { 1148 efx_oword_t oword; 1149 unsigned int index; 1150 1151 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); 1152 1153 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0); 1154 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); 1155 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); 1156 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); 1157 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0); 1158 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32); 1159 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); 1160 1161 /* Zero the RSS table */ 1162 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; 1163 index++) { 1164 EFX_ZERO_OWORD(oword); 1165 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL, 1166 index, &oword, B_TRUE); 1167 } 1168 1169 #if EFSYS_OPT_RX_SCALE 1170 /* The RSS key and indirection table are writable. */ 1171 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE; 1172 1173 /* Hardware can insert RX hash with/without RSS */ 1174 enp->en_hash_support = EFX_RX_HASH_AVAILABLE; 1175 #endif /* EFSYS_OPT_RX_SCALE */ 1176 1177 return (0); 1178 } 1179 1180 #if EFSYS_OPT_RX_SCATTER 1181 static __checkReturn efx_rc_t 1182 siena_rx_scatter_enable( 1183 __in efx_nic_t *enp, 1184 __in unsigned int buf_size) 1185 { 1186 unsigned int nbuf32; 1187 efx_oword_t oword; 1188 efx_rc_t rc; 1189 1190 nbuf32 = buf_size / 32; 1191 if ((nbuf32 == 0) || 1192 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) || 1193 ((buf_size % 32) != 0)) { 1194 rc = EINVAL; 1195 goto fail1; 1196 } 1197 1198 if (enp->en_rx_qcount > 0) { 1199 rc = EBUSY; 1200 goto fail2; 1201 } 1202 1203 /* Set scatter buffer size */ 1204 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); 1205 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32); 1206 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); 1207 1208 /* Enable scatter for packets not matching a filter */ 1209 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); 1210 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1); 1211 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); 1212 1213 return (0); 1214 1215 fail2: 1216 EFSYS_PROBE(fail2); 1217 fail1: 1218 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1219 1220 return (rc); 1221 } 1222 #endif /* EFSYS_OPT_RX_SCATTER */ 1223 1224 1225 #define EFX_RX_LFSR_HASH(_enp, _insert) \ 1226 do { \ 1227 efx_oword_t oword; \ 1228 \ 1229 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 1230 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \ 1231 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \ 1232 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \ 1233 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \ 1234 (_insert) ? 1 : 0); \ 1235 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 1236 \ 1237 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \ 1238 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \ 1239 &oword); \ 1240 EFX_SET_OWORD_FIELD(oword, \ 1241 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \ 1242 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \ 1243 &oword); \ 1244 } \ 1245 \ 1246 _NOTE(CONSTANTCONDITION) \ 1247 } while (B_FALSE) 1248 1249 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \ 1250 do { \ 1251 efx_oword_t oword; \ 1252 \ 1253 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 1254 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \ 1255 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \ 1256 (_ip) ? 1 : 0); \ 1257 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \ 1258 (_tcp) ? 0 : 1); \ 1259 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \ 1260 (_insert) ? 1 : 0); \ 1261 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 1262 \ 1263 _NOTE(CONSTANTCONDITION) \ 1264 } while (B_FALSE) 1265 1266 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \ 1267 do { \ 1268 efx_oword_t oword; \ 1269 \ 1270 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \ 1271 EFX_SET_OWORD_FIELD(oword, \ 1272 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \ 1273 EFX_SET_OWORD_FIELD(oword, \ 1274 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \ 1275 EFX_SET_OWORD_FIELD(oword, \ 1276 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \ 1277 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \ 1278 \ 1279 (_rc) = 0; \ 1280 \ 1281 _NOTE(CONSTANTCONDITION) \ 1282 } while (B_FALSE) 1283 1284 1285 #if EFSYS_OPT_RX_SCALE 1286 1287 static __checkReturn efx_rc_t 1288 siena_rx_scale_mode_set( 1289 __in efx_nic_t *enp, 1290 __in uint32_t rss_context, 1291 __in efx_rx_hash_alg_t alg, 1292 __in efx_rx_hash_type_t type, 1293 __in boolean_t insert) 1294 { 1295 efx_rc_t rc; 1296 1297 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) { 1298 rc = EINVAL; 1299 goto fail1; 1300 } 1301 1302 switch (alg) { 1303 case EFX_RX_HASHALG_LFSR: 1304 EFX_RX_LFSR_HASH(enp, insert); 1305 break; 1306 1307 case EFX_RX_HASHALG_TOEPLITZ: 1308 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert, 1309 (type & EFX_RX_HASH_IPV4) ? B_TRUE : B_FALSE, 1310 (type & EFX_RX_HASH_TCPIPV4) ? B_TRUE : B_FALSE); 1311 1312 EFX_RX_TOEPLITZ_IPV6_HASH(enp, 1313 (type & EFX_RX_HASH_IPV6) ? B_TRUE : B_FALSE, 1314 (type & EFX_RX_HASH_TCPIPV6) ? B_TRUE : B_FALSE, 1315 rc); 1316 if (rc != 0) 1317 goto fail2; 1318 1319 break; 1320 1321 default: 1322 rc = EINVAL; 1323 goto fail3; 1324 } 1325 1326 return (0); 1327 1328 fail3: 1329 EFSYS_PROBE(fail3); 1330 fail2: 1331 EFSYS_PROBE(fail2); 1332 fail1: 1333 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1334 1335 EFX_RX_LFSR_HASH(enp, B_FALSE); 1336 1337 return (rc); 1338 } 1339 #endif 1340 1341 #if EFSYS_OPT_RX_SCALE 1342 static __checkReturn efx_rc_t 1343 siena_rx_scale_key_set( 1344 __in efx_nic_t *enp, 1345 __in uint32_t rss_context, 1346 __in_ecount(n) uint8_t *key, 1347 __in size_t n) 1348 { 1349 efx_oword_t oword; 1350 unsigned int byte; 1351 unsigned int offset; 1352 efx_rc_t rc; 1353 1354 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) { 1355 rc = EINVAL; 1356 goto fail1; 1357 } 1358 1359 byte = 0; 1360 1361 /* Write Toeplitz IPv4 hash key */ 1362 EFX_ZERO_OWORD(oword); 1363 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8; 1364 offset > 0 && byte < n; 1365 --offset) 1366 oword.eo_u8[offset - 1] = key[byte++]; 1367 1368 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword); 1369 1370 byte = 0; 1371 1372 /* Verify Toeplitz IPv4 hash key */ 1373 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword); 1374 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8; 1375 offset > 0 && byte < n; 1376 --offset) { 1377 if (oword.eo_u8[offset - 1] != key[byte++]) { 1378 rc = EFAULT; 1379 goto fail2; 1380 } 1381 } 1382 1383 if ((enp->en_features & EFX_FEATURE_IPV6) == 0) 1384 goto done; 1385 1386 byte = 0; 1387 1388 /* Write Toeplitz IPv6 hash key 3 */ 1389 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); 1390 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN + 1391 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8; 1392 offset > 0 && byte < n; 1393 --offset) 1394 oword.eo_u8[offset - 1] = key[byte++]; 1395 1396 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); 1397 1398 /* Write Toeplitz IPv6 hash key 2 */ 1399 EFX_ZERO_OWORD(oword); 1400 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN + 1401 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8; 1402 offset > 0 && byte < n; 1403 --offset) 1404 oword.eo_u8[offset - 1] = key[byte++]; 1405 1406 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword); 1407 1408 /* Write Toeplitz IPv6 hash key 1 */ 1409 EFX_ZERO_OWORD(oword); 1410 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN + 1411 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8; 1412 offset > 0 && byte < n; 1413 --offset) 1414 oword.eo_u8[offset - 1] = key[byte++]; 1415 1416 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword); 1417 1418 byte = 0; 1419 1420 /* Verify Toeplitz IPv6 hash key 3 */ 1421 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); 1422 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN + 1423 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8; 1424 offset > 0 && byte < n; 1425 --offset) { 1426 if (oword.eo_u8[offset - 1] != key[byte++]) { 1427 rc = EFAULT; 1428 goto fail3; 1429 } 1430 } 1431 1432 /* Verify Toeplitz IPv6 hash key 2 */ 1433 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword); 1434 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN + 1435 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8; 1436 offset > 0 && byte < n; 1437 --offset) { 1438 if (oword.eo_u8[offset - 1] != key[byte++]) { 1439 rc = EFAULT; 1440 goto fail4; 1441 } 1442 } 1443 1444 /* Verify Toeplitz IPv6 hash key 1 */ 1445 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword); 1446 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN + 1447 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8; 1448 offset > 0 && byte < n; 1449 --offset) { 1450 if (oword.eo_u8[offset - 1] != key[byte++]) { 1451 rc = EFAULT; 1452 goto fail5; 1453 } 1454 } 1455 1456 done: 1457 return (0); 1458 1459 fail5: 1460 EFSYS_PROBE(fail5); 1461 fail4: 1462 EFSYS_PROBE(fail4); 1463 fail3: 1464 EFSYS_PROBE(fail3); 1465 fail2: 1466 EFSYS_PROBE(fail2); 1467 fail1: 1468 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1469 1470 return (rc); 1471 } 1472 #endif 1473 1474 #if EFSYS_OPT_RX_SCALE 1475 static __checkReturn efx_rc_t 1476 siena_rx_scale_tbl_set( 1477 __in efx_nic_t *enp, 1478 __in uint32_t rss_context, 1479 __in_ecount(nentries) unsigned int *table, 1480 __in size_t nentries) 1481 { 1482 efx_oword_t oword; 1483 int index; 1484 efx_rc_t rc; 1485 1486 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS); 1487 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH)); 1488 1489 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) { 1490 rc = EINVAL; 1491 goto fail1; 1492 } 1493 1494 if (nentries > FR_BZ_RX_INDIRECTION_TBL_ROWS) { 1495 rc = EINVAL; 1496 goto fail2; 1497 } 1498 1499 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) { 1500 uint32_t byte; 1501 1502 /* Calculate the entry to place in the table */ 1503 byte = (nentries > 0) ? (uint32_t)table[index % nentries] : 0; 1504 1505 EFSYS_PROBE2(table, int, index, uint32_t, byte); 1506 1507 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte); 1508 1509 /* Write the table */ 1510 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL, 1511 index, &oword, B_TRUE); 1512 } 1513 1514 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) { 1515 uint32_t byte; 1516 1517 /* Determine if we're starting a new batch */ 1518 byte = (nentries > 0) ? (uint32_t)table[index % nentries] : 0; 1519 1520 /* Read the table */ 1521 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL, 1522 index, &oword, B_TRUE); 1523 1524 /* Verify the entry */ 1525 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) { 1526 rc = EFAULT; 1527 goto fail3; 1528 } 1529 } 1530 1531 return (0); 1532 1533 fail3: 1534 EFSYS_PROBE(fail3); 1535 fail2: 1536 EFSYS_PROBE(fail2); 1537 fail1: 1538 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1539 1540 return (rc); 1541 } 1542 #endif 1543 1544 /* 1545 * Falcon/Siena pseudo-header 1546 * -------------------------- 1547 * 1548 * Receive packets are prefixed by an optional 16 byte pseudo-header. 1549 * The pseudo-header is a byte array of one of the forms: 1550 * 1551 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1552 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT 1553 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL 1554 * 1555 * where: 1556 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian) 1557 * LL.LL LFSR hash (16-bit big-endian) 1558 */ 1559 1560 /* 1561 * Provide Rx prefix layout with Toeplitz hash only since LSFR is 1562 * used by no supported drivers. 1563 * 1564 * Siena does not support Rx prefix choice via MC_CMD_GET_RX_PREFIX_ID 1565 * and query its layout using MC_CMD_QUERY_RX_PREFIX_ID. 1566 */ 1567 static const efx_rx_prefix_layout_t siena_toeplitz_rx_prefix_layout = { 1568 .erpl_id = 0, 1569 .erpl_length = 16, 1570 .erpl_fields = { 1571 [EFX_RX_PREFIX_FIELD_RSS_HASH] = { 12 * 8, 32, B_TRUE }, 1572 } 1573 }; 1574 1575 #if EFSYS_OPT_RX_SCALE 1576 static __checkReturn uint32_t 1577 siena_rx_prefix_hash( 1578 __in efx_nic_t *enp, 1579 __in efx_rx_hash_alg_t func, 1580 __in uint8_t *buffer) 1581 { 1582 _NOTE(ARGUNUSED(enp)) 1583 1584 switch (func) { 1585 case EFX_RX_HASHALG_TOEPLITZ: 1586 return ((buffer[12] << 24) | 1587 (buffer[13] << 16) | 1588 (buffer[14] << 8) | 1589 buffer[15]); 1590 1591 case EFX_RX_HASHALG_LFSR: 1592 return ((buffer[14] << 8) | buffer[15]); 1593 1594 default: 1595 EFSYS_ASSERT(0); 1596 return (0); 1597 } 1598 } 1599 #endif /* EFSYS_OPT_RX_SCALE */ 1600 1601 static __checkReturn efx_rc_t 1602 siena_rx_prefix_pktlen( 1603 __in efx_nic_t *enp, 1604 __in uint8_t *buffer, 1605 __out uint16_t *lengthp) 1606 { 1607 _NOTE(ARGUNUSED(enp, buffer, lengthp)) 1608 1609 /* Not supported by Falcon/Siena hardware */ 1610 EFSYS_ASSERT(0); 1611 return (ENOTSUP); 1612 } 1613 1614 1615 static void 1616 siena_rx_qpost( 1617 __in efx_rxq_t *erp, 1618 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 1619 __in size_t size, 1620 __in unsigned int ndescs, 1621 __in unsigned int completed, 1622 __in unsigned int added) 1623 { 1624 efx_qword_t qword; 1625 unsigned int i; 1626 unsigned int offset; 1627 unsigned int id; 1628 1629 /* The client driver must not overfill the queue */ 1630 EFSYS_ASSERT3U(added - completed + ndescs, <=, 1631 EFX_RXQ_LIMIT(erp->er_mask + 1)); 1632 1633 id = added & (erp->er_mask); 1634 for (i = 0; i < ndescs; i++) { 1635 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index, 1636 unsigned int, id, efsys_dma_addr_t, addrp[i], 1637 size_t, size); 1638 1639 EFX_POPULATE_QWORD_3(qword, 1640 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size), 1641 FSF_AZ_RX_KER_BUF_ADDR_DW0, 1642 (uint32_t)(addrp[i] & 0xffffffff), 1643 FSF_AZ_RX_KER_BUF_ADDR_DW1, 1644 (uint32_t)(addrp[i] >> 32)); 1645 1646 offset = id * sizeof (efx_qword_t); 1647 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword); 1648 1649 id = (id + 1) & (erp->er_mask); 1650 } 1651 } 1652 1653 static void 1654 siena_rx_qpush( 1655 __in efx_rxq_t *erp, 1656 __in unsigned int added, 1657 __inout unsigned int *pushedp) 1658 { 1659 efx_nic_t *enp = erp->er_enp; 1660 unsigned int pushed = *pushedp; 1661 uint32_t wptr; 1662 efx_oword_t oword; 1663 efx_dword_t dword; 1664 1665 /* All descriptors are pushed */ 1666 *pushedp = added; 1667 1668 /* Push the populated descriptors out */ 1669 wptr = added & erp->er_mask; 1670 1671 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr); 1672 1673 /* Only write the third DWORD */ 1674 EFX_POPULATE_DWORD_1(dword, 1675 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3)); 1676 1677 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ 1678 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1, 1679 SIENA_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask); 1680 EFSYS_PIO_WRITE_BARRIER(); 1681 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0, 1682 erp->er_index, &dword, B_FALSE); 1683 } 1684 1685 #if EFSYS_OPT_RX_PACKED_STREAM 1686 static void 1687 siena_rx_qpush_ps_credits( 1688 __in efx_rxq_t *erp) 1689 { 1690 /* Not supported by Siena hardware */ 1691 EFSYS_ASSERT(0); 1692 } 1693 1694 static uint8_t * 1695 siena_rx_qps_packet_info( 1696 __in efx_rxq_t *erp, 1697 __in uint8_t *buffer, 1698 __in uint32_t buffer_length, 1699 __in uint32_t current_offset, 1700 __out uint16_t *lengthp, 1701 __out uint32_t *next_offsetp, 1702 __out uint32_t *timestamp) 1703 { 1704 /* Not supported by Siena hardware */ 1705 EFSYS_ASSERT(0); 1706 1707 return (NULL); 1708 } 1709 #endif /* EFSYS_OPT_RX_PACKED_STREAM */ 1710 1711 static __checkReturn efx_rc_t 1712 siena_rx_qflush( 1713 __in efx_rxq_t *erp) 1714 { 1715 efx_nic_t *enp = erp->er_enp; 1716 efx_oword_t oword; 1717 uint32_t label; 1718 1719 label = erp->er_index; 1720 1721 /* Flush the queue */ 1722 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, 1723 FRF_AZ_RX_FLUSH_DESCQ, label); 1724 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword); 1725 1726 return (0); 1727 } 1728 1729 static void 1730 siena_rx_qenable( 1731 __in efx_rxq_t *erp) 1732 { 1733 efx_nic_t *enp = erp->er_enp; 1734 efx_oword_t oword; 1735 1736 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 1737 1738 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL, 1739 erp->er_index, &oword, B_TRUE); 1740 1741 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0); 1742 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0); 1743 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1); 1744 1745 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, 1746 erp->er_index, &oword, B_TRUE); 1747 } 1748 1749 static __checkReturn efx_rc_t 1750 siena_rx_qcreate( 1751 __in efx_nic_t *enp, 1752 __in unsigned int index, 1753 __in unsigned int label, 1754 __in efx_rxq_type_t type, 1755 __in_opt const efx_rxq_type_data_t *type_data, 1756 __in efsys_mem_t *esmp, 1757 __in size_t ndescs, 1758 __in uint32_t id, 1759 __in unsigned int flags, 1760 __in efx_evq_t *eep, 1761 __in efx_rxq_t *erp) 1762 { 1763 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1764 efx_oword_t oword; 1765 uint32_t size; 1766 boolean_t jumbo = B_FALSE; 1767 efx_rc_t rc; 1768 1769 _NOTE(ARGUNUSED(esmp)) 1770 1771 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == 1772 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH)); 1773 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS); 1774 1775 for (size = 0; 1776 (1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs; 1777 size++) 1778 if ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs) 1779 break; 1780 if (id + (1 << size) >= encp->enc_buftbl_limit) { 1781 rc = EINVAL; 1782 goto fail1; 1783 } 1784 1785 switch (type) { 1786 case EFX_RXQ_TYPE_DEFAULT: 1787 erp->er_buf_size = type_data->ertd_default.ed_buf_size; 1788 /* 1789 * Ignore EFX_RXQ_FLAG_RSS_HASH since if RSS hash is calculated 1790 * it is always delivered from HW in the pseudo-header. 1791 */ 1792 break; 1793 1794 default: 1795 rc = EINVAL; 1796 goto fail2; 1797 } 1798 1799 #if EFSYS_OPT_RX_SCATTER 1800 #define SUPPORTED_RXQ_FLAGS EFX_RXQ_FLAG_SCATTER 1801 #else 1802 #define SUPPORTED_RXQ_FLAGS EFX_RXQ_FLAG_NONE 1803 #endif 1804 /* Reject flags for unsupported queue features */ 1805 if ((flags & ~SUPPORTED_RXQ_FLAGS) != 0) { 1806 rc = EINVAL; 1807 goto fail3; 1808 } 1809 #undef SUPPORTED_RXQ_FLAGS 1810 1811 if (flags & EFX_RXQ_FLAG_SCATTER) 1812 jumbo = B_TRUE; 1813 1814 /* Set up the new descriptor queue */ 1815 EFX_POPULATE_OWORD_7(oword, 1816 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id, 1817 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index, 1818 FRF_AZ_RX_DESCQ_OWNER_ID, 0, 1819 FRF_AZ_RX_DESCQ_LABEL, label, 1820 FRF_AZ_RX_DESCQ_SIZE, size, 1821 FRF_AZ_RX_DESCQ_TYPE, 0, 1822 FRF_AZ_RX_DESCQ_JUMBO, jumbo); 1823 1824 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, 1825 erp->er_index, &oword, B_TRUE); 1826 1827 erp->er_prefix_layout = siena_toeplitz_rx_prefix_layout; 1828 1829 return (0); 1830 1831 fail3: 1832 EFSYS_PROBE(fail3); 1833 fail2: 1834 EFSYS_PROBE(fail2); 1835 fail1: 1836 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1837 1838 return (rc); 1839 } 1840 1841 static void 1842 siena_rx_qdestroy( 1843 __in efx_rxq_t *erp) 1844 { 1845 efx_nic_t *enp = erp->er_enp; 1846 efx_oword_t oword; 1847 1848 /* Purge descriptor queue */ 1849 EFX_ZERO_OWORD(oword); 1850 1851 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, 1852 erp->er_index, &oword, B_TRUE); 1853 } 1854 1855 static void 1856 siena_rx_fini( 1857 __in efx_nic_t *enp) 1858 { 1859 _NOTE(ARGUNUSED(enp)) 1860 } 1861 1862 #endif /* EFSYS_OPT_SIENA */ 1863 1864 static __checkReturn boolean_t 1865 efx_rx_prefix_layout_fields_match( 1866 __in const efx_rx_prefix_field_info_t *erpfip1, 1867 __in const efx_rx_prefix_field_info_t *erpfip2) 1868 { 1869 if (erpfip1->erpfi_offset_bits != erpfip2->erpfi_offset_bits) 1870 return (B_FALSE); 1871 1872 if (erpfip1->erpfi_width_bits != erpfip2->erpfi_width_bits) 1873 return (B_FALSE); 1874 1875 if (erpfip1->erpfi_big_endian != erpfip2->erpfi_big_endian) 1876 return (B_FALSE); 1877 1878 return (B_TRUE); 1879 } 1880 1881 __checkReturn uint32_t 1882 efx_rx_prefix_layout_check( 1883 __in const efx_rx_prefix_layout_t *available, 1884 __in const efx_rx_prefix_layout_t *wanted) 1885 { 1886 uint32_t result = 0; 1887 unsigned int i; 1888 1889 EFX_STATIC_ASSERT(EFX_RX_PREFIX_NFIELDS < sizeof (result) * 8); 1890 for (i = 0; i < EFX_RX_PREFIX_NFIELDS; ++i) { 1891 /* Skip the field if driver does not want to use it */ 1892 if (wanted->erpl_fields[i].erpfi_width_bits == 0) 1893 continue; 1894 1895 if (efx_rx_prefix_layout_fields_match( 1896 &available->erpl_fields[i], 1897 &wanted->erpl_fields[i]) == B_FALSE) 1898 result |= (1U << i); 1899 } 1900 1901 return (result); 1902 } 1903