1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_EF10_REGS_H 8 #define _SYS_EFX_EF10_REGS_H 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /************************************************************************** 15 * NOTE: the line below marks the start of the autogenerated section 16 * EF10 registers and descriptors 17 * 18 ************************************************************************** 19 */ 20 21 /* 22 * BIU_HW_REV_ID_REG(32bit): 23 * 24 */ 25 26 #define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 27 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 28 #define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face 29 30 31 #define ERF_DZ_HW_REV_ID_LBN 0 32 #define ERF_DZ_HW_REV_ID_WIDTH 32 33 34 35 /* 36 * BIU_MC_SFT_STATUS_REG(32bit): 37 * 38 */ 39 40 #define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 41 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 42 #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 43 #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 44 #define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face 45 46 47 #define ERF_DZ_MC_SFT_STATUS_LBN 0 48 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 49 50 51 /* 52 * BIU_INT_ISR_REG(32bit): 53 * 54 */ 55 56 #define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 57 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 58 #define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 59 60 61 #define ERF_DZ_ISR_REG_LBN 0 62 #define ERF_DZ_ISR_REG_WIDTH 32 63 64 65 /* 66 * MC_DB_LWRD_REG(32bit): 67 * 68 */ 69 70 #define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 71 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 72 #define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 73 74 75 #define ERF_DZ_MC_DOORBELL_L_LBN 0 76 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 77 78 79 /* 80 * MC_DB_HWRD_REG(32bit): 81 * 82 */ 83 84 #define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 85 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 86 #define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 87 88 89 #define ERF_DZ_MC_DOORBELL_H_LBN 0 90 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 91 92 93 /* 94 * EVQ_RPTR_REG(32bit): 95 * 96 */ 97 98 #define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 99 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 100 #define ER_DZ_EVQ_RPTR_REG_STEP 8192 101 #define ER_DZ_EVQ_RPTR_REG_ROWS 2048 102 #define ER_DZ_EVQ_RPTR_REG_RESET 0x0 103 104 105 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 106 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 107 #define ERF_DZ_EVQ_RPTR_LBN 0 108 #define ERF_DZ_EVQ_RPTR_WIDTH 15 109 110 111 /* 112 * EVQ_RPTR_REG_64K(32bit): 113 * 114 */ 115 116 #define ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400 117 /* medford2a0=pf_dbell_bar */ 118 #define ER_FZ_EVQ_RPTR_REG_64K_STEP 65536 119 #define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048 120 #define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0 121 122 123 #define ERF_FZ_EVQ_RPTR_VLD_LBN 15 124 #define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 125 #define ERF_FZ_EVQ_RPTR_LBN 0 126 #define ERF_FZ_EVQ_RPTR_WIDTH 15 127 128 129 /* 130 * EVQ_RPTR_REG_16K(32bit): 131 * 132 */ 133 134 #define ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400 135 /* medford2a0=pf_dbell_bar */ 136 #define ER_FZ_EVQ_RPTR_REG_16K_STEP 16384 137 #define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048 138 #define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0 139 140 141 /* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */ 142 /* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */ 143 /* defined as ERF_FZ_EVQ_RPTR_LBN 0; */ 144 /* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */ 145 146 147 /* 148 * EVQ_TMR_REG_64K(32bit): 149 * 150 */ 151 152 #define ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420 153 /* medford2a0=pf_dbell_bar */ 154 #define ER_FZ_EVQ_TMR_REG_64K_STEP 65536 155 #define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048 156 #define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0 157 158 159 #define ERF_FZ_TC_TMR_REL_VAL_LBN 16 160 #define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 161 #define ERF_FZ_TC_TIMER_MODE_LBN 14 162 #define ERF_FZ_TC_TIMER_MODE_WIDTH 2 163 #define ERF_FZ_TC_TIMER_VAL_LBN 0 164 #define ERF_FZ_TC_TIMER_VAL_WIDTH 14 165 166 167 /* 168 * EVQ_TMR_REG_16K(32bit): 169 * 170 */ 171 172 #define ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420 173 /* medford2a0=pf_dbell_bar */ 174 #define ER_FZ_EVQ_TMR_REG_16K_STEP 16384 175 #define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048 176 #define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0 177 178 179 /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ 180 /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ 181 /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */ 182 /* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */ 183 /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */ 184 /* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */ 185 186 187 /* 188 * EVQ_TMR_REG(32bit): 189 * 190 */ 191 192 #define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 193 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 194 #define ER_DZ_EVQ_TMR_REG_STEP 8192 195 #define ER_DZ_EVQ_TMR_REG_ROWS 2048 196 #define ER_DZ_EVQ_TMR_REG_RESET 0x0 197 198 199 /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ 200 /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ 201 #define ERF_DZ_TC_TIMER_MODE_LBN 14 202 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 203 #define ERF_DZ_TC_TIMER_VAL_LBN 0 204 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 205 206 207 /* 208 * RX_DESC_UPD_REG_16K(32bit): 209 * 210 */ 211 212 #define ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830 213 /* medford2a0=pf_dbell_bar */ 214 #define ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384 215 #define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048 216 #define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0 217 218 219 #define ERF_FZ_RX_DESC_WPTR_LBN 0 220 #define ERF_FZ_RX_DESC_WPTR_WIDTH 12 221 222 223 /* 224 * RX_DESC_UPD_REG(32bit): 225 * 226 */ 227 228 #define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 229 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 230 #define ER_DZ_RX_DESC_UPD_REG_STEP 8192 231 #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 232 #define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 233 234 235 #define ERF_DZ_RX_DESC_WPTR_LBN 0 236 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 237 238 239 /* 240 * RX_DESC_UPD_REG_64K(32bit): 241 * 242 */ 243 244 #define ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830 245 /* medford2a0=pf_dbell_bar */ 246 #define ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536 247 #define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048 248 #define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0 249 250 251 /* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */ 252 /* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */ 253 254 255 /* 256 * TX_DESC_UPD_REG_64K(96bit): 257 * 258 */ 259 260 #define ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10 261 /* medford2a0=pf_dbell_bar */ 262 #define ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536 263 #define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048 264 #define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0 265 266 267 #define ERF_FZ_RSVD_LBN 76 268 #define ERF_FZ_RSVD_WIDTH 20 269 #define ERF_FZ_TX_DESC_WPTR_LBN 64 270 #define ERF_FZ_TX_DESC_WPTR_WIDTH 12 271 #define ERF_FZ_TX_DESC_HWORD_LBN 32 272 #define ERF_FZ_TX_DESC_HWORD_WIDTH 32 273 #define ERF_FZ_TX_DESC_LWORD_LBN 0 274 #define ERF_FZ_TX_DESC_LWORD_WIDTH 32 275 276 277 /* 278 * TX_DESC_UPD_REG_16K(96bit): 279 * 280 */ 281 282 #define ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10 283 /* medford2a0=pf_dbell_bar */ 284 #define ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384 285 #define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048 286 #define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0 287 288 289 /* defined as ERF_FZ_RSVD_LBN 76; */ 290 /* defined as ERF_FZ_RSVD_WIDTH 20 */ 291 /* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */ 292 /* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */ 293 /* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */ 294 /* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */ 295 /* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */ 296 /* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */ 297 298 299 /* 300 * TX_DESC_UPD_REG(96bit): 301 * 302 */ 303 304 #define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 305 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 306 #define ER_DZ_TX_DESC_UPD_REG_STEP 8192 307 #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 308 #define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 309 310 311 #define ERF_DZ_RSVD_LBN 76 312 #define ERF_DZ_RSVD_WIDTH 20 313 #define ERF_DZ_TX_DESC_WPTR_LBN 64 314 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 315 #define ERF_DZ_TX_DESC_HWORD_LBN 32 316 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 317 #define ERF_DZ_TX_DESC_LWORD_LBN 0 318 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 319 320 321 /* ES_DRIVER_EV */ 322 #define ESF_DZ_DRV_CODE_LBN 60 323 #define ESF_DZ_DRV_CODE_WIDTH 4 324 #define ESF_DZ_DRV_SUB_CODE_LBN 56 325 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 326 #define ESE_DZ_DRV_TIMER_EV 3 327 #define ESE_DZ_DRV_START_UP_EV 2 328 #define ESE_DZ_DRV_WAKE_UP_EV 1 329 #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 330 #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 331 #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 332 #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 333 #define ESF_DZ_DRV_SUB_DATA_LBN 0 334 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 335 #define ESF_DZ_DRV_EVQ_ID_LBN 0 336 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 337 #define ESF_DZ_DRV_TMR_ID_LBN 0 338 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 339 340 341 /* ES_EVENT_ENTRY */ 342 #define ESF_DZ_EV_CODE_LBN 60 343 #define ESF_DZ_EV_CODE_WIDTH 4 344 #define ESE_DZ_EV_CODE_MCDI_EV 12 345 #define ESE_DZ_EV_CODE_DRIVER_EV 5 346 #define ESE_DZ_EV_CODE_TX_EV 2 347 #define ESE_DZ_EV_CODE_RX_EV 0 348 #define ESE_DZ_OTHER other 349 #define ESF_DZ_EV_DATA_DW0_LBN 0 350 #define ESF_DZ_EV_DATA_DW0_WIDTH 32 351 #define ESF_DZ_EV_DATA_DW1_LBN 32 352 #define ESF_DZ_EV_DATA_DW1_WIDTH 28 353 #define ESF_DZ_EV_DATA_LBN 0 354 #define ESF_DZ_EV_DATA_WIDTH 60 355 356 357 /* ES_MC_EVENT */ 358 #define ESF_DZ_MC_CODE_LBN 60 359 #define ESF_DZ_MC_CODE_WIDTH 4 360 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 361 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 362 #define ESF_DZ_MC_DROP_EVENT_LBN 58 363 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 364 #define ESF_DZ_MC_SOFT_DW0_LBN 0 365 #define ESF_DZ_MC_SOFT_DW0_WIDTH 32 366 #define ESF_DZ_MC_SOFT_DW1_LBN 32 367 #define ESF_DZ_MC_SOFT_DW1_WIDTH 26 368 #define ESF_DZ_MC_SOFT_LBN 0 369 #define ESF_DZ_MC_SOFT_WIDTH 58 370 371 372 /* ES_RX_EVENT */ 373 #define ESF_DZ_RX_CODE_LBN 60 374 #define ESF_DZ_RX_CODE_WIDTH 4 375 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 376 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 377 #define ESF_DZ_RX_DROP_EVENT_LBN 58 378 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 379 #define ESF_DD_RX_EV_RSVD2_LBN 54 380 #define ESF_DD_RX_EV_RSVD2_WIDTH 4 381 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 382 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 383 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 384 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 385 #define ESF_EZ_RX_EV_RSVD2_LBN 54 386 #define ESF_EZ_RX_EV_RSVD2_WIDTH 2 387 #define ESF_DZ_RX_EV_SOFT2_LBN 52 388 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 389 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 390 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 391 #define ESF_DE_RX_L4_CLASS_LBN 45 392 #define ESF_DE_RX_L4_CLASS_WIDTH 3 393 #define ESE_DE_L4_CLASS_RSVD7 7 394 #define ESE_DE_L4_CLASS_RSVD6 6 395 #define ESE_DE_L4_CLASS_RSVD5 5 396 #define ESE_DE_L4_CLASS_RSVD4 4 397 #define ESE_DE_L4_CLASS_RSVD3 3 398 #define ESE_DE_L4_CLASS_UDP 2 399 #define ESE_DE_L4_CLASS_TCP 1 400 #define ESE_DE_L4_CLASS_UNKNOWN 0 401 #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 402 #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 403 #define ESF_FZ_RX_L4_CLASS_LBN 45 404 #define ESF_FZ_RX_L4_CLASS_WIDTH 2 405 #define ESE_FZ_L4_CLASS_RSVD3 3 406 #define ESE_FZ_L4_CLASS_UDP 2 407 #define ESE_FZ_L4_CLASS_TCP 1 408 #define ESE_FZ_L4_CLASS_UNKNOWN 0 409 #define ESF_DZ_RX_L3_CLASS_LBN 42 410 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 411 #define ESE_DZ_L3_CLASS_RSVD7 7 412 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 413 #define ESE_DZ_L3_CLASS_ARP 5 414 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 415 #define ESE_DZ_L3_CLASS_FCOE 3 416 #define ESE_DZ_L3_CLASS_IP6 2 417 #define ESE_DZ_L3_CLASS_IP4 1 418 #define ESE_DZ_L3_CLASS_UNKNOWN 0 419 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 420 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 421 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 422 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 423 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 424 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 425 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 426 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 427 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 428 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 429 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 430 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 431 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 432 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 433 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 434 #define ESF_DZ_RX_MAC_CLASS_LBN 35 435 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 436 #define ESE_DZ_MAC_CLASS_MCAST 1 437 #define ESE_DZ_MAC_CLASS_UCAST 0 438 #define ESF_DD_RX_EV_SOFT1_LBN 32 439 #define ESF_DD_RX_EV_SOFT1_WIDTH 3 440 #define ESF_EZ_RX_EV_SOFT1_LBN 34 441 #define ESF_EZ_RX_EV_SOFT1_WIDTH 1 442 #define ESF_EZ_RX_ENCAP_HDR_LBN 32 443 #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 444 #define ESE_EZ_ENCAP_HDR_GRE 2 445 #define ESE_EZ_ENCAP_HDR_VXLAN 1 446 #define ESE_EZ_ENCAP_HDR_NONE 0 447 #define ESF_DD_RX_EV_RSVD1_LBN 30 448 #define ESF_DD_RX_EV_RSVD1_WIDTH 2 449 #define ESF_EZ_RX_EV_RSVD1_LBN 31 450 #define ESF_EZ_RX_EV_RSVD1_WIDTH 1 451 #define ESF_EZ_RX_ABORT_LBN 30 452 #define ESF_EZ_RX_ABORT_WIDTH 1 453 #define ESF_DZ_RX_ECC_ERR_LBN 29 454 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 455 #define ESF_DZ_RX_TRUNC_ERR_LBN 29 456 #define ESF_DZ_RX_TRUNC_ERR_WIDTH 1 457 #define ESF_DZ_RX_CRC1_ERR_LBN 28 458 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 459 #define ESF_DZ_RX_CRC0_ERR_LBN 27 460 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 461 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 462 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 463 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 464 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 465 #define ESF_DZ_RX_ECRC_ERR_LBN 24 466 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 467 #define ESF_DZ_RX_QLABEL_LBN 16 468 #define ESF_DZ_RX_QLABEL_WIDTH 5 469 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 470 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 471 #define ESF_DZ_RX_CONT_LBN 14 472 #define ESF_DZ_RX_CONT_WIDTH 1 473 #define ESF_DZ_RX_BYTES_LBN 0 474 #define ESF_DZ_RX_BYTES_WIDTH 14 475 476 477 /* ES_RX_KER_DESC */ 478 #define ESF_DZ_RX_KER_RESERVED_LBN 62 479 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 480 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 481 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 482 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0 483 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 484 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32 485 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16 486 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 487 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 488 489 490 /* ES_TX_CSUM_TSTAMP_DESC */ 491 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 492 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 493 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 494 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 495 #define ESE_DZ_TX_OPTION_DESC_TSO 7 496 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 497 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 498 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 499 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 500 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 501 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 502 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 503 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 504 #define ESF_DZ_TX_TIMESTAMP_LBN 5 505 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 506 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 507 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 508 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 509 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 510 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 511 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 512 #define ESE_DZ_TX_OPTION_CRC_FCOE 1 513 #define ESE_DZ_TX_OPTION_CRC_OFF 0 514 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 515 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 516 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 517 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 518 519 520 /* ES_TX_EVENT */ 521 #define ESF_DZ_TX_CODE_LBN 60 522 #define ESF_DZ_TX_CODE_WIDTH 4 523 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 524 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 525 #define ESF_DZ_TX_DROP_EVENT_LBN 58 526 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 527 #define ESF_DD_TX_EV_RSVD_LBN 48 528 #define ESF_DD_TX_EV_RSVD_WIDTH 10 529 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 530 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 531 #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 532 #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 533 #define ESF_EZ_TX_EV_RSVD_LBN 48 534 #define ESF_EZ_TX_EV_RSVD_WIDTH 8 535 #define ESF_DZ_TX_SOFT2_LBN 32 536 #define ESF_DZ_TX_SOFT2_WIDTH 16 537 #define ESF_DD_TX_SOFT1_LBN 24 538 #define ESF_DD_TX_SOFT1_WIDTH 8 539 #define ESF_EZ_TX_CAN_MERGE_LBN 31 540 #define ESF_EZ_TX_CAN_MERGE_WIDTH 1 541 #define ESF_EZ_TX_SOFT1_LBN 24 542 #define ESF_EZ_TX_SOFT1_WIDTH 7 543 #define ESF_DZ_TX_QLABEL_LBN 16 544 #define ESF_DZ_TX_QLABEL_WIDTH 5 545 #define ESF_DZ_TX_DESCR_INDX_LBN 0 546 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 547 548 549 /* ES_TX_KER_DESC */ 550 #define ESF_DZ_TX_KER_TYPE_LBN 63 551 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 552 #define ESF_DZ_TX_KER_CONT_LBN 62 553 #define ESF_DZ_TX_KER_CONT_WIDTH 1 554 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 555 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 556 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 557 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 558 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 559 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 560 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 561 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 562 563 564 /* ES_TX_PIO_DESC */ 565 #define ESF_DZ_TX_PIO_TYPE_LBN 63 566 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 567 #define ESF_DZ_TX_PIO_OPT_LBN 60 568 #define ESF_DZ_TX_PIO_OPT_WIDTH 3 569 #define ESF_DZ_TX_PIO_CONT_LBN 59 570 #define ESF_DZ_TX_PIO_CONT_WIDTH 1 571 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 572 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 573 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 574 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 575 576 577 /* ES_TX_TSO_DESC */ 578 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 579 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 580 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 581 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 582 #define ESE_DZ_TX_OPTION_DESC_TSO 7 583 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 584 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 585 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 586 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 587 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 588 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 589 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 590 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 591 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 592 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 593 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 594 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 595 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 596 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 597 598 599 /* ES_TX_TSO_V2_DESC_A */ 600 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 601 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 602 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 603 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 604 #define ESE_DZ_TX_OPTION_DESC_TSO 7 605 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 606 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 607 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 608 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 609 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 610 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 611 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 612 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 613 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 614 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 615 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 616 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 617 618 619 /* ES_TX_TSO_V2_DESC_B */ 620 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 621 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 622 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 623 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 624 #define ESE_DZ_TX_OPTION_DESC_TSO 7 625 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 626 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 627 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 628 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 629 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 630 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 631 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 632 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 633 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 634 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 635 #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 636 #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 637 638 639 /* ES_TX_VLAN_DESC */ 640 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 641 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 642 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 643 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 644 #define ESE_DZ_TX_OPTION_DESC_TSO 7 645 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 646 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 647 #define ESF_DZ_TX_VLAN_OP_LBN 32 648 #define ESF_DZ_TX_VLAN_OP_WIDTH 2 649 #define ESF_DZ_TX_VLAN_TAG2_LBN 16 650 #define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 651 #define ESF_DZ_TX_VLAN_TAG1_LBN 0 652 #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 653 654 655 /************************************************************************* 656 * NOTE: the comment line above marks the end of the autogenerated section 657 */ 658 659 /* 660 * The workaround for bug 35388 requires multiplexing writes through 661 * the ERF_DZ_TX_DESC_WPTR address. 662 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 663 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 664 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 665 */ 666 #define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) 667 #define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP 668 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 669 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 670 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 671 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 672 #define ERF_DD_EVQ_IND_RPTR_LBN 0 673 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 674 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 675 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 676 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 677 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 678 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 679 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 680 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 681 682 /* Packed stream magic doorbell command */ 683 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_LBN 11 684 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_WIDTH 1 685 686 #define ERF_DZ_RX_DESC_MAGIC_CMD_LBN 8 687 #define ERF_DZ_RX_DESC_MAGIC_CMD_WIDTH 3 688 #define ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS 0 689 690 #define ERF_DZ_RX_DESC_MAGIC_DATA_LBN 0 691 #define ERF_DZ_RX_DESC_MAGIC_DATA_WIDTH 8 692 693 /* Packed stream RX packet prefix */ 694 #define ES_DZ_PS_RX_PREFIX_TSTAMP_LBN 0 695 #define ES_DZ_PS_RX_PREFIX_TSTAMP_WIDTH 32 696 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_LBN 32 697 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_WIDTH 16 698 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_LBN 48 699 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_WIDTH 16 700 701 /* Equal stride super-buffer RX packet prefix (see SF-119419-TC) */ 702 #define ES_EZ_ESSB_RX_PREFIX_LEN 8 703 #define ES_EZ_ESSB_RX_PREFIX_DATA_LEN_LBN 0 704 #define ES_EZ_ESSB_RX_PREFIX_DATA_LEN_WIDTH 16 705 #define ES_EZ_ESSB_RX_PREFIX_MARK_LBN 16 706 #define ES_EZ_ESSB_RX_PREFIX_MARK_WIDTH 8 707 #define ES_EZ_ESSB_RX_PREFIX_HASH_VALID_LBN 28 708 #define ES_EZ_ESSB_RX_PREFIX_HASH_VALID_WIDTH 1 709 #define ES_EZ_ESSB_RX_PREFIX_MARK_VALID_LBN 29 710 #define ES_EZ_ESSB_RX_PREFIX_MARK_VALID_WIDTH 1 711 #define ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_LBN 30 712 #define ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_WIDTH 1 713 #define ES_EZ_ESSB_RX_PREFIX_HASH_LBN 32 714 #define ES_EZ_ESSB_RX_PREFIX_HASH_WIDTH 32 715 716 /* 717 * An extra flag for the packed stream mode, 718 * signalling the start of a new buffer 719 */ 720 #define ESF_DZ_RX_EV_ROTATE_LBN 53 721 #define ESF_DZ_RX_EV_ROTATE_WIDTH 1 722 723 #ifdef __cplusplus 724 } 725 #endif 726 727 #endif /* _SYS_EFX_EF10_REGS_H */ 728