1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2020 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 10 11 __checkReturn efx_rc_t 12 efx_family( 13 __in uint16_t venid, 14 __in uint16_t devid, 15 __out efx_family_t *efp, 16 __out unsigned int *membarp) 17 { 18 if (venid == EFX_PCI_VENID_SFC) { 19 switch (devid) { 20 #if EFSYS_OPT_SIENA 21 case EFX_PCI_DEVID_SIENA_F1_UNINIT: 22 /* 23 * Hardware default for PF0 of uninitialised Siena. 24 * manftest must be able to cope with this device id. 25 */ 26 case EFX_PCI_DEVID_BETHPAGE: 27 case EFX_PCI_DEVID_SIENA: 28 *efp = EFX_FAMILY_SIENA; 29 *membarp = EFX_MEM_BAR_SIENA; 30 return (0); 31 #endif /* EFSYS_OPT_SIENA */ 32 33 #if EFSYS_OPT_HUNTINGTON 34 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT: 35 /* 36 * Hardware default for PF0 of uninitialised Huntington. 37 * manftest must be able to cope with this device id. 38 */ 39 case EFX_PCI_DEVID_FARMINGDALE: 40 case EFX_PCI_DEVID_GREENPORT: 41 *efp = EFX_FAMILY_HUNTINGTON; 42 *membarp = EFX_MEM_BAR_HUNTINGTON_PF; 43 return (0); 44 45 case EFX_PCI_DEVID_FARMINGDALE_VF: 46 case EFX_PCI_DEVID_GREENPORT_VF: 47 *efp = EFX_FAMILY_HUNTINGTON; 48 *membarp = EFX_MEM_BAR_HUNTINGTON_VF; 49 return (0); 50 #endif /* EFSYS_OPT_HUNTINGTON */ 51 52 #if EFSYS_OPT_MEDFORD 53 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT: 54 /* 55 * Hardware default for PF0 of uninitialised Medford. 56 * manftest must be able to cope with this device id. 57 */ 58 case EFX_PCI_DEVID_MEDFORD: 59 *efp = EFX_FAMILY_MEDFORD; 60 *membarp = EFX_MEM_BAR_MEDFORD_PF; 61 return (0); 62 63 case EFX_PCI_DEVID_MEDFORD_VF: 64 *efp = EFX_FAMILY_MEDFORD; 65 *membarp = EFX_MEM_BAR_MEDFORD_VF; 66 return (0); 67 #endif /* EFSYS_OPT_MEDFORD */ 68 69 #if EFSYS_OPT_MEDFORD2 70 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT: 71 /* 72 * Hardware default for PF0 of uninitialised Medford2. 73 * manftest must be able to cope with this device id. 74 */ 75 case EFX_PCI_DEVID_MEDFORD2: 76 case EFX_PCI_DEVID_MEDFORD2_VF: 77 *efp = EFX_FAMILY_MEDFORD2; 78 *membarp = EFX_MEM_BAR_MEDFORD2; 79 return (0); 80 #endif /* EFSYS_OPT_MEDFORD2 */ 81 82 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */ 83 default: 84 break; 85 } 86 } 87 88 if (venid == EFX_PCI_VENID_XILINX) { 89 switch (devid) { 90 #if EFSYS_OPT_RIVERHEAD 91 case EFX_PCI_DEVID_RIVERHEAD: 92 case EFX_PCI_DEVID_RIVERHEAD_VF: 93 *efp = EFX_FAMILY_RIVERHEAD; 94 *membarp = EFX_MEM_BAR_RIVERHEAD; 95 return (0); 96 #endif /* EFSYS_OPT_RIVERHEAD */ 97 default: 98 break; 99 } 100 } 101 102 *efp = EFX_FAMILY_INVALID; 103 return (ENOTSUP); 104 } 105 106 #if EFSYS_OPT_PCI 107 108 __checkReturn efx_rc_t 109 efx_family_probe_bar( 110 __in uint16_t venid, 111 __in uint16_t devid, 112 __in efsys_pci_config_t *espcp, 113 __in const efx_pci_ops_t *epop, 114 __out efx_family_t *efp, 115 __out efx_bar_region_t *ebrp) 116 { 117 efx_rc_t rc; 118 unsigned int membar; 119 120 if (venid == EFX_PCI_VENID_XILINX) { 121 switch (devid) { 122 #if EFSYS_OPT_RIVERHEAD 123 case EFX_PCI_DEVID_RIVERHEAD: 124 case EFX_PCI_DEVID_RIVERHEAD_VF: 125 rc = rhead_pci_nic_membar_lookup(espcp, epop, ebrp); 126 if (rc == 0) 127 *efp = EFX_FAMILY_RIVERHEAD; 128 129 return (rc); 130 #endif /* EFSYS_OPT_RIVERHEAD */ 131 default: 132 break; 133 } 134 } 135 136 rc = efx_family(venid, devid, efp, &membar); 137 if (rc == 0) { 138 ebrp->ebr_type = EFX_BAR_TYPE_MEM; 139 ebrp->ebr_index = membar; 140 ebrp->ebr_offset = 0; 141 ebrp->ebr_length = 0; 142 } 143 144 return (rc); 145 } 146 147 #endif /* EFSYS_OPT_PCI */ 148 149 #if EFSYS_OPT_SIENA 150 151 static const efx_nic_ops_t __efx_nic_siena_ops = { 152 siena_nic_probe, /* eno_probe */ 153 NULL, /* eno_board_cfg */ 154 NULL, /* eno_set_drv_limits */ 155 siena_nic_reset, /* eno_reset */ 156 siena_nic_init, /* eno_init */ 157 NULL, /* eno_get_vi_pool */ 158 NULL, /* eno_get_bar_region */ 159 NULL, /* eno_hw_unavailable */ 160 NULL, /* eno_set_hw_unavailable */ 161 #if EFSYS_OPT_DIAG 162 siena_nic_register_test, /* eno_register_test */ 163 #endif /* EFSYS_OPT_DIAG */ 164 siena_nic_fini, /* eno_fini */ 165 siena_nic_unprobe, /* eno_unprobe */ 166 }; 167 168 #endif /* EFSYS_OPT_SIENA */ 169 170 #if EFSYS_OPT_HUNTINGTON 171 172 static const efx_nic_ops_t __efx_nic_hunt_ops = { 173 ef10_nic_probe, /* eno_probe */ 174 hunt_board_cfg, /* eno_board_cfg */ 175 ef10_nic_set_drv_limits, /* eno_set_drv_limits */ 176 ef10_nic_reset, /* eno_reset */ 177 ef10_nic_init, /* eno_init */ 178 ef10_nic_get_vi_pool, /* eno_get_vi_pool */ 179 ef10_nic_get_bar_region, /* eno_get_bar_region */ 180 ef10_nic_hw_unavailable, /* eno_hw_unavailable */ 181 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */ 182 #if EFSYS_OPT_DIAG 183 ef10_nic_register_test, /* eno_register_test */ 184 #endif /* EFSYS_OPT_DIAG */ 185 ef10_nic_fini, /* eno_fini */ 186 ef10_nic_unprobe, /* eno_unprobe */ 187 }; 188 189 #endif /* EFSYS_OPT_HUNTINGTON */ 190 191 #if EFSYS_OPT_MEDFORD 192 193 static const efx_nic_ops_t __efx_nic_medford_ops = { 194 ef10_nic_probe, /* eno_probe */ 195 medford_board_cfg, /* eno_board_cfg */ 196 ef10_nic_set_drv_limits, /* eno_set_drv_limits */ 197 ef10_nic_reset, /* eno_reset */ 198 ef10_nic_init, /* eno_init */ 199 ef10_nic_get_vi_pool, /* eno_get_vi_pool */ 200 ef10_nic_get_bar_region, /* eno_get_bar_region */ 201 ef10_nic_hw_unavailable, /* eno_hw_unavailable */ 202 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */ 203 #if EFSYS_OPT_DIAG 204 ef10_nic_register_test, /* eno_register_test */ 205 #endif /* EFSYS_OPT_DIAG */ 206 ef10_nic_fini, /* eno_fini */ 207 ef10_nic_unprobe, /* eno_unprobe */ 208 }; 209 210 #endif /* EFSYS_OPT_MEDFORD */ 211 212 #if EFSYS_OPT_MEDFORD2 213 214 static const efx_nic_ops_t __efx_nic_medford2_ops = { 215 ef10_nic_probe, /* eno_probe */ 216 medford2_board_cfg, /* eno_board_cfg */ 217 ef10_nic_set_drv_limits, /* eno_set_drv_limits */ 218 ef10_nic_reset, /* eno_reset */ 219 ef10_nic_init, /* eno_init */ 220 ef10_nic_get_vi_pool, /* eno_get_vi_pool */ 221 ef10_nic_get_bar_region, /* eno_get_bar_region */ 222 ef10_nic_hw_unavailable, /* eno_hw_unavailable */ 223 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */ 224 #if EFSYS_OPT_DIAG 225 ef10_nic_register_test, /* eno_register_test */ 226 #endif /* EFSYS_OPT_DIAG */ 227 ef10_nic_fini, /* eno_fini */ 228 ef10_nic_unprobe, /* eno_unprobe */ 229 }; 230 231 #endif /* EFSYS_OPT_MEDFORD2 */ 232 233 #if EFSYS_OPT_RIVERHEAD 234 235 static const efx_nic_ops_t __efx_nic_riverhead_ops = { 236 rhead_nic_probe, /* eno_probe */ 237 rhead_board_cfg, /* eno_board_cfg */ 238 rhead_nic_set_drv_limits, /* eno_set_drv_limits */ 239 rhead_nic_reset, /* eno_reset */ 240 rhead_nic_init, /* eno_init */ 241 rhead_nic_get_vi_pool, /* eno_get_vi_pool */ 242 rhead_nic_get_bar_region, /* eno_get_bar_region */ 243 rhead_nic_hw_unavailable, /* eno_hw_unavailable */ 244 rhead_nic_set_hw_unavailable, /* eno_set_hw_unavailable */ 245 #if EFSYS_OPT_DIAG 246 rhead_nic_register_test, /* eno_register_test */ 247 #endif /* EFSYS_OPT_DIAG */ 248 rhead_nic_fini, /* eno_fini */ 249 rhead_nic_unprobe, /* eno_unprobe */ 250 }; 251 252 #endif /* EFSYS_OPT_RIVERHEAD */ 253 254 255 __checkReturn efx_rc_t 256 efx_nic_create( 257 __in efx_family_t family, 258 __in efsys_identifier_t *esip, 259 __in efsys_bar_t *esbp, 260 __in uint32_t fcw_offset, 261 __in efsys_lock_t *eslp, 262 __deref_out efx_nic_t **enpp) 263 { 264 efx_nic_t *enp; 265 efx_rc_t rc; 266 267 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID); 268 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES); 269 270 /* Allocate a NIC object */ 271 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp); 272 273 if (enp == NULL) { 274 rc = ENOMEM; 275 goto fail1; 276 } 277 278 enp->en_magic = EFX_NIC_MAGIC; 279 280 switch (family) { 281 #if EFSYS_OPT_SIENA 282 case EFX_FAMILY_SIENA: 283 enp->en_enop = &__efx_nic_siena_ops; 284 enp->en_features = 285 EFX_FEATURE_IPV6 | 286 EFX_FEATURE_LFSR_HASH_INSERT | 287 EFX_FEATURE_LINK_EVENTS | 288 EFX_FEATURE_PERIODIC_MAC_STATS | 289 EFX_FEATURE_MCDI | 290 EFX_FEATURE_LOOKAHEAD_SPLIT | 291 EFX_FEATURE_MAC_HEADER_FILTERS | 292 EFX_FEATURE_TX_SRC_FILTERS; 293 break; 294 #endif /* EFSYS_OPT_SIENA */ 295 296 #if EFSYS_OPT_HUNTINGTON 297 case EFX_FAMILY_HUNTINGTON: 298 enp->en_enop = &__efx_nic_hunt_ops; 299 enp->en_features = 300 EFX_FEATURE_IPV6 | 301 EFX_FEATURE_LINK_EVENTS | 302 EFX_FEATURE_PERIODIC_MAC_STATS | 303 EFX_FEATURE_MCDI | 304 EFX_FEATURE_MAC_HEADER_FILTERS | 305 EFX_FEATURE_MCDI_DMA | 306 EFX_FEATURE_PIO_BUFFERS | 307 EFX_FEATURE_FW_ASSISTED_TSO | 308 EFX_FEATURE_FW_ASSISTED_TSO_V2 | 309 EFX_FEATURE_PACKED_STREAM | 310 EFX_FEATURE_TXQ_CKSUM_OP_DESC; 311 break; 312 #endif /* EFSYS_OPT_HUNTINGTON */ 313 314 #if EFSYS_OPT_MEDFORD 315 case EFX_FAMILY_MEDFORD: 316 enp->en_enop = &__efx_nic_medford_ops; 317 /* 318 * FW_ASSISTED_TSO omitted as Medford only supports firmware 319 * assisted TSO version 2, not the v1 scheme used on Huntington. 320 */ 321 enp->en_features = 322 EFX_FEATURE_IPV6 | 323 EFX_FEATURE_LINK_EVENTS | 324 EFX_FEATURE_PERIODIC_MAC_STATS | 325 EFX_FEATURE_MCDI | 326 EFX_FEATURE_MAC_HEADER_FILTERS | 327 EFX_FEATURE_MCDI_DMA | 328 EFX_FEATURE_PIO_BUFFERS | 329 EFX_FEATURE_FW_ASSISTED_TSO_V2 | 330 EFX_FEATURE_PACKED_STREAM | 331 EFX_FEATURE_TXQ_CKSUM_OP_DESC; 332 break; 333 #endif /* EFSYS_OPT_MEDFORD */ 334 335 #if EFSYS_OPT_MEDFORD2 336 case EFX_FAMILY_MEDFORD2: 337 enp->en_enop = &__efx_nic_medford2_ops; 338 enp->en_features = 339 EFX_FEATURE_IPV6 | 340 EFX_FEATURE_LINK_EVENTS | 341 EFX_FEATURE_PERIODIC_MAC_STATS | 342 EFX_FEATURE_MCDI | 343 EFX_FEATURE_MAC_HEADER_FILTERS | 344 EFX_FEATURE_MCDI_DMA | 345 EFX_FEATURE_PIO_BUFFERS | 346 EFX_FEATURE_FW_ASSISTED_TSO_V2 | 347 EFX_FEATURE_PACKED_STREAM | 348 EFX_FEATURE_TXQ_CKSUM_OP_DESC; 349 break; 350 #endif /* EFSYS_OPT_MEDFORD2 */ 351 352 #if EFSYS_OPT_RIVERHEAD 353 case EFX_FAMILY_RIVERHEAD: 354 enp->en_enop = &__efx_nic_riverhead_ops; 355 enp->en_features = 356 EFX_FEATURE_IPV6 | 357 EFX_FEATURE_LINK_EVENTS | 358 EFX_FEATURE_PERIODIC_MAC_STATS | 359 EFX_FEATURE_MCDI | 360 EFX_FEATURE_MAC_HEADER_FILTERS | 361 EFX_FEATURE_MCDI_DMA; 362 enp->en_arch.ef10.ena_fcw_base = fcw_offset; 363 break; 364 #endif /* EFSYS_OPT_RIVERHEAD */ 365 366 default: 367 rc = ENOTSUP; 368 goto fail2; 369 } 370 371 if ((family != EFX_FAMILY_RIVERHEAD) && (fcw_offset != 0)) { 372 rc = EINVAL; 373 goto fail3; 374 } 375 376 enp->en_family = family; 377 enp->en_esip = esip; 378 enp->en_esbp = esbp; 379 enp->en_eslp = eslp; 380 381 *enpp = enp; 382 383 return (0); 384 385 fail3: 386 EFSYS_PROBE(fail3); 387 fail2: 388 EFSYS_PROBE(fail2); 389 390 enp->en_magic = 0; 391 392 /* Free the NIC object */ 393 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); 394 395 fail1: 396 EFSYS_PROBE1(fail1, efx_rc_t, rc); 397 398 return (rc); 399 } 400 401 __checkReturn efx_rc_t 402 efx_nic_probe( 403 __in efx_nic_t *enp, 404 __in efx_fw_variant_t efv) 405 { 406 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 407 const efx_nic_ops_t *enop; 408 efx_rc_t rc; 409 410 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 411 #if EFSYS_OPT_MCDI 412 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 413 #endif /* EFSYS_OPT_MCDI */ 414 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE)); 415 416 /* Ensure FW variant codes match with MC_CMD_FW codes */ 417 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED == 418 MC_CMD_FW_FULL_FEATURED); 419 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY == 420 MC_CMD_FW_LOW_LATENCY); 421 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM == 422 MC_CMD_FW_PACKED_STREAM); 423 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE == 424 MC_CMD_FW_HIGH_TX_RATE); 425 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 == 426 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1); 427 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE == 428 MC_CMD_FW_RULES_ENGINE); 429 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK == 430 MC_CMD_FW_DPDK); 431 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE == 432 (int)MC_CMD_FW_DONT_CARE); 433 434 enop = enp->en_enop; 435 enp->efv = efv; 436 437 if ((rc = enop->eno_probe(enp)) != 0) 438 goto fail1; 439 440 encp->enc_features = enp->en_features; 441 442 if ((rc = efx_phy_probe(enp)) != 0) 443 goto fail2; 444 445 enp->en_mod_flags |= EFX_MOD_PROBE; 446 447 return (0); 448 449 fail2: 450 EFSYS_PROBE(fail2); 451 452 enop->eno_unprobe(enp); 453 454 fail1: 455 EFSYS_PROBE1(fail1, efx_rc_t, rc); 456 457 return (rc); 458 } 459 460 __checkReturn efx_rc_t 461 efx_nic_set_drv_limits( 462 __inout efx_nic_t *enp, 463 __in efx_drv_limits_t *edlp) 464 { 465 const efx_nic_ops_t *enop = enp->en_enop; 466 efx_rc_t rc; 467 468 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 469 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 470 471 if (enop->eno_set_drv_limits != NULL) { 472 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0) 473 goto fail1; 474 } 475 476 return (0); 477 478 fail1: 479 EFSYS_PROBE1(fail1, efx_rc_t, rc); 480 481 return (rc); 482 } 483 484 __checkReturn efx_rc_t 485 efx_nic_set_drv_version( 486 __inout efx_nic_t *enp, 487 __in_ecount(length) char const *verp, 488 __in size_t length) 489 { 490 efx_rc_t rc; 491 492 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 493 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE)); 494 495 /* 496 * length is the string content length in bytes. 497 * Accept any content which fits into the version 498 * buffer, excluding the last byte. This is reserved 499 * for an appended NUL terminator. 500 */ 501 if (length >= sizeof (enp->en_drv_version)) { 502 rc = E2BIG; 503 goto fail1; 504 } 505 506 (void) memset(enp->en_drv_version, 0, 507 sizeof (enp->en_drv_version)); 508 memcpy(enp->en_drv_version, verp, length); 509 510 return (0); 511 512 fail1: 513 EFSYS_PROBE1(fail1, efx_rc_t, rc); 514 515 return (rc); 516 } 517 518 519 __checkReturn efx_rc_t 520 efx_nic_get_bar_region( 521 __in efx_nic_t *enp, 522 __in efx_nic_region_t region, 523 __out uint32_t *offsetp, 524 __out size_t *sizep) 525 { 526 const efx_nic_ops_t *enop = enp->en_enop; 527 efx_rc_t rc; 528 529 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 530 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 531 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 532 533 if (enop->eno_get_bar_region == NULL) { 534 rc = ENOTSUP; 535 goto fail1; 536 } 537 if ((rc = (enop->eno_get_bar_region)(enp, 538 region, offsetp, sizep)) != 0) { 539 goto fail2; 540 } 541 542 return (0); 543 544 fail2: 545 EFSYS_PROBE(fail2); 546 547 fail1: 548 EFSYS_PROBE1(fail1, efx_rc_t, rc); 549 550 return (rc); 551 } 552 553 554 __checkReturn efx_rc_t 555 efx_nic_get_vi_pool( 556 __in efx_nic_t *enp, 557 __out uint32_t *evq_countp, 558 __out uint32_t *rxq_countp, 559 __out uint32_t *txq_countp) 560 { 561 const efx_nic_ops_t *enop = enp->en_enop; 562 efx_nic_cfg_t *encp = &enp->en_nic_cfg; 563 efx_rc_t rc; 564 565 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 566 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 567 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 568 569 if (enop->eno_get_vi_pool != NULL) { 570 uint32_t vi_count = 0; 571 572 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0) 573 goto fail1; 574 575 *evq_countp = vi_count; 576 *rxq_countp = vi_count; 577 *txq_countp = vi_count; 578 } else { 579 /* Use NIC limits as default value */ 580 *evq_countp = encp->enc_evq_limit; 581 *rxq_countp = encp->enc_rxq_limit; 582 *txq_countp = encp->enc_txq_limit; 583 } 584 585 return (0); 586 587 fail1: 588 EFSYS_PROBE1(fail1, efx_rc_t, rc); 589 590 return (rc); 591 } 592 593 594 __checkReturn efx_rc_t 595 efx_nic_init( 596 __in efx_nic_t *enp) 597 { 598 const efx_nic_ops_t *enop = enp->en_enop; 599 efx_rc_t rc; 600 601 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 602 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 603 604 if (enp->en_mod_flags & EFX_MOD_NIC) { 605 rc = EINVAL; 606 goto fail1; 607 } 608 609 if ((rc = enop->eno_init(enp)) != 0) 610 goto fail2; 611 612 enp->en_mod_flags |= EFX_MOD_NIC; 613 614 return (0); 615 616 fail2: 617 EFSYS_PROBE(fail2); 618 fail1: 619 EFSYS_PROBE1(fail1, efx_rc_t, rc); 620 621 return (rc); 622 } 623 624 void 625 efx_nic_fini( 626 __in efx_nic_t *enp) 627 { 628 const efx_nic_ops_t *enop = enp->en_enop; 629 630 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 631 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); 632 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC); 633 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); 634 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 635 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 636 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 637 638 enop->eno_fini(enp); 639 640 enp->en_mod_flags &= ~EFX_MOD_NIC; 641 } 642 643 void 644 efx_nic_unprobe( 645 __in efx_nic_t *enp) 646 { 647 const efx_nic_ops_t *enop = enp->en_enop; 648 649 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 650 #if EFSYS_OPT_MCDI 651 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 652 #endif /* EFSYS_OPT_MCDI */ 653 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 654 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 655 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); 656 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 657 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 658 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 659 660 efx_phy_unprobe(enp); 661 662 enop->eno_unprobe(enp); 663 664 enp->en_mod_flags &= ~EFX_MOD_PROBE; 665 } 666 667 void 668 efx_nic_destroy( 669 __in efx_nic_t *enp) 670 { 671 efsys_identifier_t *esip = enp->en_esip; 672 673 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 674 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); 675 676 enp->en_family = EFX_FAMILY_INVALID; 677 enp->en_esip = NULL; 678 enp->en_esbp = NULL; 679 enp->en_eslp = NULL; 680 681 enp->en_enop = NULL; 682 683 enp->en_magic = 0; 684 685 /* Free the NIC object */ 686 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); 687 } 688 689 __checkReturn efx_rc_t 690 efx_nic_reset( 691 __in efx_nic_t *enp) 692 { 693 const efx_nic_ops_t *enop = enp->en_enop; 694 unsigned int mod_flags; 695 efx_rc_t rc; 696 697 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 698 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); 699 /* 700 * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL 701 * (which we do not reset here) must have been shut down or never 702 * initialized. 703 * 704 * A rule of thumb here is: If the controller or MC reboots, is *any* 705 * state lost. If it's lost and needs reapplying, then the module 706 * *must* not be initialised during the reset. 707 */ 708 mod_flags = enp->en_mod_flags; 709 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM | 710 EFX_MOD_VPD | EFX_MOD_MON); 711 #if EFSYS_OPT_TUNNEL 712 mod_flags &= ~EFX_MOD_TUNNEL; 713 #endif /* EFSYS_OPT_TUNNEL */ 714 EFSYS_ASSERT3U(mod_flags, ==, 0); 715 if (mod_flags != 0) { 716 rc = EINVAL; 717 goto fail1; 718 } 719 720 if ((rc = enop->eno_reset(enp)) != 0) 721 goto fail2; 722 723 return (0); 724 725 fail2: 726 EFSYS_PROBE(fail2); 727 fail1: 728 EFSYS_PROBE1(fail1, efx_rc_t, rc); 729 730 return (rc); 731 } 732 733 const efx_nic_cfg_t * 734 efx_nic_cfg_get( 735 __in const efx_nic_t *enp) 736 { 737 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 738 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 739 740 return (&(enp->en_nic_cfg)); 741 } 742 743 __checkReturn efx_rc_t 744 efx_nic_get_fw_version( 745 __in efx_nic_t *enp, 746 __out efx_nic_fw_info_t *enfip) 747 { 748 uint16_t mc_fw_version[4]; 749 efx_rc_t rc; 750 751 if (enfip == NULL) { 752 rc = EINVAL; 753 goto fail1; 754 } 755 756 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 757 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 758 759 /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */ 760 EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID == 761 MC_CMD_GET_CAPABILITIES_OUT_RXDP); 762 EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID == 763 MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY); 764 EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID == 765 MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM); 766 EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID == 767 MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE); 768 EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID == 769 MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK); 770 771 rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL); 772 if (rc != 0) 773 goto fail2; 774 775 rc = efx_mcdi_get_capabilities(enp, NULL, 776 &enfip->enfi_rx_dpcpu_fw_id, 777 &enfip->enfi_tx_dpcpu_fw_id, 778 NULL, NULL); 779 if (rc == 0) { 780 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE; 781 } else if (rc == ENOTSUP) { 782 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE; 783 enfip->enfi_rx_dpcpu_fw_id = 0; 784 enfip->enfi_tx_dpcpu_fw_id = 0; 785 } else { 786 goto fail3; 787 } 788 789 memcpy(enfip->enfi_mc_fw_version, mc_fw_version, 790 sizeof (mc_fw_version)); 791 792 return (0); 793 794 fail3: 795 EFSYS_PROBE(fail3); 796 fail2: 797 EFSYS_PROBE(fail2); 798 fail1: 799 EFSYS_PROBE1(fail1, efx_rc_t, rc); 800 801 return (rc); 802 } 803 804 __checkReturn boolean_t 805 efx_nic_hw_unavailable( 806 __in efx_nic_t *enp) 807 { 808 const efx_nic_ops_t *enop = enp->en_enop; 809 810 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 811 /* NOTE: can be used by MCDI before NIC probe */ 812 813 if (enop->eno_hw_unavailable != NULL) { 814 if ((enop->eno_hw_unavailable)(enp) != B_FALSE) 815 goto unavail; 816 } 817 818 return (B_FALSE); 819 820 unavail: 821 return (B_TRUE); 822 } 823 824 void 825 efx_nic_set_hw_unavailable( 826 __in efx_nic_t *enp) 827 { 828 const efx_nic_ops_t *enop = enp->en_enop; 829 830 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 831 832 if (enop->eno_set_hw_unavailable != NULL) 833 enop->eno_set_hw_unavailable(enp); 834 } 835 836 837 #if EFSYS_OPT_DIAG 838 839 __checkReturn efx_rc_t 840 efx_nic_register_test( 841 __in efx_nic_t *enp) 842 { 843 const efx_nic_ops_t *enop = enp->en_enop; 844 efx_rc_t rc; 845 846 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 847 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 848 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 849 850 if ((rc = enop->eno_register_test(enp)) != 0) 851 goto fail1; 852 853 return (0); 854 855 fail1: 856 EFSYS_PROBE1(fail1, efx_rc_t, rc); 857 858 return (rc); 859 } 860 861 #endif /* EFSYS_OPT_DIAG */ 862 863 #if EFSYS_OPT_LOOPBACK 864 865 extern void 866 efx_loopback_mask( 867 __in efx_loopback_kind_t loopback_kind, 868 __out efx_qword_t *maskp) 869 { 870 efx_qword_t mask; 871 872 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS); 873 EFSYS_ASSERT(maskp != NULL); 874 875 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */ 876 #define LOOPBACK_CHECK(_mcdi, _efx) \ 877 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx) 878 879 LOOPBACK_CHECK(NONE, OFF); 880 LOOPBACK_CHECK(DATA, DATA); 881 LOOPBACK_CHECK(GMAC, GMAC); 882 LOOPBACK_CHECK(XGMII, XGMII); 883 LOOPBACK_CHECK(XGXS, XGXS); 884 LOOPBACK_CHECK(XAUI, XAUI); 885 LOOPBACK_CHECK(GMII, GMII); 886 LOOPBACK_CHECK(SGMII, SGMII); 887 LOOPBACK_CHECK(XGBR, XGBR); 888 LOOPBACK_CHECK(XFI, XFI); 889 LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR); 890 LOOPBACK_CHECK(GMII_FAR, GMII_FAR); 891 LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR); 892 LOOPBACK_CHECK(XFI_FAR, XFI_FAR); 893 LOOPBACK_CHECK(GPHY, GPHY); 894 LOOPBACK_CHECK(PHYXS, PHY_XS); 895 LOOPBACK_CHECK(PCS, PCS); 896 LOOPBACK_CHECK(PMAPMD, PMA_PMD); 897 LOOPBACK_CHECK(XPORT, XPORT); 898 LOOPBACK_CHECK(XGMII_WS, XGMII_WS); 899 LOOPBACK_CHECK(XAUI_WS, XAUI_WS); 900 LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR); 901 LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR); 902 LOOPBACK_CHECK(GMII_WS, GMII_WS); 903 LOOPBACK_CHECK(XFI_WS, XFI_WS); 904 LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR); 905 LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS); 906 LOOPBACK_CHECK(PMA_INT, PMA_INT); 907 LOOPBACK_CHECK(SD_NEAR, SD_NEAR); 908 LOOPBACK_CHECK(SD_FAR, SD_FAR); 909 LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS); 910 LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS); 911 LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS); 912 LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS); 913 LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS); 914 LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR); 915 LOOPBACK_CHECK(DATA_WS, DATA_WS); 916 LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK); 917 #undef LOOPBACK_CHECK 918 919 /* Build bitmask of possible loopback types */ 920 EFX_ZERO_QWORD(mask); 921 922 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) || 923 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { 924 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF); 925 } 926 927 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) || 928 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { 929 /* 930 * The "MAC" grouping has historically been used by drivers to 931 * mean loopbacks supported by on-chip hardware. Keep that 932 * meaning here, and include on-chip PHY layer loopbacks. 933 */ 934 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA); 935 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC); 936 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII); 937 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS); 938 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI); 939 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII); 940 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII); 941 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR); 942 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI); 943 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR); 944 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR); 945 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR); 946 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR); 947 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT); 948 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR); 949 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR); 950 } 951 952 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) || 953 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { 954 /* 955 * The "PHY" grouping has historically been used by drivers to 956 * mean loopbacks supported by off-chip hardware. Keep that 957 * meaning here. 958 */ 959 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY); 960 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS); 961 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS); 962 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD); 963 } 964 965 *maskp = mask; 966 } 967 968 __checkReturn efx_rc_t 969 efx_mcdi_get_loopback_modes( 970 __in efx_nic_t *enp) 971 { 972 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 973 efx_mcdi_req_t req; 974 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN, 975 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN); 976 efx_qword_t mask; 977 efx_qword_t modes; 978 efx_rc_t rc; 979 980 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES; 981 req.emr_in_buf = payload; 982 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN; 983 req.emr_out_buf = payload; 984 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN; 985 986 efx_mcdi_execute(enp, &req); 987 988 if (req.emr_rc != 0) { 989 rc = req.emr_rc; 990 goto fail1; 991 } 992 993 if (req.emr_out_length_used < 994 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST + 995 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) { 996 rc = EMSGSIZE; 997 goto fail2; 998 } 999 1000 /* 1001 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree 1002 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link(). 1003 */ 1004 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask); 1005 1006 EFX_AND_QWORD(mask, 1007 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED)); 1008 1009 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M); 1010 EFX_AND_QWORD(modes, mask); 1011 encp->enc_loopback_types[EFX_LINK_100FDX] = modes; 1012 1013 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G); 1014 EFX_AND_QWORD(modes, mask); 1015 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes; 1016 1017 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G); 1018 EFX_AND_QWORD(modes, mask); 1019 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes; 1020 1021 if (req.emr_out_length_used >= 1022 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST + 1023 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) { 1024 /* Response includes 40G loopback modes */ 1025 modes = *MCDI_OUT2(req, efx_qword_t, 1026 GET_LOOPBACK_MODES_OUT_40G); 1027 EFX_AND_QWORD(modes, mask); 1028 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes; 1029 } 1030 1031 if (req.emr_out_length_used >= 1032 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST + 1033 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) { 1034 /* Response includes 25G loopback modes */ 1035 modes = *MCDI_OUT2(req, efx_qword_t, 1036 GET_LOOPBACK_MODES_OUT_V2_25G); 1037 EFX_AND_QWORD(modes, mask); 1038 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes; 1039 } 1040 1041 if (req.emr_out_length_used >= 1042 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST + 1043 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) { 1044 /* Response includes 50G loopback modes */ 1045 modes = *MCDI_OUT2(req, efx_qword_t, 1046 GET_LOOPBACK_MODES_OUT_V2_50G); 1047 EFX_AND_QWORD(modes, mask); 1048 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes; 1049 } 1050 1051 if (req.emr_out_length_used >= 1052 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST + 1053 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) { 1054 /* Response includes 100G loopback modes */ 1055 modes = *MCDI_OUT2(req, efx_qword_t, 1056 GET_LOOPBACK_MODES_OUT_V2_100G); 1057 EFX_AND_QWORD(modes, mask); 1058 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes; 1059 } 1060 1061 EFX_ZERO_QWORD(modes); 1062 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF); 1063 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]); 1064 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]); 1065 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]); 1066 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]); 1067 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]); 1068 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]); 1069 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]); 1070 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes; 1071 1072 return (0); 1073 1074 fail2: 1075 EFSYS_PROBE(fail2); 1076 fail1: 1077 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1078 1079 return (rc); 1080 } 1081 1082 #endif /* EFSYS_OPT_LOOPBACK */ 1083 1084 __checkReturn efx_rc_t 1085 efx_nic_calculate_pcie_link_bandwidth( 1086 __in uint32_t pcie_link_width, 1087 __in uint32_t pcie_link_gen, 1088 __out uint32_t *bandwidth_mbpsp) 1089 { 1090 uint32_t lane_bandwidth; 1091 uint32_t total_bandwidth; 1092 efx_rc_t rc; 1093 1094 if ((pcie_link_width == 0) || (pcie_link_width > 16) || 1095 !ISP2(pcie_link_width)) { 1096 rc = EINVAL; 1097 goto fail1; 1098 } 1099 1100 switch (pcie_link_gen) { 1101 case EFX_PCIE_LINK_SPEED_GEN1: 1102 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */ 1103 lane_bandwidth = 2000; 1104 break; 1105 case EFX_PCIE_LINK_SPEED_GEN2: 1106 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */ 1107 lane_bandwidth = 4000; 1108 break; 1109 case EFX_PCIE_LINK_SPEED_GEN3: 1110 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */ 1111 lane_bandwidth = 7877; 1112 break; 1113 default: 1114 rc = EINVAL; 1115 goto fail2; 1116 } 1117 1118 total_bandwidth = lane_bandwidth * pcie_link_width; 1119 *bandwidth_mbpsp = total_bandwidth; 1120 1121 return (0); 1122 1123 fail2: 1124 EFSYS_PROBE(fail2); 1125 fail1: 1126 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1127 1128 return (rc); 1129 } 1130 1131 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 1132 1133 __checkReturn efx_rc_t 1134 efx_nic_get_fw_subvariant( 1135 __in efx_nic_t *enp, 1136 __out efx_nic_fw_subvariant_t *subvariantp) 1137 { 1138 efx_rc_t rc; 1139 uint32_t value; 1140 1141 rc = efx_mcdi_get_nic_global(enp, 1142 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value); 1143 if (rc != 0) 1144 goto fail1; 1145 1146 /* Mapping is not required since values match MCDI */ 1147 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT == 1148 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT); 1149 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM == 1150 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM); 1151 1152 switch (value) { 1153 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT: 1154 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM: 1155 *subvariantp = value; 1156 break; 1157 default: 1158 rc = EINVAL; 1159 goto fail2; 1160 } 1161 1162 return (0); 1163 1164 fail2: 1165 EFSYS_PROBE(fail2); 1166 1167 fail1: 1168 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1169 1170 return (rc); 1171 } 1172 1173 __checkReturn efx_rc_t 1174 efx_nic_set_fw_subvariant( 1175 __in efx_nic_t *enp, 1176 __in efx_nic_fw_subvariant_t subvariant) 1177 { 1178 efx_rc_t rc; 1179 1180 switch (subvariant) { 1181 case EFX_NIC_FW_SUBVARIANT_DEFAULT: 1182 case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM: 1183 /* Mapping is not required since values match MCDI */ 1184 break; 1185 default: 1186 rc = EINVAL; 1187 goto fail1; 1188 } 1189 1190 rc = efx_mcdi_set_nic_global(enp, 1191 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant); 1192 if (rc != 0) 1193 goto fail2; 1194 1195 return (0); 1196 1197 fail2: 1198 EFSYS_PROBE(fail2); 1199 1200 fail1: 1201 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1202 1203 return (rc); 1204 } 1205 1206 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 1207 1208 __checkReturn efx_rc_t 1209 efx_nic_check_pcie_link_speed( 1210 __in efx_nic_t *enp, 1211 __in uint32_t pcie_link_width, 1212 __in uint32_t pcie_link_gen, 1213 __out efx_pcie_link_performance_t *resultp) 1214 { 1215 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1216 uint32_t bandwidth; 1217 efx_pcie_link_performance_t result; 1218 efx_rc_t rc; 1219 1220 if ((encp->enc_required_pcie_bandwidth_mbps == 0) || 1221 (pcie_link_width == 0) || (pcie_link_width == 32) || 1222 (pcie_link_gen == 0)) { 1223 /* 1224 * No usable info on what is required and/or in use. In virtual 1225 * machines, sometimes the PCIe link width is reported as 0 or 1226 * 32, or the speed as 0. 1227 */ 1228 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH; 1229 goto out; 1230 } 1231 1232 /* Calculate the available bandwidth in megabits per second */ 1233 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width, 1234 pcie_link_gen, &bandwidth); 1235 if (rc != 0) 1236 goto fail1; 1237 1238 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) { 1239 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH; 1240 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) { 1241 /* The link provides enough bandwidth but not optimal latency */ 1242 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY; 1243 } else { 1244 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL; 1245 } 1246 1247 out: 1248 *resultp = result; 1249 1250 return (0); 1251 1252 fail1: 1253 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1254 1255 return (rc); 1256 } 1257