1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2020 Xilinx, Inc. 4 * Copyright(c) 2008-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 10 #if EFSYS_OPT_MCDI 11 12 /* 13 * There are three versions of the MCDI interface: 14 * - MCDIv0: Siena BootROM. Transport uses MCDIv1 headers. 15 * - MCDIv1: Siena firmware and Huntington BootROM. 16 * - MCDIv2: EF10 firmware (Huntington/Medford) and Medford BootROM. 17 * Transport uses MCDIv2 headers. 18 * 19 * MCDIv2 Header NOT_EPOCH flag 20 * ---------------------------- 21 * A new epoch begins at initial startup or after an MC reboot, and defines when 22 * the MC should reject stale MCDI requests. 23 * 24 * The first MCDI request sent by the host should contain NOT_EPOCH=0, and all 25 * subsequent requests (until the next MC reboot) should contain NOT_EPOCH=1. 26 * 27 * After rebooting the MC will fail all requests with NOT_EPOCH=1 by writing a 28 * response with ERROR=1 and DATALEN=0 until a request is seen with NOT_EPOCH=0. 29 */ 30 31 32 33 #if EFSYS_OPT_SIENA 34 35 static const efx_mcdi_ops_t __efx_mcdi_siena_ops = { 36 siena_mcdi_init, /* emco_init */ 37 siena_mcdi_send_request, /* emco_send_request */ 38 siena_mcdi_poll_reboot, /* emco_poll_reboot */ 39 siena_mcdi_poll_response, /* emco_poll_response */ 40 siena_mcdi_read_response, /* emco_read_response */ 41 siena_mcdi_fini, /* emco_fini */ 42 siena_mcdi_feature_supported, /* emco_feature_supported */ 43 siena_mcdi_get_timeout, /* emco_get_timeout */ 44 }; 45 46 #endif /* EFSYS_OPT_SIENA */ 47 48 #if EFX_OPTS_EF10() 49 50 static const efx_mcdi_ops_t __efx_mcdi_ef10_ops = { 51 ef10_mcdi_init, /* emco_init */ 52 ef10_mcdi_send_request, /* emco_send_request */ 53 ef10_mcdi_poll_reboot, /* emco_poll_reboot */ 54 ef10_mcdi_poll_response, /* emco_poll_response */ 55 ef10_mcdi_read_response, /* emco_read_response */ 56 ef10_mcdi_fini, /* emco_fini */ 57 ef10_mcdi_feature_supported, /* emco_feature_supported */ 58 ef10_mcdi_get_timeout, /* emco_get_timeout */ 59 }; 60 61 #endif /* EFX_OPTS_EF10() */ 62 63 #if EFSYS_OPT_RIVERHEAD 64 65 static const efx_mcdi_ops_t __efx_mcdi_rhead_ops = { 66 ef10_mcdi_init, /* emco_init */ 67 ef10_mcdi_send_request, /* emco_send_request */ 68 ef10_mcdi_poll_reboot, /* emco_poll_reboot */ 69 ef10_mcdi_poll_response, /* emco_poll_response */ 70 ef10_mcdi_read_response, /* emco_read_response */ 71 ef10_mcdi_fini, /* emco_fini */ 72 ef10_mcdi_feature_supported, /* emco_feature_supported */ 73 ef10_mcdi_get_timeout, /* emco_get_timeout */ 74 }; 75 76 #endif /* EFSYS_OPT_RIVERHEAD */ 77 78 79 80 __checkReturn efx_rc_t 81 efx_mcdi_init( 82 __in efx_nic_t *enp, 83 __in const efx_mcdi_transport_t *emtp) 84 { 85 const efx_mcdi_ops_t *emcop; 86 efx_rc_t rc; 87 88 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 89 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); 90 91 switch (enp->en_family) { 92 #if EFSYS_OPT_SIENA 93 case EFX_FAMILY_SIENA: 94 emcop = &__efx_mcdi_siena_ops; 95 break; 96 #endif /* EFSYS_OPT_SIENA */ 97 98 #if EFSYS_OPT_HUNTINGTON 99 case EFX_FAMILY_HUNTINGTON: 100 emcop = &__efx_mcdi_ef10_ops; 101 break; 102 #endif /* EFSYS_OPT_HUNTINGTON */ 103 104 #if EFSYS_OPT_MEDFORD 105 case EFX_FAMILY_MEDFORD: 106 emcop = &__efx_mcdi_ef10_ops; 107 break; 108 #endif /* EFSYS_OPT_MEDFORD */ 109 110 #if EFSYS_OPT_MEDFORD2 111 case EFX_FAMILY_MEDFORD2: 112 emcop = &__efx_mcdi_ef10_ops; 113 break; 114 #endif /* EFSYS_OPT_MEDFORD2 */ 115 116 #if EFSYS_OPT_RIVERHEAD 117 case EFX_FAMILY_RIVERHEAD: 118 emcop = &__efx_mcdi_rhead_ops; 119 break; 120 #endif /* EFSYS_OPT_RIVERHEAD */ 121 122 default: 123 EFSYS_ASSERT(0); 124 rc = ENOTSUP; 125 goto fail1; 126 } 127 128 if (enp->en_features & EFX_FEATURE_MCDI_DMA) { 129 /* MCDI requires a DMA buffer in host memory */ 130 if ((emtp == NULL) || (emtp->emt_dma_mem) == NULL) { 131 rc = EINVAL; 132 goto fail2; 133 } 134 } 135 enp->en_mcdi.em_emtp = emtp; 136 137 if (emcop != NULL && emcop->emco_init != NULL) { 138 if ((rc = emcop->emco_init(enp, emtp)) != 0) 139 goto fail3; 140 } 141 142 enp->en_mcdi.em_emcop = emcop; 143 enp->en_mod_flags |= EFX_MOD_MCDI; 144 145 return (0); 146 147 fail3: 148 EFSYS_PROBE(fail3); 149 fail2: 150 EFSYS_PROBE(fail2); 151 fail1: 152 EFSYS_PROBE1(fail1, efx_rc_t, rc); 153 154 enp->en_mcdi.em_emcop = NULL; 155 enp->en_mcdi.em_emtp = NULL; 156 enp->en_mod_flags &= ~EFX_MOD_MCDI; 157 158 return (rc); 159 } 160 161 void 162 efx_mcdi_fini( 163 __in efx_nic_t *enp) 164 { 165 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 166 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 167 168 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 169 EFSYS_ASSERT3U(enp->en_mod_flags, ==, EFX_MOD_MCDI); 170 171 if (emcop != NULL && emcop->emco_fini != NULL) 172 emcop->emco_fini(enp); 173 174 emip->emi_port = 0; 175 emip->emi_aborted = 0; 176 177 enp->en_mcdi.em_emcop = NULL; 178 enp->en_mod_flags &= ~EFX_MOD_MCDI; 179 } 180 181 void 182 efx_mcdi_new_epoch( 183 __in efx_nic_t *enp) 184 { 185 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 186 efsys_lock_state_t state; 187 188 /* Start a new epoch (allow fresh MCDI requests to succeed) */ 189 EFSYS_LOCK(enp->en_eslp, state); 190 emip->emi_new_epoch = B_TRUE; 191 EFSYS_UNLOCK(enp->en_eslp, state); 192 } 193 194 static void 195 efx_mcdi_send_request( 196 __in efx_nic_t *enp, 197 __in void *hdrp, 198 __in size_t hdr_len, 199 __in void *sdup, 200 __in size_t sdu_len) 201 { 202 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 203 204 emcop->emco_send_request(enp, hdrp, hdr_len, sdup, sdu_len); 205 } 206 207 static efx_rc_t 208 efx_mcdi_poll_reboot( 209 __in efx_nic_t *enp) 210 { 211 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 212 efx_rc_t rc; 213 214 rc = emcop->emco_poll_reboot(enp); 215 return (rc); 216 } 217 218 static boolean_t 219 efx_mcdi_poll_response( 220 __in efx_nic_t *enp) 221 { 222 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 223 boolean_t available; 224 225 available = emcop->emco_poll_response(enp); 226 return (available); 227 } 228 229 static void 230 efx_mcdi_read_response( 231 __in efx_nic_t *enp, 232 __out void *bufferp, 233 __in size_t offset, 234 __in size_t length) 235 { 236 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 237 238 emcop->emco_read_response(enp, bufferp, offset, length); 239 } 240 241 void 242 efx_mcdi_request_start( 243 __in efx_nic_t *enp, 244 __in efx_mcdi_req_t *emrp, 245 __in boolean_t ev_cpl) 246 { 247 #if EFSYS_OPT_MCDI_LOGGING 248 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 249 #endif 250 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 251 efx_dword_t hdr[2]; 252 size_t hdr_len; 253 unsigned int max_version; 254 unsigned int seq; 255 unsigned int xflags; 256 boolean_t new_epoch; 257 efsys_lock_state_t state; 258 259 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 260 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 261 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 262 263 /* 264 * efx_mcdi_request_start() is naturally serialised against both 265 * efx_mcdi_request_poll() and efx_mcdi_ev_cpl()/efx_mcdi_ev_death(), 266 * by virtue of there only being one outstanding MCDI request. 267 * Unfortunately, upper layers may also call efx_mcdi_request_abort() 268 * at any time, to timeout a pending mcdi request, That request may 269 * then subsequently complete, meaning efx_mcdi_ev_cpl() or 270 * efx_mcdi_ev_death() may end up running in parallel with 271 * efx_mcdi_request_start(). This race is handled by ensuring that 272 * %emi_pending_req, %emi_ev_cpl and %emi_seq are protected by the 273 * en_eslp lock. 274 */ 275 EFSYS_LOCK(enp->en_eslp, state); 276 EFSYS_ASSERT(emip->emi_pending_req == NULL); 277 emip->emi_pending_req = emrp; 278 emip->emi_ev_cpl = ev_cpl; 279 emip->emi_poll_cnt = 0; 280 seq = emip->emi_seq++ & EFX_MASK32(MCDI_HEADER_SEQ); 281 new_epoch = emip->emi_new_epoch; 282 max_version = emip->emi_max_version; 283 EFSYS_UNLOCK(enp->en_eslp, state); 284 285 xflags = 0; 286 if (ev_cpl) 287 xflags |= MCDI_HEADER_XFLAGS_EVREQ; 288 289 /* 290 * Huntington firmware supports MCDIv2, but the Huntington BootROM only 291 * supports MCDIv1. Use MCDIv1 headers for MCDIv1 commands where 292 * possible to support this. 293 */ 294 if ((max_version >= 2) && 295 ((emrp->emr_cmd > MC_CMD_CMD_SPACE_ESCAPE_7) || 296 (emrp->emr_in_length > MCDI_CTL_SDU_LEN_MAX_V1) || 297 (emrp->emr_out_length > MCDI_CTL_SDU_LEN_MAX_V1))) { 298 /* Construct MCDI v2 header */ 299 hdr_len = sizeof (hdr); 300 EFX_POPULATE_DWORD_8(hdr[0], 301 MCDI_HEADER_CODE, MC_CMD_V2_EXTN, 302 MCDI_HEADER_RESYNC, 1, 303 MCDI_HEADER_DATALEN, 0, 304 MCDI_HEADER_SEQ, seq, 305 MCDI_HEADER_NOT_EPOCH, new_epoch ? 0 : 1, 306 MCDI_HEADER_ERROR, 0, 307 MCDI_HEADER_RESPONSE, 0, 308 MCDI_HEADER_XFLAGS, xflags); 309 310 EFX_POPULATE_DWORD_2(hdr[1], 311 MC_CMD_V2_EXTN_IN_EXTENDED_CMD, emrp->emr_cmd, 312 MC_CMD_V2_EXTN_IN_ACTUAL_LEN, emrp->emr_in_length); 313 } else { 314 /* Construct MCDI v1 header */ 315 hdr_len = sizeof (hdr[0]); 316 EFX_POPULATE_DWORD_8(hdr[0], 317 MCDI_HEADER_CODE, emrp->emr_cmd, 318 MCDI_HEADER_RESYNC, 1, 319 MCDI_HEADER_DATALEN, emrp->emr_in_length, 320 MCDI_HEADER_SEQ, seq, 321 MCDI_HEADER_NOT_EPOCH, new_epoch ? 0 : 1, 322 MCDI_HEADER_ERROR, 0, 323 MCDI_HEADER_RESPONSE, 0, 324 MCDI_HEADER_XFLAGS, xflags); 325 } 326 327 #if EFSYS_OPT_MCDI_LOGGING 328 if (emtp->emt_logger != NULL) { 329 emtp->emt_logger(emtp->emt_context, EFX_LOG_MCDI_REQUEST, 330 &hdr[0], hdr_len, 331 emrp->emr_in_buf, emrp->emr_in_length); 332 } 333 #endif /* EFSYS_OPT_MCDI_LOGGING */ 334 335 efx_mcdi_send_request(enp, &hdr[0], hdr_len, 336 emrp->emr_in_buf, emrp->emr_in_length); 337 } 338 339 340 static void 341 efx_mcdi_read_response_header( 342 __in efx_nic_t *enp, 343 __inout efx_mcdi_req_t *emrp) 344 { 345 #if EFSYS_OPT_MCDI_LOGGING 346 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 347 #endif /* EFSYS_OPT_MCDI_LOGGING */ 348 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 349 efx_dword_t hdr[2]; 350 unsigned int hdr_len; 351 unsigned int data_len; 352 unsigned int seq; 353 unsigned int cmd; 354 unsigned int error; 355 efx_rc_t rc; 356 357 EFSYS_ASSERT(emrp != NULL); 358 359 efx_mcdi_read_response(enp, &hdr[0], 0, sizeof (hdr[0])); 360 hdr_len = sizeof (hdr[0]); 361 362 cmd = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_CODE); 363 seq = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_SEQ); 364 error = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_ERROR); 365 366 if (cmd != MC_CMD_V2_EXTN) { 367 data_len = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_DATALEN); 368 } else { 369 efx_mcdi_read_response(enp, &hdr[1], hdr_len, sizeof (hdr[1])); 370 hdr_len += sizeof (hdr[1]); 371 372 cmd = EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_EXTENDED_CMD); 373 data_len = 374 EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_ACTUAL_LEN); 375 } 376 377 if (error && (data_len == 0)) { 378 /* The MC has rebooted since the request was sent. */ 379 EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); 380 efx_mcdi_poll_reboot(enp); 381 rc = EIO; 382 goto fail1; 383 } 384 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 385 if (((cmd != emrp->emr_cmd) && (emrp->emr_cmd != MC_CMD_PROXY_CMD)) || 386 #else 387 if ((cmd != emrp->emr_cmd) || 388 #endif 389 (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { 390 /* Response is for a different request */ 391 rc = EIO; 392 goto fail2; 393 } 394 if (error) { 395 efx_dword_t err[2]; 396 unsigned int err_len = MIN(data_len, sizeof (err)); 397 int err_code = MC_CMD_ERR_EPROTO; 398 int err_arg = 0; 399 400 /* Read error code (and arg num for MCDI v2 commands) */ 401 efx_mcdi_read_response(enp, &err, hdr_len, err_len); 402 403 if (err_len >= (MC_CMD_ERR_CODE_OFST + sizeof (efx_dword_t))) 404 err_code = EFX_DWORD_FIELD(err[0], EFX_DWORD_0); 405 #ifdef WITH_MCDI_V2 406 if (err_len >= (MC_CMD_ERR_ARG_OFST + sizeof (efx_dword_t))) 407 err_arg = EFX_DWORD_FIELD(err[1], EFX_DWORD_0); 408 #endif 409 emrp->emr_err_code = err_code; 410 emrp->emr_err_arg = err_arg; 411 412 #if EFSYS_OPT_MCDI_PROXY_AUTH 413 if ((err_code == MC_CMD_ERR_PROXY_PENDING) && 414 (err_len == sizeof (err))) { 415 /* 416 * The MCDI request would normally fail with EPERM, but 417 * firmware has forwarded it to an authorization agent 418 * attached to a privileged PF. 419 * 420 * Save the authorization request handle. The client 421 * must wait for a PROXY_RESPONSE event, or timeout. 422 */ 423 emrp->emr_proxy_handle = err_arg; 424 } 425 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 426 427 #if EFSYS_OPT_MCDI_LOGGING 428 if (emtp->emt_logger != NULL) { 429 emtp->emt_logger(emtp->emt_context, 430 EFX_LOG_MCDI_RESPONSE, 431 &hdr[0], hdr_len, 432 &err[0], err_len); 433 } 434 #endif /* EFSYS_OPT_MCDI_LOGGING */ 435 436 if (!emrp->emr_quiet) { 437 EFSYS_PROBE3(mcdi_err_arg, int, emrp->emr_cmd, 438 int, err_code, int, err_arg); 439 } 440 441 rc = efx_mcdi_request_errcode(err_code); 442 goto fail3; 443 } 444 445 emrp->emr_rc = 0; 446 emrp->emr_out_length_used = data_len; 447 #if EFSYS_OPT_MCDI_PROXY_AUTH 448 emrp->emr_proxy_handle = 0; 449 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 450 return; 451 452 fail3: 453 fail2: 454 fail1: 455 emrp->emr_rc = rc; 456 emrp->emr_out_length_used = 0; 457 } 458 459 static void 460 efx_mcdi_finish_response( 461 __in efx_nic_t *enp, 462 __in efx_mcdi_req_t *emrp) 463 { 464 #if EFSYS_OPT_MCDI_LOGGING 465 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 466 #endif /* EFSYS_OPT_MCDI_LOGGING */ 467 efx_dword_t hdr[2]; 468 unsigned int hdr_len; 469 size_t bytes; 470 unsigned int resp_off; 471 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 472 unsigned int resp_cmd; 473 boolean_t proxied_cmd_resp = B_FALSE; 474 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 475 476 if (emrp->emr_out_buf == NULL) 477 return; 478 479 /* Read the command header to detect MCDI response format */ 480 hdr_len = sizeof (hdr[0]); 481 efx_mcdi_read_response(enp, &hdr[0], 0, hdr_len); 482 if (EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_CODE) == MC_CMD_V2_EXTN) { 483 /* 484 * Read the actual payload length. The length given in the event 485 * is only correct for responses with the V1 format. 486 */ 487 efx_mcdi_read_response(enp, &hdr[1], hdr_len, sizeof (hdr[1])); 488 hdr_len += sizeof (hdr[1]); 489 resp_off = hdr_len; 490 491 emrp->emr_out_length_used = EFX_DWORD_FIELD(hdr[1], 492 MC_CMD_V2_EXTN_IN_ACTUAL_LEN); 493 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 494 /* 495 * A proxy MCDI command is executed by PF on behalf of 496 * one of its VFs. The command to be proxied follows 497 * immediately afterward in the host buffer. 498 * PROXY_CMD inner call complete response should be copied to 499 * output buffer so that it can be returned to the requesting 500 * function in MC_CMD_PROXY_COMPLETE payload. 501 */ 502 resp_cmd = 503 EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_EXTENDED_CMD); 504 proxied_cmd_resp = ((emrp->emr_cmd == MC_CMD_PROXY_CMD) && 505 (resp_cmd != MC_CMD_PROXY_CMD)); 506 if (proxied_cmd_resp) { 507 resp_off = 0; 508 emrp->emr_out_length_used += hdr_len; 509 } 510 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 511 } else { 512 resp_off = hdr_len; 513 } 514 515 /* Copy payload out into caller supplied buffer */ 516 bytes = MIN(emrp->emr_out_length_used, emrp->emr_out_length); 517 efx_mcdi_read_response(enp, emrp->emr_out_buf, resp_off, bytes); 518 519 #if EFSYS_OPT_MCDI_LOGGING 520 if (emtp->emt_logger != NULL) { 521 emtp->emt_logger(emtp->emt_context, 522 EFX_LOG_MCDI_RESPONSE, 523 &hdr[0], hdr_len, 524 emrp->emr_out_buf, bytes); 525 } 526 #endif /* EFSYS_OPT_MCDI_LOGGING */ 527 } 528 529 530 __checkReturn boolean_t 531 efx_mcdi_request_poll( 532 __in efx_nic_t *enp) 533 { 534 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 535 efx_mcdi_req_t *emrp; 536 efsys_lock_state_t state; 537 efx_rc_t rc; 538 539 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 540 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 541 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 542 543 /* Serialise against post-watchdog efx_mcdi_ev* */ 544 EFSYS_LOCK(enp->en_eslp, state); 545 546 EFSYS_ASSERT(emip->emi_pending_req != NULL); 547 EFSYS_ASSERT(!emip->emi_ev_cpl); 548 emrp = emip->emi_pending_req; 549 550 /* Check if hardware is unavailable */ 551 if (efx_nic_hw_unavailable(enp)) { 552 EFSYS_UNLOCK(enp->en_eslp, state); 553 return (B_FALSE); 554 } 555 556 /* Check for reboot atomically w.r.t efx_mcdi_request_start */ 557 if (emip->emi_poll_cnt++ == 0) { 558 if ((rc = efx_mcdi_poll_reboot(enp)) != 0) { 559 emip->emi_pending_req = NULL; 560 EFSYS_UNLOCK(enp->en_eslp, state); 561 562 /* Reboot/Assertion */ 563 if (rc == EIO || rc == EINTR) 564 efx_mcdi_raise_exception(enp, emrp, rc); 565 566 goto fail1; 567 } 568 } 569 570 /* Check if a response is available */ 571 if (efx_mcdi_poll_response(enp) == B_FALSE) { 572 EFSYS_UNLOCK(enp->en_eslp, state); 573 return (B_FALSE); 574 } 575 576 /* Read the response header */ 577 efx_mcdi_read_response_header(enp, emrp); 578 579 /* Request complete */ 580 emip->emi_pending_req = NULL; 581 582 /* Ensure stale MCDI requests fail after an MC reboot. */ 583 emip->emi_new_epoch = B_FALSE; 584 585 EFSYS_UNLOCK(enp->en_eslp, state); 586 587 if ((rc = emrp->emr_rc) != 0) 588 goto fail2; 589 590 efx_mcdi_finish_response(enp, emrp); 591 return (B_TRUE); 592 593 fail2: 594 if (!emrp->emr_quiet) 595 EFSYS_PROBE(fail2); 596 fail1: 597 if (!emrp->emr_quiet) 598 EFSYS_PROBE1(fail1, efx_rc_t, rc); 599 600 return (B_TRUE); 601 } 602 603 __checkReturn boolean_t 604 efx_mcdi_request_abort( 605 __in efx_nic_t *enp) 606 { 607 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 608 efx_mcdi_req_t *emrp; 609 boolean_t aborted; 610 efsys_lock_state_t state; 611 612 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 613 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 614 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 615 616 /* 617 * efx_mcdi_ev_* may have already completed this event, and be 618 * spinning/blocked on the upper layer lock. So it *is* legitimate 619 * to for emi_pending_req to be NULL. If there is a pending event 620 * completed request, then provide a "credit" to allow 621 * efx_mcdi_ev_cpl() to accept a single spurious completion. 622 */ 623 EFSYS_LOCK(enp->en_eslp, state); 624 emrp = emip->emi_pending_req; 625 aborted = (emrp != NULL); 626 if (aborted) { 627 emip->emi_pending_req = NULL; 628 629 /* Error the request */ 630 emrp->emr_out_length_used = 0; 631 emrp->emr_rc = ETIMEDOUT; 632 633 /* Provide a credit for seqno/emr_pending_req mismatches */ 634 if (emip->emi_ev_cpl) 635 ++emip->emi_aborted; 636 637 /* 638 * The upper layer has called us, so we don't 639 * need to complete the request. 640 */ 641 } 642 EFSYS_UNLOCK(enp->en_eslp, state); 643 644 return (aborted); 645 } 646 647 void 648 efx_mcdi_get_timeout( 649 __in efx_nic_t *enp, 650 __in efx_mcdi_req_t *emrp, 651 __out uint32_t *timeoutp) 652 { 653 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 654 655 emcop->emco_get_timeout(enp, emrp, timeoutp); 656 } 657 658 __checkReturn efx_rc_t 659 efx_mcdi_request_errcode( 660 __in unsigned int err) 661 { 662 663 switch (err) { 664 /* MCDI v1 */ 665 case MC_CMD_ERR_EPERM: 666 return (EACCES); 667 case MC_CMD_ERR_ENOENT: 668 return (ENOENT); 669 case MC_CMD_ERR_EINTR: 670 return (EINTR); 671 case MC_CMD_ERR_EACCES: 672 return (EACCES); 673 case MC_CMD_ERR_EBUSY: 674 return (EBUSY); 675 case MC_CMD_ERR_EINVAL: 676 return (EINVAL); 677 case MC_CMD_ERR_EDEADLK: 678 return (EDEADLK); 679 case MC_CMD_ERR_ENOSYS: 680 return (ENOTSUP); 681 case MC_CMD_ERR_ETIME: 682 return (ETIMEDOUT); 683 case MC_CMD_ERR_ENOTSUP: 684 return (ENOTSUP); 685 case MC_CMD_ERR_EALREADY: 686 return (EALREADY); 687 688 /* MCDI v2 */ 689 case MC_CMD_ERR_EEXIST: 690 return (EEXIST); 691 #ifdef MC_CMD_ERR_EAGAIN 692 case MC_CMD_ERR_EAGAIN: 693 return (EAGAIN); 694 #endif 695 #ifdef MC_CMD_ERR_ENOSPC 696 case MC_CMD_ERR_ENOSPC: 697 return (ENOSPC); 698 #endif 699 case MC_CMD_ERR_ERANGE: 700 return (ERANGE); 701 702 case MC_CMD_ERR_ALLOC_FAIL: 703 return (ENOMEM); 704 case MC_CMD_ERR_NO_VADAPTOR: 705 return (ENOENT); 706 case MC_CMD_ERR_NO_EVB_PORT: 707 return (ENOENT); 708 case MC_CMD_ERR_NO_VSWITCH: 709 return (ENODEV); 710 case MC_CMD_ERR_VLAN_LIMIT: 711 return (EINVAL); 712 case MC_CMD_ERR_BAD_PCI_FUNC: 713 return (ENODEV); 714 case MC_CMD_ERR_BAD_VLAN_MODE: 715 return (EINVAL); 716 case MC_CMD_ERR_BAD_VSWITCH_TYPE: 717 return (EINVAL); 718 case MC_CMD_ERR_BAD_VPORT_TYPE: 719 return (EINVAL); 720 case MC_CMD_ERR_MAC_EXIST: 721 return (EEXIST); 722 723 case MC_CMD_ERR_PROXY_PENDING: 724 return (EAGAIN); 725 726 default: 727 EFSYS_PROBE1(mc_pcol_error, int, err); 728 return (EIO); 729 } 730 } 731 732 void 733 efx_mcdi_raise_exception( 734 __in efx_nic_t *enp, 735 __in_opt efx_mcdi_req_t *emrp, 736 __in int rc) 737 { 738 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 739 efx_mcdi_exception_t exception; 740 741 /* Reboot or Assertion failure only */ 742 EFSYS_ASSERT(rc == EIO || rc == EINTR); 743 744 /* 745 * If MC_CMD_REBOOT causes a reboot (dependent on parameters), 746 * then the EIO is not worthy of an exception. 747 */ 748 if (emrp != NULL && emrp->emr_cmd == MC_CMD_REBOOT && rc == EIO) 749 return; 750 751 exception = (rc == EIO) 752 ? EFX_MCDI_EXCEPTION_MC_REBOOT 753 : EFX_MCDI_EXCEPTION_MC_BADASSERT; 754 755 emtp->emt_exception(emtp->emt_context, exception); 756 } 757 758 void 759 efx_mcdi_execute( 760 __in efx_nic_t *enp, 761 __inout efx_mcdi_req_t *emrp) 762 { 763 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 764 765 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 766 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 767 768 emrp->emr_quiet = B_FALSE; 769 emtp->emt_execute(emtp->emt_context, emrp); 770 } 771 772 void 773 efx_mcdi_execute_quiet( 774 __in efx_nic_t *enp, 775 __inout efx_mcdi_req_t *emrp) 776 { 777 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 778 779 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 780 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 781 782 emrp->emr_quiet = B_TRUE; 783 emtp->emt_execute(emtp->emt_context, emrp); 784 } 785 786 void 787 efx_mcdi_ev_cpl( 788 __in efx_nic_t *enp, 789 __in unsigned int seq, 790 __in unsigned int outlen, 791 __in int errcode) 792 { 793 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 794 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 795 efx_mcdi_req_t *emrp; 796 efsys_lock_state_t state; 797 798 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 799 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 800 801 /* 802 * Serialise against efx_mcdi_request_poll()/efx_mcdi_request_start() 803 * when we're completing an aborted request. 804 */ 805 EFSYS_LOCK(enp->en_eslp, state); 806 if (emip->emi_pending_req == NULL || !emip->emi_ev_cpl || 807 (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { 808 EFSYS_ASSERT(emip->emi_aborted > 0); 809 if (emip->emi_aborted > 0) 810 --emip->emi_aborted; 811 EFSYS_UNLOCK(enp->en_eslp, state); 812 return; 813 } 814 815 emrp = emip->emi_pending_req; 816 emip->emi_pending_req = NULL; 817 EFSYS_UNLOCK(enp->en_eslp, state); 818 819 if (emip->emi_max_version >= 2) { 820 /* MCDIv2 response details do not fit into an event. */ 821 efx_mcdi_read_response_header(enp, emrp); 822 } else { 823 if (errcode != 0) { 824 if (!emrp->emr_quiet) { 825 EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, 826 int, errcode); 827 } 828 emrp->emr_out_length_used = 0; 829 emrp->emr_rc = efx_mcdi_request_errcode(errcode); 830 } else { 831 emrp->emr_out_length_used = outlen; 832 emrp->emr_rc = 0; 833 } 834 } 835 if (emrp->emr_rc == 0) 836 efx_mcdi_finish_response(enp, emrp); 837 838 emtp->emt_ev_cpl(emtp->emt_context); 839 } 840 841 #if EFSYS_OPT_MCDI_PROXY_AUTH 842 843 __checkReturn efx_rc_t 844 efx_mcdi_get_proxy_handle( 845 __in efx_nic_t *enp, 846 __in efx_mcdi_req_t *emrp, 847 __out uint32_t *handlep) 848 { 849 efx_rc_t rc; 850 851 _NOTE(ARGUNUSED(enp)) 852 853 /* 854 * Return proxy handle from MCDI request that returned with error 855 * MC_MCD_ERR_PROXY_PENDING. This handle is used to wait for a matching 856 * PROXY_RESPONSE event. 857 */ 858 if ((emrp == NULL) || (handlep == NULL)) { 859 rc = EINVAL; 860 goto fail1; 861 } 862 if ((emrp->emr_rc != 0) && 863 (emrp->emr_err_code == MC_CMD_ERR_PROXY_PENDING)) { 864 *handlep = emrp->emr_proxy_handle; 865 rc = 0; 866 } else { 867 *handlep = 0; 868 rc = ENOENT; 869 } 870 return (rc); 871 872 fail1: 873 EFSYS_PROBE1(fail1, efx_rc_t, rc); 874 return (rc); 875 } 876 877 void 878 efx_mcdi_ev_proxy_response( 879 __in efx_nic_t *enp, 880 __in unsigned int handle, 881 __in unsigned int status) 882 { 883 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 884 efx_rc_t rc; 885 886 /* 887 * Handle results of an authorization request for a privileged MCDI 888 * command. If authorization was granted then we must re-issue the 889 * original MCDI request. If authorization failed or timed out, 890 * then the original MCDI request should be completed with the 891 * result code from this event. 892 */ 893 rc = (status == 0) ? 0 : efx_mcdi_request_errcode(status); 894 895 emtp->emt_ev_proxy_response(emtp->emt_context, handle, rc); 896 } 897 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 898 899 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 900 void 901 efx_mcdi_ev_proxy_request( 902 __in efx_nic_t *enp, 903 __in unsigned int index) 904 { 905 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 906 907 if (emtp->emt_ev_proxy_request != NULL) 908 emtp->emt_ev_proxy_request(emtp->emt_context, index); 909 } 910 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 911 void 912 efx_mcdi_ev_death( 913 __in efx_nic_t *enp, 914 __in int rc) 915 { 916 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 917 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; 918 efx_mcdi_req_t *emrp = NULL; 919 boolean_t ev_cpl; 920 efsys_lock_state_t state; 921 922 /* 923 * The MCDI request (if there is one) has been terminated, either 924 * by a BADASSERT or REBOOT event. 925 * 926 * If there is an outstanding event-completed MCDI operation, then we 927 * will never receive the completion event (because both MCDI 928 * completions and BADASSERT events are sent to the same evq). So 929 * complete this MCDI op. 930 * 931 * This function might run in parallel with efx_mcdi_request_poll() 932 * for poll completed mcdi requests, and also with 933 * efx_mcdi_request_start() for post-watchdog completions. 934 */ 935 EFSYS_LOCK(enp->en_eslp, state); 936 emrp = emip->emi_pending_req; 937 ev_cpl = emip->emi_ev_cpl; 938 if (emrp != NULL && emip->emi_ev_cpl) { 939 emip->emi_pending_req = NULL; 940 941 emrp->emr_out_length_used = 0; 942 emrp->emr_rc = rc; 943 ++emip->emi_aborted; 944 } 945 946 /* 947 * Since we're running in parallel with a request, consume the 948 * status word before dropping the lock. 949 */ 950 if (rc == EIO || rc == EINTR) { 951 EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); 952 (void) efx_mcdi_poll_reboot(enp); 953 emip->emi_new_epoch = B_TRUE; 954 } 955 956 EFSYS_UNLOCK(enp->en_eslp, state); 957 958 efx_mcdi_raise_exception(enp, emrp, rc); 959 960 if (emrp != NULL && ev_cpl) 961 emtp->emt_ev_cpl(emtp->emt_context); 962 } 963 964 __checkReturn efx_rc_t 965 efx_mcdi_version( 966 __in efx_nic_t *enp, 967 __out_ecount_opt(4) uint16_t versionp[4], 968 __out_opt uint32_t *buildp, 969 __out_opt efx_mcdi_boot_t *statusp) 970 { 971 efx_mcdi_req_t req; 972 EFX_MCDI_DECLARE_BUF(payload, 973 MAX(MC_CMD_GET_VERSION_IN_LEN, MC_CMD_GET_BOOT_STATUS_IN_LEN), 974 MAX(MC_CMD_GET_VERSION_OUT_LEN, 975 MC_CMD_GET_BOOT_STATUS_OUT_LEN)); 976 efx_word_t *ver_words; 977 uint16_t version[4]; 978 uint32_t build; 979 efx_mcdi_boot_t status; 980 efx_rc_t rc; 981 982 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); 983 984 req.emr_cmd = MC_CMD_GET_VERSION; 985 req.emr_in_buf = payload; 986 req.emr_in_length = MC_CMD_GET_VERSION_IN_LEN; 987 req.emr_out_buf = payload; 988 req.emr_out_length = MC_CMD_GET_VERSION_OUT_LEN; 989 990 efx_mcdi_execute(enp, &req); 991 992 if (req.emr_rc != 0) { 993 rc = req.emr_rc; 994 goto fail1; 995 } 996 997 /* bootrom support */ 998 if (req.emr_out_length_used == MC_CMD_GET_VERSION_V0_OUT_LEN) { 999 version[0] = version[1] = version[2] = version[3] = 0; 1000 build = MCDI_OUT_DWORD(req, GET_VERSION_OUT_FIRMWARE); 1001 1002 goto version; 1003 } 1004 1005 if (req.emr_out_length_used < MC_CMD_GET_VERSION_OUT_LEN) { 1006 rc = EMSGSIZE; 1007 goto fail2; 1008 } 1009 1010 ver_words = MCDI_OUT2(req, efx_word_t, GET_VERSION_OUT_VERSION); 1011 version[0] = EFX_WORD_FIELD(ver_words[0], EFX_WORD_0); 1012 version[1] = EFX_WORD_FIELD(ver_words[1], EFX_WORD_0); 1013 version[2] = EFX_WORD_FIELD(ver_words[2], EFX_WORD_0); 1014 version[3] = EFX_WORD_FIELD(ver_words[3], EFX_WORD_0); 1015 build = MCDI_OUT_DWORD(req, GET_VERSION_OUT_FIRMWARE); 1016 1017 version: 1018 /* The bootrom doesn't understand BOOT_STATUS */ 1019 if (MC_FW_VERSION_IS_BOOTLOADER(build)) { 1020 status = EFX_MCDI_BOOT_ROM; 1021 goto out; 1022 } 1023 1024 (void) memset(payload, 0, sizeof (payload)); 1025 req.emr_cmd = MC_CMD_GET_BOOT_STATUS; 1026 req.emr_in_buf = payload; 1027 req.emr_in_length = MC_CMD_GET_BOOT_STATUS_IN_LEN; 1028 req.emr_out_buf = payload; 1029 req.emr_out_length = MC_CMD_GET_BOOT_STATUS_OUT_LEN; 1030 1031 efx_mcdi_execute_quiet(enp, &req); 1032 1033 if (req.emr_rc == EACCES) { 1034 /* Unprivileged functions cannot access BOOT_STATUS */ 1035 status = EFX_MCDI_BOOT_PRIMARY; 1036 version[0] = version[1] = version[2] = version[3] = 0; 1037 build = 0; 1038 goto out; 1039 } 1040 1041 if (req.emr_rc != 0) { 1042 rc = req.emr_rc; 1043 goto fail3; 1044 } 1045 1046 if (req.emr_out_length_used < MC_CMD_GET_BOOT_STATUS_OUT_LEN) { 1047 rc = EMSGSIZE; 1048 goto fail4; 1049 } 1050 1051 if (MCDI_OUT_DWORD_FIELD(req, GET_BOOT_STATUS_OUT_FLAGS, 1052 GET_BOOT_STATUS_OUT_FLAGS_PRIMARY)) 1053 status = EFX_MCDI_BOOT_PRIMARY; 1054 else 1055 status = EFX_MCDI_BOOT_SECONDARY; 1056 1057 out: 1058 if (versionp != NULL) 1059 memcpy(versionp, version, sizeof (version)); 1060 if (buildp != NULL) 1061 *buildp = build; 1062 if (statusp != NULL) 1063 *statusp = status; 1064 1065 return (0); 1066 1067 fail4: 1068 EFSYS_PROBE(fail4); 1069 fail3: 1070 EFSYS_PROBE(fail3); 1071 fail2: 1072 EFSYS_PROBE(fail2); 1073 fail1: 1074 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1075 1076 return (rc); 1077 } 1078 1079 __checkReturn efx_rc_t 1080 efx_mcdi_get_capabilities( 1081 __in efx_nic_t *enp, 1082 __out_opt uint32_t *flagsp, 1083 __out_opt uint16_t *rx_dpcpu_fw_idp, 1084 __out_opt uint16_t *tx_dpcpu_fw_idp, 1085 __out_opt uint32_t *flags2p, 1086 __out_opt uint32_t *tso2ncp) 1087 { 1088 efx_mcdi_req_t req; 1089 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN, 1090 MC_CMD_GET_CAPABILITIES_V2_OUT_LEN); 1091 boolean_t v2_capable; 1092 efx_rc_t rc; 1093 1094 req.emr_cmd = MC_CMD_GET_CAPABILITIES; 1095 req.emr_in_buf = payload; 1096 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; 1097 req.emr_out_buf = payload; 1098 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN; 1099 1100 efx_mcdi_execute_quiet(enp, &req); 1101 1102 if (req.emr_rc != 0) { 1103 rc = req.emr_rc; 1104 goto fail1; 1105 } 1106 1107 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 1108 rc = EMSGSIZE; 1109 goto fail2; 1110 } 1111 1112 if (flagsp != NULL) 1113 *flagsp = MCDI_OUT_DWORD(req, GET_CAPABILITIES_OUT_FLAGS1); 1114 1115 if (rx_dpcpu_fw_idp != NULL) 1116 *rx_dpcpu_fw_idp = MCDI_OUT_WORD(req, 1117 GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 1118 1119 if (tx_dpcpu_fw_idp != NULL) 1120 *tx_dpcpu_fw_idp = MCDI_OUT_WORD(req, 1121 GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 1122 1123 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) 1124 v2_capable = B_FALSE; 1125 else 1126 v2_capable = B_TRUE; 1127 1128 if (flags2p != NULL) { 1129 *flags2p = (v2_capable) ? 1130 MCDI_OUT_DWORD(req, GET_CAPABILITIES_V2_OUT_FLAGS2) : 1131 0; 1132 } 1133 1134 if (tso2ncp != NULL) { 1135 *tso2ncp = (v2_capable) ? 1136 MCDI_OUT_WORD(req, 1137 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS) : 1138 0; 1139 } 1140 1141 return (0); 1142 1143 fail2: 1144 EFSYS_PROBE(fail2); 1145 fail1: 1146 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1147 1148 return (rc); 1149 } 1150 1151 static __checkReturn efx_rc_t 1152 efx_mcdi_do_reboot( 1153 __in efx_nic_t *enp, 1154 __in boolean_t after_assertion) 1155 { 1156 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_REBOOT_IN_LEN, 1157 MC_CMD_REBOOT_OUT_LEN); 1158 efx_mcdi_req_t req; 1159 efx_rc_t rc; 1160 1161 /* 1162 * We could require the caller to have caused en_mod_flags=0 to 1163 * call this function. This doesn't help the other port though, 1164 * who's about to get the MC ripped out from underneath them. 1165 * Since they have to cope with the subsequent fallout of MCDI 1166 * failures, we should as well. 1167 */ 1168 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1169 1170 req.emr_cmd = MC_CMD_REBOOT; 1171 req.emr_in_buf = payload; 1172 req.emr_in_length = MC_CMD_REBOOT_IN_LEN; 1173 req.emr_out_buf = payload; 1174 req.emr_out_length = MC_CMD_REBOOT_OUT_LEN; 1175 1176 MCDI_IN_SET_DWORD(req, REBOOT_IN_FLAGS, 1177 (after_assertion ? MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION : 0)); 1178 1179 efx_mcdi_execute_quiet(enp, &req); 1180 1181 if (req.emr_rc == EACCES) { 1182 /* Unprivileged functions cannot reboot the MC. */ 1183 goto out; 1184 } 1185 1186 /* A successful reboot request returns EIO. */ 1187 if (req.emr_rc != 0 && req.emr_rc != EIO) { 1188 rc = req.emr_rc; 1189 goto fail1; 1190 } 1191 1192 out: 1193 return (0); 1194 1195 fail1: 1196 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1197 1198 return (rc); 1199 } 1200 1201 __checkReturn efx_rc_t 1202 efx_mcdi_reboot( 1203 __in efx_nic_t *enp) 1204 { 1205 return (efx_mcdi_do_reboot(enp, B_FALSE)); 1206 } 1207 1208 __checkReturn efx_rc_t 1209 efx_mcdi_exit_assertion_handler( 1210 __in efx_nic_t *enp) 1211 { 1212 return (efx_mcdi_do_reboot(enp, B_TRUE)); 1213 } 1214 1215 __checkReturn efx_rc_t 1216 efx_mcdi_read_assertion( 1217 __in efx_nic_t *enp) 1218 { 1219 efx_mcdi_req_t req; 1220 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_ASSERTS_IN_LEN, 1221 MC_CMD_GET_ASSERTS_OUT_LEN); 1222 const char *reason; 1223 unsigned int flags; 1224 unsigned int index; 1225 unsigned int ofst; 1226 int retry; 1227 efx_rc_t rc; 1228 1229 /* 1230 * Before we attempt to chat to the MC, we should verify that the MC 1231 * isn't in it's assertion handler, either due to a previous reboot, 1232 * or because we're reinitializing due to an eec_exception(). 1233 * 1234 * Use GET_ASSERTS to read any assertion state that may be present. 1235 * Retry this command twice. Once because a boot-time assertion failure 1236 * might cause the 1st MCDI request to fail. And once again because 1237 * we might race with efx_mcdi_exit_assertion_handler() running on 1238 * partner port(s) on the same NIC. 1239 */ 1240 retry = 2; 1241 do { 1242 (void) memset(payload, 0, sizeof (payload)); 1243 req.emr_cmd = MC_CMD_GET_ASSERTS; 1244 req.emr_in_buf = payload; 1245 req.emr_in_length = MC_CMD_GET_ASSERTS_IN_LEN; 1246 req.emr_out_buf = payload; 1247 req.emr_out_length = MC_CMD_GET_ASSERTS_OUT_LEN; 1248 1249 MCDI_IN_SET_DWORD(req, GET_ASSERTS_IN_CLEAR, 1); 1250 efx_mcdi_execute_quiet(enp, &req); 1251 1252 } while ((req.emr_rc == EINTR || req.emr_rc == EIO) && retry-- > 0); 1253 1254 if (req.emr_rc != 0) { 1255 if (req.emr_rc == EACCES) { 1256 /* Unprivileged functions cannot clear assertions. */ 1257 goto out; 1258 } 1259 rc = req.emr_rc; 1260 goto fail1; 1261 } 1262 1263 if (req.emr_out_length_used < MC_CMD_GET_ASSERTS_OUT_LEN) { 1264 rc = EMSGSIZE; 1265 goto fail2; 1266 } 1267 1268 /* Print out any assertion state recorded */ 1269 flags = MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_GLOBAL_FLAGS); 1270 if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS) 1271 return (0); 1272 1273 reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL) 1274 ? "system-level assertion" 1275 : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL) 1276 ? "thread-level assertion" 1277 : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED) 1278 ? "watchdog reset" 1279 : (flags == MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP) 1280 ? "illegal address trap" 1281 : "unknown assertion"; 1282 EFSYS_PROBE3(mcpu_assertion, 1283 const char *, reason, unsigned int, 1284 MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_SAVED_PC_OFFS), 1285 unsigned int, 1286 MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_THREAD_OFFS)); 1287 1288 /* Print out the registers (r1 ... r31) */ 1289 ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST; 1290 for (index = 1; 1291 index < 1 + MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM; 1292 index++) { 1293 EFSYS_PROBE2(mcpu_register, unsigned int, index, unsigned int, 1294 EFX_DWORD_FIELD(*MCDI_OUT(req, efx_dword_t, ofst), 1295 EFX_DWORD_0)); 1296 ofst += sizeof (efx_dword_t); 1297 } 1298 EFSYS_ASSERT(ofst <= MC_CMD_GET_ASSERTS_OUT_LEN); 1299 1300 out: 1301 return (0); 1302 1303 fail2: 1304 EFSYS_PROBE(fail2); 1305 fail1: 1306 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1307 1308 return (rc); 1309 } 1310 1311 1312 /* 1313 * Internal routines for for specific MCDI requests. 1314 */ 1315 1316 __checkReturn efx_rc_t 1317 efx_mcdi_drv_attach( 1318 __in efx_nic_t *enp, 1319 __in boolean_t attach) 1320 { 1321 efx_mcdi_req_t req; 1322 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRV_ATTACH_IN_V2_LEN, 1323 MC_CMD_DRV_ATTACH_EXT_OUT_LEN); 1324 efx_rc_t rc; 1325 1326 req.emr_cmd = MC_CMD_DRV_ATTACH; 1327 req.emr_in_buf = payload; 1328 if (enp->en_drv_version[0] == '\0') { 1329 req.emr_in_length = MC_CMD_DRV_ATTACH_IN_LEN; 1330 } else { 1331 req.emr_in_length = MC_CMD_DRV_ATTACH_IN_V2_LEN; 1332 } 1333 req.emr_out_buf = payload; 1334 req.emr_out_length = MC_CMD_DRV_ATTACH_EXT_OUT_LEN; 1335 1336 /* 1337 * Typically, client drivers use DONT_CARE for the datapath firmware 1338 * type to ensure that the driver can attach to an unprivileged 1339 * function. The datapath firmware type to use is controlled by the 1340 * 'sfboot' utility. 1341 * If a client driver wishes to attach with a specific datapath firmware 1342 * type, that can be passed in second argument of efx_nic_probe API. One 1343 * such example is the ESXi native driver that attempts attaching with 1344 * FULL_FEATURED datapath firmware type first and fall backs to 1345 * DONT_CARE datapath firmware type if MC_CMD_DRV_ATTACH fails. 1346 */ 1347 MCDI_IN_POPULATE_DWORD_2(req, DRV_ATTACH_IN_NEW_STATE, 1348 DRV_ATTACH_IN_ATTACH, attach ? 1 : 0, 1349 DRV_ATTACH_IN_SUBVARIANT_AWARE, EFSYS_OPT_FW_SUBVARIANT_AWARE); 1350 MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_UPDATE, 1); 1351 MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_FIRMWARE_ID, enp->efv); 1352 1353 if (req.emr_in_length >= MC_CMD_DRV_ATTACH_IN_V2_LEN) { 1354 EFX_STATIC_ASSERT(sizeof (enp->en_drv_version) == 1355 MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN); 1356 memcpy(MCDI_IN2(req, char, DRV_ATTACH_IN_V2_DRIVER_VERSION), 1357 enp->en_drv_version, 1358 MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN); 1359 } 1360 1361 efx_mcdi_execute(enp, &req); 1362 1363 if (req.emr_rc != 0) { 1364 rc = req.emr_rc; 1365 goto fail1; 1366 } 1367 1368 if (req.emr_out_length_used < MC_CMD_DRV_ATTACH_OUT_LEN) { 1369 rc = EMSGSIZE; 1370 goto fail2; 1371 } 1372 1373 return (0); 1374 1375 fail2: 1376 EFSYS_PROBE(fail2); 1377 fail1: 1378 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1379 1380 return (rc); 1381 } 1382 1383 __checkReturn efx_rc_t 1384 efx_mcdi_get_board_cfg( 1385 __in efx_nic_t *enp, 1386 __out_opt uint32_t *board_typep, 1387 __out_opt efx_dword_t *capabilitiesp, 1388 __out_ecount_opt(6) uint8_t mac_addrp[6]) 1389 { 1390 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 1391 efx_mcdi_req_t req; 1392 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_BOARD_CFG_IN_LEN, 1393 MC_CMD_GET_BOARD_CFG_OUT_LENMIN); 1394 efx_rc_t rc; 1395 1396 req.emr_cmd = MC_CMD_GET_BOARD_CFG; 1397 req.emr_in_buf = payload; 1398 req.emr_in_length = MC_CMD_GET_BOARD_CFG_IN_LEN; 1399 req.emr_out_buf = payload; 1400 req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMIN; 1401 1402 efx_mcdi_execute(enp, &req); 1403 1404 if (req.emr_rc != 0) { 1405 rc = req.emr_rc; 1406 goto fail1; 1407 } 1408 1409 if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) { 1410 rc = EMSGSIZE; 1411 goto fail2; 1412 } 1413 1414 if (mac_addrp != NULL) { 1415 uint8_t *addrp; 1416 1417 if (emip->emi_port == 1) { 1418 addrp = MCDI_OUT2(req, uint8_t, 1419 GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0); 1420 } else if (emip->emi_port == 2) { 1421 addrp = MCDI_OUT2(req, uint8_t, 1422 GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1); 1423 } else { 1424 rc = EINVAL; 1425 goto fail3; 1426 } 1427 1428 EFX_MAC_ADDR_COPY(mac_addrp, addrp); 1429 } 1430 1431 if (capabilitiesp != NULL) { 1432 if (emip->emi_port == 1) { 1433 *capabilitiesp = *MCDI_OUT2(req, efx_dword_t, 1434 GET_BOARD_CFG_OUT_CAPABILITIES_PORT0); 1435 } else if (emip->emi_port == 2) { 1436 *capabilitiesp = *MCDI_OUT2(req, efx_dword_t, 1437 GET_BOARD_CFG_OUT_CAPABILITIES_PORT1); 1438 } else { 1439 rc = EINVAL; 1440 goto fail4; 1441 } 1442 } 1443 1444 if (board_typep != NULL) { 1445 *board_typep = MCDI_OUT_DWORD(req, 1446 GET_BOARD_CFG_OUT_BOARD_TYPE); 1447 } 1448 1449 return (0); 1450 1451 fail4: 1452 EFSYS_PROBE(fail4); 1453 fail3: 1454 EFSYS_PROBE(fail3); 1455 fail2: 1456 EFSYS_PROBE(fail2); 1457 fail1: 1458 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1459 1460 return (rc); 1461 } 1462 1463 __checkReturn efx_rc_t 1464 efx_mcdi_get_resource_limits( 1465 __in efx_nic_t *enp, 1466 __out_opt uint32_t *nevqp, 1467 __out_opt uint32_t *nrxqp, 1468 __out_opt uint32_t *ntxqp) 1469 { 1470 efx_mcdi_req_t req; 1471 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RESOURCE_LIMITS_IN_LEN, 1472 MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN); 1473 efx_rc_t rc; 1474 1475 req.emr_cmd = MC_CMD_GET_RESOURCE_LIMITS; 1476 req.emr_in_buf = payload; 1477 req.emr_in_length = MC_CMD_GET_RESOURCE_LIMITS_IN_LEN; 1478 req.emr_out_buf = payload; 1479 req.emr_out_length = MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN; 1480 1481 efx_mcdi_execute(enp, &req); 1482 1483 if (req.emr_rc != 0) { 1484 rc = req.emr_rc; 1485 goto fail1; 1486 } 1487 1488 if (req.emr_out_length_used < MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN) { 1489 rc = EMSGSIZE; 1490 goto fail2; 1491 } 1492 1493 if (nevqp != NULL) 1494 *nevqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_EVQ); 1495 if (nrxqp != NULL) 1496 *nrxqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_RXQ); 1497 if (ntxqp != NULL) 1498 *ntxqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_TXQ); 1499 1500 return (0); 1501 1502 fail2: 1503 EFSYS_PROBE(fail2); 1504 fail1: 1505 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1506 1507 return (rc); 1508 } 1509 1510 __checkReturn efx_rc_t 1511 efx_mcdi_get_phy_cfg( 1512 __in efx_nic_t *enp) 1513 { 1514 efx_port_t *epp = &(enp->en_port); 1515 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1516 efx_mcdi_req_t req; 1517 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_CFG_IN_LEN, 1518 MC_CMD_GET_PHY_CFG_OUT_LEN); 1519 #if EFSYS_OPT_NAMES 1520 const char *namep; 1521 size_t namelen; 1522 #endif 1523 uint32_t phy_media_type; 1524 efx_rc_t rc; 1525 1526 req.emr_cmd = MC_CMD_GET_PHY_CFG; 1527 req.emr_in_buf = payload; 1528 req.emr_in_length = MC_CMD_GET_PHY_CFG_IN_LEN; 1529 req.emr_out_buf = payload; 1530 req.emr_out_length = MC_CMD_GET_PHY_CFG_OUT_LEN; 1531 1532 efx_mcdi_execute(enp, &req); 1533 1534 if (req.emr_rc != 0) { 1535 rc = req.emr_rc; 1536 goto fail1; 1537 } 1538 1539 if (req.emr_out_length_used < MC_CMD_GET_PHY_CFG_OUT_LEN) { 1540 rc = EMSGSIZE; 1541 goto fail2; 1542 } 1543 1544 encp->enc_phy_type = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_TYPE); 1545 #if EFSYS_OPT_NAMES 1546 namep = MCDI_OUT2(req, char, GET_PHY_CFG_OUT_NAME); 1547 namelen = MIN(sizeof (encp->enc_phy_name) - 1, 1548 strnlen(namep, MC_CMD_GET_PHY_CFG_OUT_NAME_LEN)); 1549 (void) memset(encp->enc_phy_name, 0, 1550 sizeof (encp->enc_phy_name)); 1551 memcpy(encp->enc_phy_name, namep, namelen); 1552 #endif /* EFSYS_OPT_NAMES */ 1553 (void) memset(encp->enc_phy_revision, 0, 1554 sizeof (encp->enc_phy_revision)); 1555 memcpy(encp->enc_phy_revision, 1556 MCDI_OUT2(req, char, GET_PHY_CFG_OUT_REVISION), 1557 MIN(sizeof (encp->enc_phy_revision) - 1, 1558 MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN)); 1559 #if EFSYS_OPT_PHY_LED_CONTROL 1560 encp->enc_led_mask = ((1 << EFX_PHY_LED_DEFAULT) | 1561 (1 << EFX_PHY_LED_OFF) | 1562 (1 << EFX_PHY_LED_ON)); 1563 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1564 1565 /* Get the media type of the fixed port, if recognised. */ 1566 EFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI); 1567 EFX_STATIC_ASSERT(MC_CMD_MEDIA_CX4 == EFX_PHY_MEDIA_CX4); 1568 EFX_STATIC_ASSERT(MC_CMD_MEDIA_KX4 == EFX_PHY_MEDIA_KX4); 1569 EFX_STATIC_ASSERT(MC_CMD_MEDIA_XFP == EFX_PHY_MEDIA_XFP); 1570 EFX_STATIC_ASSERT(MC_CMD_MEDIA_SFP_PLUS == EFX_PHY_MEDIA_SFP_PLUS); 1571 EFX_STATIC_ASSERT(MC_CMD_MEDIA_BASE_T == EFX_PHY_MEDIA_BASE_T); 1572 EFX_STATIC_ASSERT(MC_CMD_MEDIA_QSFP_PLUS == EFX_PHY_MEDIA_QSFP_PLUS); 1573 phy_media_type = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_MEDIA_TYPE); 1574 epp->ep_fixed_port_type = (efx_phy_media_type_t)phy_media_type; 1575 if (epp->ep_fixed_port_type >= EFX_PHY_MEDIA_NTYPES) 1576 epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID; 1577 1578 epp->ep_phy_cap_mask = 1579 MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_SUPPORTED_CAP); 1580 #if EFSYS_OPT_PHY_FLAGS 1581 encp->enc_phy_flags_mask = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_FLAGS); 1582 #endif /* EFSYS_OPT_PHY_FLAGS */ 1583 1584 encp->enc_port = (uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_PRT); 1585 1586 /* Populate internal state */ 1587 encp->enc_mcdi_mdio_channel = 1588 (uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_CHANNEL); 1589 1590 #if EFSYS_OPT_PHY_STATS 1591 encp->enc_mcdi_phy_stat_mask = 1592 MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_STATS_MASK); 1593 #endif /* EFSYS_OPT_PHY_STATS */ 1594 1595 #if EFSYS_OPT_BIST 1596 encp->enc_bist_mask = 0; 1597 if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, 1598 GET_PHY_CFG_OUT_BIST_CABLE_SHORT)) 1599 encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_CABLE_SHORT); 1600 if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, 1601 GET_PHY_CFG_OUT_BIST_CABLE_LONG)) 1602 encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_CABLE_LONG); 1603 if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS, 1604 GET_PHY_CFG_OUT_BIST)) 1605 encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_NORMAL); 1606 #endif /* EFSYS_OPT_BIST */ 1607 1608 return (0); 1609 1610 fail2: 1611 EFSYS_PROBE(fail2); 1612 fail1: 1613 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1614 1615 return (rc); 1616 } 1617 1618 __checkReturn efx_rc_t 1619 efx_mcdi_firmware_update_supported( 1620 __in efx_nic_t *enp, 1621 __out boolean_t *supportedp) 1622 { 1623 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 1624 efx_rc_t rc; 1625 1626 if (emcop != NULL) { 1627 if ((rc = emcop->emco_feature_supported(enp, 1628 EFX_MCDI_FEATURE_FW_UPDATE, supportedp)) != 0) 1629 goto fail1; 1630 } else { 1631 /* Earlier devices always supported updates */ 1632 *supportedp = B_TRUE; 1633 } 1634 1635 return (0); 1636 1637 fail1: 1638 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1639 1640 return (rc); 1641 } 1642 1643 __checkReturn efx_rc_t 1644 efx_mcdi_macaddr_change_supported( 1645 __in efx_nic_t *enp, 1646 __out boolean_t *supportedp) 1647 { 1648 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 1649 efx_rc_t rc; 1650 1651 if (emcop != NULL) { 1652 if ((rc = emcop->emco_feature_supported(enp, 1653 EFX_MCDI_FEATURE_MACADDR_CHANGE, supportedp)) != 0) 1654 goto fail1; 1655 } else { 1656 /* Earlier devices always supported MAC changes */ 1657 *supportedp = B_TRUE; 1658 } 1659 1660 return (0); 1661 1662 fail1: 1663 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1664 1665 return (rc); 1666 } 1667 1668 __checkReturn efx_rc_t 1669 efx_mcdi_link_control_supported( 1670 __in efx_nic_t *enp, 1671 __out boolean_t *supportedp) 1672 { 1673 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 1674 efx_rc_t rc; 1675 1676 if (emcop != NULL) { 1677 if ((rc = emcop->emco_feature_supported(enp, 1678 EFX_MCDI_FEATURE_LINK_CONTROL, supportedp)) != 0) 1679 goto fail1; 1680 } else { 1681 /* Earlier devices always supported link control */ 1682 *supportedp = B_TRUE; 1683 } 1684 1685 return (0); 1686 1687 fail1: 1688 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1689 1690 return (rc); 1691 } 1692 1693 __checkReturn efx_rc_t 1694 efx_mcdi_mac_spoofing_supported( 1695 __in efx_nic_t *enp, 1696 __out boolean_t *supportedp) 1697 { 1698 const efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; 1699 efx_rc_t rc; 1700 1701 if (emcop != NULL) { 1702 if ((rc = emcop->emco_feature_supported(enp, 1703 EFX_MCDI_FEATURE_MAC_SPOOFING, supportedp)) != 0) 1704 goto fail1; 1705 } else { 1706 /* Earlier devices always supported MAC spoofing */ 1707 *supportedp = B_TRUE; 1708 } 1709 1710 return (0); 1711 1712 fail1: 1713 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1714 1715 return (rc); 1716 } 1717 1718 #if EFSYS_OPT_BIST 1719 1720 #if EFX_OPTS_EF10() 1721 /* 1722 * Enter bist offline mode. This is a fw mode which puts the NIC into a state 1723 * where memory BIST tests can be run and not much else can interfere or happen. 1724 * A reboot is required to exit this mode. 1725 */ 1726 __checkReturn efx_rc_t 1727 efx_mcdi_bist_enable_offline( 1728 __in efx_nic_t *enp) 1729 { 1730 efx_mcdi_req_t req; 1731 efx_rc_t rc; 1732 1733 EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN == 0); 1734 EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN == 0); 1735 1736 req.emr_cmd = MC_CMD_ENABLE_OFFLINE_BIST; 1737 req.emr_in_buf = NULL; 1738 req.emr_in_length = 0; 1739 req.emr_out_buf = NULL; 1740 req.emr_out_length = 0; 1741 1742 efx_mcdi_execute(enp, &req); 1743 1744 if (req.emr_rc != 0) { 1745 rc = req.emr_rc; 1746 goto fail1; 1747 } 1748 1749 return (0); 1750 1751 fail1: 1752 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1753 1754 return (rc); 1755 } 1756 #endif /* EFX_OPTS_EF10() */ 1757 1758 __checkReturn efx_rc_t 1759 efx_mcdi_bist_start( 1760 __in efx_nic_t *enp, 1761 __in efx_bist_type_t type) 1762 { 1763 efx_mcdi_req_t req; 1764 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_START_BIST_IN_LEN, 1765 MC_CMD_START_BIST_OUT_LEN); 1766 efx_rc_t rc; 1767 1768 req.emr_cmd = MC_CMD_START_BIST; 1769 req.emr_in_buf = payload; 1770 req.emr_in_length = MC_CMD_START_BIST_IN_LEN; 1771 req.emr_out_buf = payload; 1772 req.emr_out_length = MC_CMD_START_BIST_OUT_LEN; 1773 1774 switch (type) { 1775 case EFX_BIST_TYPE_PHY_NORMAL: 1776 MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, MC_CMD_PHY_BIST); 1777 break; 1778 case EFX_BIST_TYPE_PHY_CABLE_SHORT: 1779 MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, 1780 MC_CMD_PHY_BIST_CABLE_SHORT); 1781 break; 1782 case EFX_BIST_TYPE_PHY_CABLE_LONG: 1783 MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, 1784 MC_CMD_PHY_BIST_CABLE_LONG); 1785 break; 1786 case EFX_BIST_TYPE_MC_MEM: 1787 MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, 1788 MC_CMD_MC_MEM_BIST); 1789 break; 1790 case EFX_BIST_TYPE_SAT_MEM: 1791 MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, 1792 MC_CMD_PORT_MEM_BIST); 1793 break; 1794 case EFX_BIST_TYPE_REG: 1795 MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, 1796 MC_CMD_REG_BIST); 1797 break; 1798 default: 1799 EFSYS_ASSERT(0); 1800 } 1801 1802 efx_mcdi_execute(enp, &req); 1803 1804 if (req.emr_rc != 0) { 1805 rc = req.emr_rc; 1806 goto fail1; 1807 } 1808 1809 return (0); 1810 1811 fail1: 1812 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1813 1814 return (rc); 1815 } 1816 1817 #endif /* EFSYS_OPT_BIST */ 1818 1819 1820 /* Enable logging of some events (e.g. link state changes) */ 1821 __checkReturn efx_rc_t 1822 efx_mcdi_log_ctrl( 1823 __in efx_nic_t *enp) 1824 { 1825 efx_mcdi_req_t req; 1826 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LOG_CTRL_IN_LEN, 1827 MC_CMD_LOG_CTRL_OUT_LEN); 1828 efx_rc_t rc; 1829 1830 req.emr_cmd = MC_CMD_LOG_CTRL; 1831 req.emr_in_buf = payload; 1832 req.emr_in_length = MC_CMD_LOG_CTRL_IN_LEN; 1833 req.emr_out_buf = payload; 1834 req.emr_out_length = MC_CMD_LOG_CTRL_OUT_LEN; 1835 1836 MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST, 1837 MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ); 1838 MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST_EVQ, 0); 1839 1840 efx_mcdi_execute(enp, &req); 1841 1842 if (req.emr_rc != 0) { 1843 rc = req.emr_rc; 1844 goto fail1; 1845 } 1846 1847 return (0); 1848 1849 fail1: 1850 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1851 1852 return (rc); 1853 } 1854 1855 1856 #if EFSYS_OPT_MAC_STATS 1857 1858 __checkReturn efx_rc_t 1859 efx_mcdi_mac_stats( 1860 __in efx_nic_t *enp, 1861 __in uint32_t vport_id, 1862 __in_opt efsys_mem_t *esmp, 1863 __in efx_stats_action_t action, 1864 __in uint16_t period_ms) 1865 { 1866 efx_mcdi_req_t req; 1867 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_MAC_STATS_IN_LEN, 1868 MC_CMD_MAC_STATS_V2_OUT_DMA_LEN); 1869 int clear = (action == EFX_STATS_CLEAR); 1870 int upload = (action == EFX_STATS_UPLOAD); 1871 int enable = (action == EFX_STATS_ENABLE_NOEVENTS); 1872 int events = (action == EFX_STATS_ENABLE_EVENTS); 1873 int disable = (action == EFX_STATS_DISABLE); 1874 efx_rc_t rc; 1875 1876 req.emr_cmd = MC_CMD_MAC_STATS; 1877 req.emr_in_buf = payload; 1878 req.emr_in_length = MC_CMD_MAC_STATS_IN_LEN; 1879 req.emr_out_buf = payload; 1880 req.emr_out_length = MC_CMD_MAC_STATS_V2_OUT_DMA_LEN; 1881 1882 MCDI_IN_POPULATE_DWORD_6(req, MAC_STATS_IN_CMD, 1883 MAC_STATS_IN_DMA, upload, 1884 MAC_STATS_IN_CLEAR, clear, 1885 MAC_STATS_IN_PERIODIC_CHANGE, enable | events | disable, 1886 MAC_STATS_IN_PERIODIC_ENABLE, enable | events, 1887 MAC_STATS_IN_PERIODIC_NOEVENT, !events, 1888 MAC_STATS_IN_PERIOD_MS, (enable | events) ? period_ms : 0); 1889 1890 if (enable || events || upload) { 1891 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; 1892 uint32_t bytes; 1893 1894 /* Periodic stats or stats upload require a DMA buffer */ 1895 if (esmp == NULL) { 1896 rc = EINVAL; 1897 goto fail1; 1898 } 1899 1900 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) { 1901 /* MAC stats count too small for legacy MAC stats */ 1902 rc = ENOSPC; 1903 goto fail2; 1904 } 1905 1906 bytes = encp->enc_mac_stats_nstats * sizeof (efx_qword_t); 1907 1908 if (EFSYS_MEM_SIZE(esmp) < bytes) { 1909 /* DMA buffer too small */ 1910 rc = ENOSPC; 1911 goto fail3; 1912 } 1913 1914 MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_LO, 1915 EFSYS_MEM_ADDR(esmp) & 0xffffffff); 1916 MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_HI, 1917 EFSYS_MEM_ADDR(esmp) >> 32); 1918 MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_LEN, bytes); 1919 } 1920 1921 /* 1922 * NOTE: Do not use EVB_PORT_ID_ASSIGNED when disabling periodic stats, 1923 * as this may fail (and leave periodic DMA enabled) if the 1924 * vadapter has already been deleted. 1925 */ 1926 MCDI_IN_SET_DWORD(req, MAC_STATS_IN_PORT_ID, 1927 (disable ? EVB_PORT_ID_NULL : vport_id)); 1928 1929 efx_mcdi_execute(enp, &req); 1930 1931 if (req.emr_rc != 0) { 1932 /* EF10: Expect ENOENT if no DMA queues are initialised */ 1933 if ((req.emr_rc != ENOENT) || 1934 (enp->en_rx_qcount + enp->en_tx_qcount != 0)) { 1935 rc = req.emr_rc; 1936 goto fail4; 1937 } 1938 } 1939 1940 return (0); 1941 1942 fail4: 1943 EFSYS_PROBE(fail4); 1944 fail3: 1945 EFSYS_PROBE(fail3); 1946 fail2: 1947 EFSYS_PROBE(fail2); 1948 fail1: 1949 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1950 1951 return (rc); 1952 } 1953 1954 __checkReturn efx_rc_t 1955 efx_mcdi_mac_stats_clear( 1956 __in efx_nic_t *enp) 1957 { 1958 efx_rc_t rc; 1959 1960 if ((rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL, 1961 EFX_STATS_CLEAR, 0)) != 0) 1962 goto fail1; 1963 1964 return (0); 1965 1966 fail1: 1967 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1968 1969 return (rc); 1970 } 1971 1972 __checkReturn efx_rc_t 1973 efx_mcdi_mac_stats_upload( 1974 __in efx_nic_t *enp, 1975 __in efsys_mem_t *esmp) 1976 { 1977 efx_rc_t rc; 1978 1979 /* 1980 * The MC DMAs aggregate statistics for our convenience, so we can 1981 * avoid having to pull the statistics buffer into the cache to 1982 * maintain cumulative statistics. 1983 */ 1984 if ((rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, esmp, 1985 EFX_STATS_UPLOAD, 0)) != 0) 1986 goto fail1; 1987 1988 return (0); 1989 1990 fail1: 1991 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1992 1993 return (rc); 1994 } 1995 1996 __checkReturn efx_rc_t 1997 efx_mcdi_mac_stats_periodic( 1998 __in efx_nic_t *enp, 1999 __in efsys_mem_t *esmp, 2000 __in uint16_t period_ms, 2001 __in boolean_t events) 2002 { 2003 efx_rc_t rc; 2004 2005 /* 2006 * The MC DMAs aggregate statistics for our convenience, so we can 2007 * avoid having to pull the statistics buffer into the cache to 2008 * maintain cumulative statistics. 2009 * Huntington uses a fixed 1sec period. 2010 * Medford uses a fixed 1sec period before v6.2.1.1033 firmware. 2011 */ 2012 if (period_ms == 0) 2013 rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL, 2014 EFX_STATS_DISABLE, 0); 2015 else if (events) 2016 rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, esmp, 2017 EFX_STATS_ENABLE_EVENTS, period_ms); 2018 else 2019 rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, esmp, 2020 EFX_STATS_ENABLE_NOEVENTS, period_ms); 2021 2022 if (rc != 0) 2023 goto fail1; 2024 2025 return (0); 2026 2027 fail1: 2028 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2029 2030 return (rc); 2031 } 2032 2033 #endif /* EFSYS_OPT_MAC_STATS */ 2034 2035 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 2036 2037 /* 2038 * This function returns the pf and vf number of a function. If it is a pf the 2039 * vf number is 0xffff. The vf number is the index of the vf on that 2040 * function. So if you have 3 vfs on pf 0 the 3 vfs will return (pf=0,vf=0), 2041 * (pf=0,vf=1), (pf=0,vf=2) aand the pf will return (pf=0, vf=0xffff). 2042 */ 2043 __checkReturn efx_rc_t 2044 efx_mcdi_get_function_info( 2045 __in efx_nic_t *enp, 2046 __out uint32_t *pfp, 2047 __out_opt uint32_t *vfp) 2048 { 2049 efx_mcdi_req_t req; 2050 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_FUNCTION_INFO_IN_LEN, 2051 MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 2052 efx_rc_t rc; 2053 2054 req.emr_cmd = MC_CMD_GET_FUNCTION_INFO; 2055 req.emr_in_buf = payload; 2056 req.emr_in_length = MC_CMD_GET_FUNCTION_INFO_IN_LEN; 2057 req.emr_out_buf = payload; 2058 req.emr_out_length = MC_CMD_GET_FUNCTION_INFO_OUT_LEN; 2059 2060 efx_mcdi_execute(enp, &req); 2061 2062 if (req.emr_rc != 0) { 2063 rc = req.emr_rc; 2064 goto fail1; 2065 } 2066 2067 if (req.emr_out_length_used < MC_CMD_GET_FUNCTION_INFO_OUT_LEN) { 2068 rc = EMSGSIZE; 2069 goto fail2; 2070 } 2071 2072 *pfp = MCDI_OUT_DWORD(req, GET_FUNCTION_INFO_OUT_PF); 2073 if (vfp != NULL) 2074 *vfp = MCDI_OUT_DWORD(req, GET_FUNCTION_INFO_OUT_VF); 2075 2076 return (0); 2077 2078 fail2: 2079 EFSYS_PROBE(fail2); 2080 fail1: 2081 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2082 2083 return (rc); 2084 } 2085 2086 __checkReturn efx_rc_t 2087 efx_mcdi_privilege_mask( 2088 __in efx_nic_t *enp, 2089 __in uint32_t pf, 2090 __in uint32_t vf, 2091 __out uint32_t *maskp) 2092 { 2093 efx_mcdi_req_t req; 2094 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PRIVILEGE_MASK_IN_LEN, 2095 MC_CMD_PRIVILEGE_MASK_OUT_LEN); 2096 efx_rc_t rc; 2097 2098 req.emr_cmd = MC_CMD_PRIVILEGE_MASK; 2099 req.emr_in_buf = payload; 2100 req.emr_in_length = MC_CMD_PRIVILEGE_MASK_IN_LEN; 2101 req.emr_out_buf = payload; 2102 req.emr_out_length = MC_CMD_PRIVILEGE_MASK_OUT_LEN; 2103 2104 MCDI_IN_POPULATE_DWORD_2(req, PRIVILEGE_MASK_IN_FUNCTION, 2105 PRIVILEGE_MASK_IN_FUNCTION_PF, pf, 2106 PRIVILEGE_MASK_IN_FUNCTION_VF, vf); 2107 2108 efx_mcdi_execute(enp, &req); 2109 2110 if (req.emr_rc != 0) { 2111 rc = req.emr_rc; 2112 goto fail1; 2113 } 2114 2115 if (req.emr_out_length_used < MC_CMD_PRIVILEGE_MASK_OUT_LEN) { 2116 rc = EMSGSIZE; 2117 goto fail2; 2118 } 2119 2120 *maskp = MCDI_OUT_DWORD(req, PRIVILEGE_MASK_OUT_OLD_MASK); 2121 2122 return (0); 2123 2124 fail2: 2125 EFSYS_PROBE(fail2); 2126 fail1: 2127 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2128 2129 return (rc); 2130 } 2131 2132 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 2133 2134 __checkReturn efx_rc_t 2135 efx_mcdi_set_workaround( 2136 __in efx_nic_t *enp, 2137 __in uint32_t type, 2138 __in boolean_t enabled, 2139 __out_opt uint32_t *flagsp) 2140 { 2141 efx_mcdi_req_t req; 2142 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_WORKAROUND_IN_LEN, 2143 MC_CMD_WORKAROUND_EXT_OUT_LEN); 2144 efx_rc_t rc; 2145 2146 req.emr_cmd = MC_CMD_WORKAROUND; 2147 req.emr_in_buf = payload; 2148 req.emr_in_length = MC_CMD_WORKAROUND_IN_LEN; 2149 req.emr_out_buf = payload; 2150 req.emr_out_length = MC_CMD_WORKAROUND_OUT_LEN; 2151 2152 MCDI_IN_SET_DWORD(req, WORKAROUND_IN_TYPE, type); 2153 MCDI_IN_SET_DWORD(req, WORKAROUND_IN_ENABLED, enabled ? 1 : 0); 2154 2155 efx_mcdi_execute_quiet(enp, &req); 2156 2157 if (req.emr_rc != 0) { 2158 rc = req.emr_rc; 2159 goto fail1; 2160 } 2161 2162 if (flagsp != NULL) { 2163 if (req.emr_out_length_used >= MC_CMD_WORKAROUND_EXT_OUT_LEN) 2164 *flagsp = MCDI_OUT_DWORD(req, WORKAROUND_EXT_OUT_FLAGS); 2165 else 2166 *flagsp = 0; 2167 } 2168 2169 return (0); 2170 2171 fail1: 2172 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2173 2174 return (rc); 2175 } 2176 2177 2178 __checkReturn efx_rc_t 2179 efx_mcdi_get_workarounds( 2180 __in efx_nic_t *enp, 2181 __out_opt uint32_t *implementedp, 2182 __out_opt uint32_t *enabledp) 2183 { 2184 efx_mcdi_req_t req; 2185 EFX_MCDI_DECLARE_BUF(payload, 0, MC_CMD_GET_WORKAROUNDS_OUT_LEN); 2186 efx_rc_t rc; 2187 2188 req.emr_cmd = MC_CMD_GET_WORKAROUNDS; 2189 req.emr_in_buf = NULL; 2190 req.emr_in_length = 0; 2191 req.emr_out_buf = payload; 2192 req.emr_out_length = MC_CMD_GET_WORKAROUNDS_OUT_LEN; 2193 2194 efx_mcdi_execute(enp, &req); 2195 2196 if (req.emr_rc != 0) { 2197 rc = req.emr_rc; 2198 goto fail1; 2199 } 2200 2201 if (implementedp != NULL) { 2202 *implementedp = 2203 MCDI_OUT_DWORD(req, GET_WORKAROUNDS_OUT_IMPLEMENTED); 2204 } 2205 2206 if (enabledp != NULL) { 2207 *enabledp = MCDI_OUT_DWORD(req, GET_WORKAROUNDS_OUT_ENABLED); 2208 } 2209 2210 return (0); 2211 2212 fail1: 2213 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2214 2215 return (rc); 2216 } 2217 2218 /* 2219 * Size of media information page in accordance with SFF-8472 and SFF-8436. 2220 * It is used in MCDI interface as well. 2221 */ 2222 #define EFX_PHY_MEDIA_INFO_PAGE_SIZE 0x80 2223 2224 /* 2225 * Transceiver identifiers from SFF-8024 Table 4-1. 2226 */ 2227 #define EFX_SFF_TRANSCEIVER_ID_SFP 0x03 /* SFP/SFP+/SFP28 */ 2228 #define EFX_SFF_TRANSCEIVER_ID_QSFP 0x0c /* QSFP */ 2229 #define EFX_SFF_TRANSCEIVER_ID_QSFP_PLUS 0x0d /* QSFP+ or later */ 2230 #define EFX_SFF_TRANSCEIVER_ID_QSFP28 0x11 /* QSFP28 or later */ 2231 2232 static __checkReturn efx_rc_t 2233 efx_mcdi_get_phy_media_info( 2234 __in efx_nic_t *enp, 2235 __in uint32_t mcdi_page, 2236 __in uint8_t offset, 2237 __in uint8_t len, 2238 __out_bcount(len) uint8_t *data) 2239 { 2240 efx_mcdi_req_t req; 2241 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN, 2242 MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN( 2243 EFX_PHY_MEDIA_INFO_PAGE_SIZE)); 2244 efx_rc_t rc; 2245 2246 EFSYS_ASSERT((uint32_t)offset + len <= EFX_PHY_MEDIA_INFO_PAGE_SIZE); 2247 2248 req.emr_cmd = MC_CMD_GET_PHY_MEDIA_INFO; 2249 req.emr_in_buf = payload; 2250 req.emr_in_length = MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN; 2251 req.emr_out_buf = payload; 2252 req.emr_out_length = 2253 MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(EFX_PHY_MEDIA_INFO_PAGE_SIZE); 2254 2255 MCDI_IN_SET_DWORD(req, GET_PHY_MEDIA_INFO_IN_PAGE, mcdi_page); 2256 2257 efx_mcdi_execute(enp, &req); 2258 2259 if (req.emr_rc != 0) { 2260 rc = req.emr_rc; 2261 goto fail1; 2262 } 2263 2264 if (req.emr_out_length_used != 2265 MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(EFX_PHY_MEDIA_INFO_PAGE_SIZE)) { 2266 rc = EMSGSIZE; 2267 goto fail2; 2268 } 2269 2270 if (MCDI_OUT_DWORD(req, GET_PHY_MEDIA_INFO_OUT_DATALEN) != 2271 EFX_PHY_MEDIA_INFO_PAGE_SIZE) { 2272 rc = EIO; 2273 goto fail3; 2274 } 2275 2276 memcpy(data, 2277 MCDI_OUT2(req, uint8_t, GET_PHY_MEDIA_INFO_OUT_DATA) + offset, 2278 len); 2279 2280 return (0); 2281 2282 fail3: 2283 EFSYS_PROBE(fail3); 2284 fail2: 2285 EFSYS_PROBE(fail2); 2286 fail1: 2287 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2288 2289 return (rc); 2290 } 2291 2292 __checkReturn efx_rc_t 2293 efx_mcdi_phy_module_get_info( 2294 __in efx_nic_t *enp, 2295 __in uint8_t dev_addr, 2296 __in size_t offset, 2297 __in size_t len, 2298 __out_bcount(len) uint8_t *data) 2299 { 2300 efx_port_t *epp = &(enp->en_port); 2301 efx_rc_t rc; 2302 uint32_t mcdi_lower_page; 2303 uint32_t mcdi_upper_page; 2304 uint8_t id; 2305 2306 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 2307 2308 /* 2309 * Map device address to MC_CMD_GET_PHY_MEDIA_INFO pages. 2310 * Offset plus length interface allows to access page 0 only. 2311 * I.e. non-zero upper pages are not accessible. 2312 * See SFF-8472 section 4 Memory Organization and SFF-8436 section 7.6 2313 * QSFP+ Memory Map for details on how information is structured 2314 * and accessible. 2315 */ 2316 switch (epp->ep_fixed_port_type) { 2317 case EFX_PHY_MEDIA_SFP_PLUS: 2318 case EFX_PHY_MEDIA_QSFP_PLUS: 2319 /* Port type supports modules */ 2320 break; 2321 default: 2322 rc = ENOTSUP; 2323 goto fail1; 2324 } 2325 2326 /* 2327 * For all supported port types, MCDI page 0 offset 0 holds the 2328 * transceiver identifier. Probe to determine the data layout. 2329 * Definitions from SFF-8024 Table 4-1. 2330 */ 2331 rc = efx_mcdi_get_phy_media_info(enp, 2332 0, 0, sizeof(id), &id); 2333 if (rc != 0) 2334 goto fail2; 2335 2336 switch (id) { 2337 case EFX_SFF_TRANSCEIVER_ID_SFP: 2338 /* 2339 * In accordance with SFF-8472 Diagnostic Monitoring 2340 * Interface for Optical Transceivers section 4 Memory 2341 * Organization two 2-wire addresses are defined. 2342 */ 2343 switch (dev_addr) { 2344 /* Base information */ 2345 case EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE: 2346 /* 2347 * MCDI page 0 should be used to access lower 2348 * page 0 (0x00 - 0x7f) at the device address 0xA0. 2349 */ 2350 mcdi_lower_page = 0; 2351 /* 2352 * MCDI page 1 should be used to access upper 2353 * page 0 (0x80 - 0xff) at the device address 0xA0. 2354 */ 2355 mcdi_upper_page = 1; 2356 break; 2357 /* Diagnostics */ 2358 case EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM: 2359 /* 2360 * MCDI page 2 should be used to access lower 2361 * page 0 (0x00 - 0x7f) at the device address 0xA2. 2362 */ 2363 mcdi_lower_page = 2; 2364 /* 2365 * MCDI page 3 should be used to access upper 2366 * page 0 (0x80 - 0xff) at the device address 0xA2. 2367 */ 2368 mcdi_upper_page = 3; 2369 break; 2370 default: 2371 rc = ENOTSUP; 2372 goto fail3; 2373 } 2374 break; 2375 case EFX_SFF_TRANSCEIVER_ID_QSFP: 2376 case EFX_SFF_TRANSCEIVER_ID_QSFP_PLUS: 2377 case EFX_SFF_TRANSCEIVER_ID_QSFP28: 2378 switch (dev_addr) { 2379 case EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP: 2380 /* 2381 * MCDI page -1 should be used to access lower page 0 2382 * (0x00 - 0x7f). 2383 */ 2384 mcdi_lower_page = (uint32_t)-1; 2385 /* 2386 * MCDI page 0 should be used to access upper page 0 2387 * (0x80h - 0xff). 2388 */ 2389 mcdi_upper_page = 0; 2390 break; 2391 default: 2392 rc = ENOTSUP; 2393 goto fail3; 2394 } 2395 break; 2396 default: 2397 rc = ENOTSUP; 2398 goto fail3; 2399 } 2400 2401 EFX_STATIC_ASSERT(EFX_PHY_MEDIA_INFO_PAGE_SIZE <= 0xFF); 2402 2403 if (offset < EFX_PHY_MEDIA_INFO_PAGE_SIZE) { 2404 size_t read_len = 2405 MIN(len, EFX_PHY_MEDIA_INFO_PAGE_SIZE - offset); 2406 2407 rc = efx_mcdi_get_phy_media_info(enp, 2408 mcdi_lower_page, (uint8_t)offset, (uint8_t)read_len, data); 2409 if (rc != 0) 2410 goto fail4; 2411 2412 data += read_len; 2413 len -= read_len; 2414 2415 offset = 0; 2416 } else { 2417 offset -= EFX_PHY_MEDIA_INFO_PAGE_SIZE; 2418 } 2419 2420 if (len > 0) { 2421 EFSYS_ASSERT3U(len, <=, EFX_PHY_MEDIA_INFO_PAGE_SIZE); 2422 EFSYS_ASSERT3U(offset, <, EFX_PHY_MEDIA_INFO_PAGE_SIZE); 2423 2424 rc = efx_mcdi_get_phy_media_info(enp, 2425 mcdi_upper_page, (uint8_t)offset, (uint8_t)len, data); 2426 if (rc != 0) 2427 goto fail5; 2428 } 2429 2430 return (0); 2431 2432 fail5: 2433 EFSYS_PROBE(fail5); 2434 fail4: 2435 EFSYS_PROBE(fail4); 2436 fail3: 2437 EFSYS_PROBE(fail3); 2438 fail2: 2439 EFSYS_PROBE(fail2); 2440 fail1: 2441 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2442 2443 return (rc); 2444 } 2445 2446 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 2447 2448 #define INIT_EVQ_MAXNBUFS MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 2449 2450 #if EFX_OPTS_EF10() 2451 # if (INIT_EVQ_MAXNBUFS < EF10_EVQ_MAXNBUFS) 2452 # error "INIT_EVQ_MAXNBUFS too small" 2453 # endif 2454 #endif /* EFX_OPTS_EF10 */ 2455 #if EFSYS_OPT_RIVERHEAD 2456 # if (INIT_EVQ_MAXNBUFS < RHEAD_EVQ_MAXNBUFS) 2457 # error "INIT_EVQ_MAXNBUFS too small" 2458 # endif 2459 #endif /* EFSYS_OPT_RIVERHEAD */ 2460 2461 __checkReturn efx_rc_t 2462 efx_mcdi_init_evq( 2463 __in efx_nic_t *enp, 2464 __in unsigned int instance, 2465 __in efsys_mem_t *esmp, 2466 __in size_t nevs, 2467 __in uint32_t irq, 2468 __in uint32_t us, 2469 __in uint32_t flags, 2470 __in boolean_t low_latency) 2471 { 2472 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); 2473 efx_mcdi_req_t req; 2474 EFX_MCDI_DECLARE_BUF(payload, 2475 MC_CMD_INIT_EVQ_V2_IN_LEN(INIT_EVQ_MAXNBUFS), 2476 MC_CMD_INIT_EVQ_V2_OUT_LEN); 2477 boolean_t interrupting; 2478 int ev_extended_width; 2479 int ev_cut_through; 2480 int ev_merge; 2481 unsigned int evq_type; 2482 efx_qword_t *dma_addr; 2483 uint64_t addr; 2484 int npages; 2485 int i; 2486 efx_rc_t rc; 2487 2488 npages = efx_evq_nbufs(enp, nevs, flags); 2489 if (npages > INIT_EVQ_MAXNBUFS) { 2490 rc = EINVAL; 2491 goto fail1; 2492 } 2493 2494 req.emr_cmd = MC_CMD_INIT_EVQ; 2495 req.emr_in_buf = payload; 2496 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages); 2497 req.emr_out_buf = payload; 2498 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN; 2499 2500 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs); 2501 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance); 2502 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq); 2503 2504 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) == 2505 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT); 2506 2507 if (encp->enc_init_evq_v2_supported) { 2508 /* 2509 * On Medford the low latency license is required to enable RX 2510 * and event cut through and to disable RX batching. If event 2511 * queue type in flags is auto, we let the firmware decide the 2512 * settings to use. If the adapter has a low latency license, 2513 * it will choose the best settings for low latency, otherwise 2514 * it will choose the best settings for throughput. 2515 */ 2516 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) { 2517 case EFX_EVQ_FLAGS_TYPE_AUTO: 2518 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO; 2519 break; 2520 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT: 2521 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT; 2522 break; 2523 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY: 2524 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY; 2525 break; 2526 default: 2527 rc = EINVAL; 2528 goto fail2; 2529 } 2530 /* EvQ type controls merging, no manual settings */ 2531 ev_merge = 0; 2532 ev_cut_through = 0; 2533 } else { 2534 /* EvQ types other than manual are not supported */ 2535 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL; 2536 /* 2537 * On Huntington RX and TX event batching can only be requested 2538 * together (even if the datapath firmware doesn't actually 2539 * support RX batching). If event cut through is enabled no RX 2540 * batching will occur. 2541 * 2542 * So always enable RX and TX event batching, and enable event 2543 * cut through if we want low latency operation. 2544 */ 2545 ev_merge = 1; 2546 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) { 2547 case EFX_EVQ_FLAGS_TYPE_AUTO: 2548 ev_cut_through = low_latency ? 1 : 0; 2549 break; 2550 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT: 2551 ev_cut_through = 0; 2552 break; 2553 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY: 2554 ev_cut_through = 1; 2555 break; 2556 default: 2557 rc = EINVAL; 2558 goto fail2; 2559 } 2560 } 2561 2562 /* 2563 * On EF100, extended width event queues have a different event 2564 * descriptor layout and are used to support descriptor proxy queues. 2565 */ 2566 ev_extended_width = 0; 2567 #if EFSYS_OPT_EV_EXTENDED_WIDTH 2568 if (encp->enc_init_evq_extended_width_supported) { 2569 if (flags & EFX_EVQ_FLAGS_EXTENDED_WIDTH) 2570 ev_extended_width = 1; 2571 } 2572 #endif 2573 2574 MCDI_IN_POPULATE_DWORD_8(req, INIT_EVQ_V2_IN_FLAGS, 2575 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting, 2576 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0, 2577 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0, 2578 INIT_EVQ_V2_IN_FLAG_CUT_THRU, ev_cut_through, 2579 INIT_EVQ_V2_IN_FLAG_RX_MERGE, ev_merge, 2580 INIT_EVQ_V2_IN_FLAG_TX_MERGE, ev_merge, 2581 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type, 2582 INIT_EVQ_V2_IN_FLAG_EXT_WIDTH, ev_extended_width); 2583 2584 /* If the value is zero then disable the timer */ 2585 if (us == 0) { 2586 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE, 2587 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS); 2588 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0); 2589 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0); 2590 } else { 2591 unsigned int ticks; 2592 2593 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0) 2594 goto fail3; 2595 2596 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE, 2597 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF); 2598 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks); 2599 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks); 2600 } 2601 2602 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE, 2603 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS); 2604 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0); 2605 2606 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR); 2607 addr = EFSYS_MEM_ADDR(esmp); 2608 2609 for (i = 0; i < npages; i++) { 2610 EFX_POPULATE_QWORD_2(*dma_addr, 2611 EFX_DWORD_1, (uint32_t)(addr >> 32), 2612 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); 2613 2614 dma_addr++; 2615 addr += EFX_BUF_SIZE; 2616 } 2617 2618 efx_mcdi_execute(enp, &req); 2619 2620 if (req.emr_rc != 0) { 2621 rc = req.emr_rc; 2622 goto fail4; 2623 } 2624 2625 if (encp->enc_init_evq_v2_supported) { 2626 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) { 2627 rc = EMSGSIZE; 2628 goto fail5; 2629 } 2630 EFSYS_PROBE1(mcdi_evq_flags, uint32_t, 2631 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS)); 2632 } else { 2633 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) { 2634 rc = EMSGSIZE; 2635 goto fail6; 2636 } 2637 } 2638 2639 /* NOTE: ignore the returned IRQ param as firmware does not set it. */ 2640 2641 return (0); 2642 2643 fail6: 2644 EFSYS_PROBE(fail6); 2645 fail5: 2646 EFSYS_PROBE(fail5); 2647 fail4: 2648 EFSYS_PROBE(fail4); 2649 fail3: 2650 EFSYS_PROBE(fail3); 2651 fail2: 2652 EFSYS_PROBE(fail2); 2653 fail1: 2654 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2655 2656 return (rc); 2657 } 2658 2659 __checkReturn efx_rc_t 2660 efx_mcdi_fini_evq( 2661 __in efx_nic_t *enp, 2662 __in uint32_t instance) 2663 { 2664 efx_mcdi_req_t req; 2665 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_EVQ_IN_LEN, 2666 MC_CMD_FINI_EVQ_OUT_LEN); 2667 efx_rc_t rc; 2668 2669 req.emr_cmd = MC_CMD_FINI_EVQ; 2670 req.emr_in_buf = payload; 2671 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN; 2672 req.emr_out_buf = payload; 2673 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN; 2674 2675 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance); 2676 2677 efx_mcdi_execute_quiet(enp, &req); 2678 2679 if (req.emr_rc != 0) { 2680 rc = req.emr_rc; 2681 goto fail1; 2682 } 2683 2684 return (0); 2685 2686 fail1: 2687 /* 2688 * EALREADY is not an error, but indicates that the MC has rebooted and 2689 * that the EVQ has already been destroyed. 2690 */ 2691 if (rc != EALREADY) 2692 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2693 2694 return (rc); 2695 } 2696 2697 __checkReturn efx_rc_t 2698 efx_mcdi_init_rxq( 2699 __in efx_nic_t *enp, 2700 __in uint32_t ndescs, 2701 __in efx_evq_t *eep, 2702 __in uint32_t label, 2703 __in uint32_t instance, 2704 __in efsys_mem_t *esmp, 2705 __in const efx_mcdi_init_rxq_params_t *params) 2706 { 2707 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2708 efx_mcdi_req_t req; 2709 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V5_IN_LEN, 2710 MC_CMD_INIT_RXQ_V5_OUT_LEN); 2711 int npages = efx_rxq_nbufs(enp, ndescs); 2712 int i; 2713 efx_qword_t *dma_addr; 2714 uint64_t addr; 2715 efx_rc_t rc; 2716 uint32_t dma_mode; 2717 boolean_t want_outer_classes; 2718 boolean_t no_cont_ev; 2719 2720 EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs); 2721 2722 if ((esmp == NULL) || 2723 (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) { 2724 rc = EINVAL; 2725 goto fail1; 2726 } 2727 2728 no_cont_ev = (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV); 2729 if ((no_cont_ev == B_TRUE) && (params->disable_scatter == B_FALSE)) { 2730 /* TODO: Support scatter in NO_CONT_EV mode */ 2731 rc = EINVAL; 2732 goto fail2; 2733 } 2734 2735 if (params->ps_buf_size > 0) 2736 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM; 2737 else if (params->es_bufs_per_desc > 0) 2738 dma_mode = MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER; 2739 else 2740 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET; 2741 2742 if (encp->enc_tunnel_encapsulations_supported != 0 && 2743 !params->want_inner_classes) { 2744 /* 2745 * WANT_OUTER_CLASSES can only be specified on hardware which 2746 * supports tunnel encapsulation offloads, even though it is 2747 * effectively the behaviour the hardware gives. 2748 * 2749 * Also, on hardware which does support such offloads, older 2750 * firmware rejects the flag if the offloads are not supported 2751 * by the current firmware variant, which means this may fail if 2752 * the capabilities are not updated when the firmware variant 2753 * changes. This is not an issue on newer firmware, as it was 2754 * changed in bug 69842 (v6.4.2.1007) to permit this flag to be 2755 * specified on all firmware variants. 2756 */ 2757 want_outer_classes = B_TRUE; 2758 } else { 2759 want_outer_classes = B_FALSE; 2760 } 2761 2762 req.emr_cmd = MC_CMD_INIT_RXQ; 2763 req.emr_in_buf = payload; 2764 req.emr_in_length = MC_CMD_INIT_RXQ_V5_IN_LEN; 2765 req.emr_out_buf = payload; 2766 req.emr_out_length = MC_CMD_INIT_RXQ_V5_OUT_LEN; 2767 2768 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs); 2769 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, eep->ee_index); 2770 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label); 2771 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance); 2772 MCDI_IN_POPULATE_DWORD_10(req, INIT_RXQ_EXT_IN_FLAGS, 2773 INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0, 2774 INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0, 2775 INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0, 2776 INIT_RXQ_EXT_IN_CRC_MODE, 0, 2777 INIT_RXQ_EXT_IN_FLAG_PREFIX, 1, 2778 INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, params->disable_scatter, 2779 INIT_RXQ_EXT_IN_DMA_MODE, 2780 dma_mode, 2781 INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, params->ps_buf_size, 2782 INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes, 2783 INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV, no_cont_ev); 2784 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0); 2785 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, enp->en_vport_id); 2786 2787 if (params->es_bufs_per_desc > 0) { 2788 MCDI_IN_SET_DWORD(req, 2789 INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET, 2790 params->es_bufs_per_desc); 2791 MCDI_IN_SET_DWORD(req, 2792 INIT_RXQ_V3_IN_ES_MAX_DMA_LEN, params->es_max_dma_len); 2793 MCDI_IN_SET_DWORD(req, 2794 INIT_RXQ_V3_IN_ES_PACKET_STRIDE, params->es_buf_stride); 2795 MCDI_IN_SET_DWORD(req, 2796 INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT, 2797 params->hol_block_timeout); 2798 } 2799 2800 if (encp->enc_init_rxq_with_buffer_size) 2801 MCDI_IN_SET_DWORD(req, INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES, 2802 params->buf_size); 2803 2804 MCDI_IN_SET_DWORD(req, INIT_RXQ_V5_IN_RX_PREFIX_ID, params->prefix_id); 2805 2806 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR); 2807 addr = EFSYS_MEM_ADDR(esmp); 2808 2809 for (i = 0; i < npages; i++) { 2810 EFX_POPULATE_QWORD_2(*dma_addr, 2811 EFX_DWORD_1, (uint32_t)(addr >> 32), 2812 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); 2813 2814 dma_addr++; 2815 addr += EFX_BUF_SIZE; 2816 } 2817 2818 efx_mcdi_execute(enp, &req); 2819 2820 if (req.emr_rc != 0) { 2821 rc = req.emr_rc; 2822 goto fail3; 2823 } 2824 2825 return (0); 2826 2827 fail3: 2828 EFSYS_PROBE(fail3); 2829 fail2: 2830 EFSYS_PROBE(fail2); 2831 fail1: 2832 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2833 2834 return (rc); 2835 } 2836 2837 __checkReturn efx_rc_t 2838 efx_mcdi_fini_rxq( 2839 __in efx_nic_t *enp, 2840 __in uint32_t instance) 2841 { 2842 efx_mcdi_req_t req; 2843 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_RXQ_IN_LEN, 2844 MC_CMD_FINI_RXQ_OUT_LEN); 2845 efx_rc_t rc; 2846 2847 req.emr_cmd = MC_CMD_FINI_RXQ; 2848 req.emr_in_buf = payload; 2849 req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN; 2850 req.emr_out_buf = payload; 2851 req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN; 2852 2853 MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance); 2854 2855 efx_mcdi_execute_quiet(enp, &req); 2856 2857 if (req.emr_rc != 0) { 2858 rc = req.emr_rc; 2859 goto fail1; 2860 } 2861 2862 return (0); 2863 2864 fail1: 2865 /* 2866 * EALREADY is not an error, but indicates that the MC has rebooted and 2867 * that the RXQ has already been destroyed. 2868 */ 2869 if (rc != EALREADY) 2870 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2871 2872 return (rc); 2873 } 2874 2875 __checkReturn efx_rc_t 2876 efx_mcdi_init_txq( 2877 __in efx_nic_t *enp, 2878 __in uint32_t ndescs, 2879 __in uint32_t target_evq, 2880 __in uint32_t label, 2881 __in uint32_t instance, 2882 __in uint16_t flags, 2883 __in efsys_mem_t *esmp) 2884 { 2885 efx_mcdi_req_t req; 2886 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_TXQ_EXT_IN_LEN, 2887 MC_CMD_INIT_TXQ_OUT_LEN); 2888 efx_qword_t *dma_addr; 2889 uint64_t addr; 2890 int npages; 2891 int i; 2892 efx_rc_t rc; 2893 2894 EFSYS_ASSERT(MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM >= 2895 efx_txq_nbufs(enp, enp->en_nic_cfg.enc_txq_max_ndescs)); 2896 2897 if ((esmp == NULL) || 2898 (EFSYS_MEM_SIZE(esmp) < efx_txq_size(enp, ndescs))) { 2899 rc = EINVAL; 2900 goto fail1; 2901 } 2902 2903 npages = efx_txq_nbufs(enp, ndescs); 2904 if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) { 2905 rc = EINVAL; 2906 goto fail2; 2907 } 2908 2909 req.emr_cmd = MC_CMD_INIT_TXQ; 2910 req.emr_in_buf = payload; 2911 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages); 2912 req.emr_out_buf = payload; 2913 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN; 2914 2915 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, ndescs); 2916 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq); 2917 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label); 2918 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance); 2919 2920 MCDI_IN_POPULATE_DWORD_9(req, INIT_TXQ_IN_FLAGS, 2921 INIT_TXQ_IN_FLAG_BUFF_MODE, 0, 2922 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, 2923 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1, 2924 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, 2925 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1, 2926 INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN, 2927 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0, 2928 INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN, 2929 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0, 2930 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0, 2931 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0, 2932 INIT_TXQ_IN_CRC_MODE, 0, 2933 INIT_TXQ_IN_FLAG_TIMESTAMP, 0); 2934 2935 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0); 2936 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, enp->en_vport_id); 2937 2938 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR); 2939 addr = EFSYS_MEM_ADDR(esmp); 2940 2941 for (i = 0; i < npages; i++) { 2942 EFX_POPULATE_QWORD_2(*dma_addr, 2943 EFX_DWORD_1, (uint32_t)(addr >> 32), 2944 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); 2945 2946 dma_addr++; 2947 addr += EFX_BUF_SIZE; 2948 } 2949 2950 efx_mcdi_execute(enp, &req); 2951 2952 if (req.emr_rc != 0) { 2953 rc = req.emr_rc; 2954 goto fail3; 2955 } 2956 2957 return (0); 2958 2959 fail3: 2960 EFSYS_PROBE(fail3); 2961 fail2: 2962 EFSYS_PROBE(fail2); 2963 fail1: 2964 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2965 2966 return (rc); 2967 } 2968 2969 __checkReturn efx_rc_t 2970 efx_mcdi_fini_txq( 2971 __in efx_nic_t *enp, 2972 __in uint32_t instance) 2973 { 2974 efx_mcdi_req_t req; 2975 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_TXQ_IN_LEN, 2976 MC_CMD_FINI_TXQ_OUT_LEN); 2977 efx_rc_t rc; 2978 2979 req.emr_cmd = MC_CMD_FINI_TXQ; 2980 req.emr_in_buf = payload; 2981 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN; 2982 req.emr_out_buf = payload; 2983 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN; 2984 2985 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance); 2986 2987 efx_mcdi_execute_quiet(enp, &req); 2988 2989 if (req.emr_rc != 0) { 2990 rc = req.emr_rc; 2991 goto fail1; 2992 } 2993 2994 return (0); 2995 2996 fail1: 2997 /* 2998 * EALREADY is not an error, but indicates that the MC has rebooted and 2999 * that the TXQ has already been destroyed. 3000 */ 3001 if (rc != EALREADY) 3002 EFSYS_PROBE1(fail1, efx_rc_t, rc); 3003 3004 return (rc); 3005 } 3006 3007 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 3008 3009 #endif /* EFSYS_OPT_MCDI */ 3010