1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_IMPL_H 8 #define _SYS_EFX_IMPL_H 9 10 #include "efx.h" 11 #include "efx_regs.h" 12 #include "efx_regs_ef10.h" 13 #include "efx_regs_ef100.h" 14 #if EFSYS_OPT_MCDI 15 #include "efx_mcdi.h" 16 #endif /* EFSYS_OPT_MCDI */ 17 18 /* FIXME: Add definition for driver generated software events */ 19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 21 #endif 22 23 24 #if EFSYS_OPT_SIENA 25 #include "siena_impl.h" 26 #endif /* EFSYS_OPT_SIENA */ 27 28 #if EFSYS_OPT_HUNTINGTON 29 #include "hunt_impl.h" 30 #endif /* EFSYS_OPT_HUNTINGTON */ 31 32 #if EFSYS_OPT_MEDFORD 33 #include "medford_impl.h" 34 #endif /* EFSYS_OPT_MEDFORD */ 35 36 #if EFSYS_OPT_MEDFORD2 37 #include "medford2_impl.h" 38 #endif /* EFSYS_OPT_MEDFORD2 */ 39 40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 41 #include "ef10_impl.h" 42 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 43 44 #if EFSYS_OPT_RIVERHEAD 45 #include "rhead_impl.h" 46 #endif /* EFSYS_OPT_RIVERHEAD */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #define EFX_MOD_MCDI 0x00000001 53 #define EFX_MOD_PROBE 0x00000002 54 #define EFX_MOD_NVRAM 0x00000004 55 #define EFX_MOD_VPD 0x00000008 56 #define EFX_MOD_NIC 0x00000010 57 #define EFX_MOD_INTR 0x00000020 58 #define EFX_MOD_EV 0x00000040 59 #define EFX_MOD_RX 0x00000080 60 #define EFX_MOD_TX 0x00000100 61 #define EFX_MOD_PORT 0x00000200 62 #define EFX_MOD_MON 0x00000400 63 #define EFX_MOD_FILTER 0x00001000 64 #define EFX_MOD_LIC 0x00002000 65 #define EFX_MOD_TUNNEL 0x00004000 66 #define EFX_MOD_EVB 0x00008000 67 #define EFX_MOD_PROXY 0x00010000 68 #define EFX_MOD_VIRTIO 0x00020000 69 70 #define EFX_RESET_PHY 0x00000001 71 #define EFX_RESET_RXQ_ERR 0x00000002 72 #define EFX_RESET_TXQ_ERR 0x00000004 73 #define EFX_RESET_HW_UNAVAIL 0x00000008 74 75 typedef enum efx_mac_type_e { 76 EFX_MAC_INVALID = 0, 77 EFX_MAC_SIENA, 78 EFX_MAC_HUNTINGTON, 79 EFX_MAC_MEDFORD, 80 EFX_MAC_MEDFORD2, 81 EFX_MAC_RIVERHEAD, 82 EFX_MAC_NTYPES 83 } efx_mac_type_t; 84 85 typedef struct efx_ev_ops_s { 86 efx_rc_t (*eevo_init)(efx_nic_t *); 87 void (*eevo_fini)(efx_nic_t *); 88 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 89 efsys_mem_t *, size_t, uint32_t, 90 uint32_t, uint32_t, uint32_t, 91 efx_evq_t *); 92 void (*eevo_qdestroy)(efx_evq_t *); 93 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 94 void (*eevo_qpost)(efx_evq_t *, uint16_t); 95 void (*eevo_qpoll)(efx_evq_t *, unsigned int *, 96 const efx_ev_callbacks_t *, void *); 97 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 98 #if EFSYS_OPT_QSTATS 99 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 100 #endif 101 } efx_ev_ops_t; 102 103 typedef struct efx_tx_ops_s { 104 efx_rc_t (*etxo_init)(efx_nic_t *); 105 void (*etxo_fini)(efx_nic_t *); 106 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 107 unsigned int, unsigned int, 108 efsys_mem_t *, size_t, 109 uint32_t, uint16_t, 110 efx_evq_t *, efx_txq_t *, 111 unsigned int *); 112 void (*etxo_qdestroy)(efx_txq_t *); 113 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 114 unsigned int, unsigned int, 115 unsigned int *); 116 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 117 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 118 efx_rc_t (*etxo_qflush)(efx_txq_t *); 119 void (*etxo_qenable)(efx_txq_t *); 120 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 121 void (*etxo_qpio_disable)(efx_txq_t *); 122 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 123 size_t); 124 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 125 unsigned int *); 126 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 127 unsigned int, unsigned int, 128 unsigned int *); 129 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 130 size_t, boolean_t, 131 efx_desc_t *); 132 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 133 uint32_t, uint8_t, 134 efx_desc_t *); 135 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 136 uint16_t, uint32_t, uint16_t, 137 efx_desc_t *, int); 138 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 139 efx_desc_t *); 140 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 141 efx_desc_t *); 142 #if EFSYS_OPT_QSTATS 143 void (*etxo_qstats_update)(efx_txq_t *, 144 efsys_stat_t *); 145 #endif 146 } efx_tx_ops_t; 147 148 typedef union efx_rxq_type_data_u { 149 struct { 150 size_t ed_buf_size; 151 } ertd_default; 152 #if EFSYS_OPT_RX_PACKED_STREAM 153 struct { 154 uint32_t eps_buf_size; 155 } ertd_packed_stream; 156 #endif 157 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 158 struct { 159 uint32_t eessb_bufs_per_desc; 160 uint32_t eessb_max_dma_len; 161 uint32_t eessb_buf_stride; 162 uint32_t eessb_hol_block_timeout; 163 } ertd_es_super_buffer; 164 #endif 165 } efx_rxq_type_data_t; 166 167 typedef struct efx_rx_ops_s { 168 efx_rc_t (*erxo_init)(efx_nic_t *); 169 void (*erxo_fini)(efx_nic_t *); 170 #if EFSYS_OPT_RX_SCATTER 171 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 172 #endif 173 #if EFSYS_OPT_RX_SCALE 174 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 175 efx_rx_scale_context_type_t, 176 uint32_t, uint32_t *); 177 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 178 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 179 efx_rx_hash_alg_t, 180 efx_rx_hash_type_t, boolean_t); 181 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 182 uint8_t *, size_t); 183 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 184 unsigned int *, size_t); 185 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 186 uint8_t *); 187 #endif /* EFSYS_OPT_RX_SCALE */ 188 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 189 uint16_t *); 190 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 191 unsigned int, unsigned int, 192 unsigned int); 193 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 194 #if EFSYS_OPT_RX_PACKED_STREAM 195 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 196 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 197 uint32_t, uint32_t, 198 uint16_t *, uint32_t *, uint32_t *); 199 #endif 200 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 201 void (*erxo_qenable)(efx_rxq_t *); 202 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 203 unsigned int, efx_rxq_type_t, 204 const efx_rxq_type_data_t *, 205 efsys_mem_t *, size_t, uint32_t, 206 unsigned int, 207 efx_evq_t *, efx_rxq_t *); 208 void (*erxo_qdestroy)(efx_rxq_t *); 209 } efx_rx_ops_t; 210 211 typedef struct efx_mac_ops_s { 212 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 213 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 214 efx_rc_t (*emo_addr_set)(efx_nic_t *); 215 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 216 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 217 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 218 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 219 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 220 efx_rxq_t *, boolean_t); 221 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 222 #if EFSYS_OPT_LOOPBACK 223 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 224 efx_loopback_type_t); 225 #endif /* EFSYS_OPT_LOOPBACK */ 226 #if EFSYS_OPT_MAC_STATS 227 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 228 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 229 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 230 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 231 uint16_t, boolean_t); 232 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 233 efsys_stat_t *, uint32_t *); 234 #endif /* EFSYS_OPT_MAC_STATS */ 235 } efx_mac_ops_t; 236 237 typedef struct efx_phy_ops_s { 238 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 239 efx_rc_t (*epo_reset)(efx_nic_t *); 240 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 241 efx_rc_t (*epo_verify)(efx_nic_t *); 242 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 243 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 244 #if EFSYS_OPT_PHY_STATS 245 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 246 uint32_t *); 247 #endif /* EFSYS_OPT_PHY_STATS */ 248 #if EFSYS_OPT_BIST 249 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 250 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 251 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 252 efx_bist_result_t *, uint32_t *, 253 unsigned long *, size_t); 254 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 255 #endif /* EFSYS_OPT_BIST */ 256 } efx_phy_ops_t; 257 258 #if EFSYS_OPT_FILTER 259 260 /* 261 * Policy for replacing existing filter when inserting a new one. 262 * Note that all policies allow for storing the new lower priority 263 * filters as overridden by existing higher priority ones. It is needed 264 * to restore the lower priority filters on higher priority ones removal. 265 */ 266 typedef enum efx_filter_replacement_policy_e { 267 /* Cannot replace existing filter */ 268 EFX_FILTER_REPLACEMENT_NEVER, 269 /* Higher priority filters can replace lower priotiry ones */ 270 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY, 271 /* 272 * Higher priority filters can replace lower priority ones and 273 * equal priority filters can replace each other. 274 */ 275 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY, 276 } efx_filter_replacement_policy_t; 277 278 typedef struct efx_filter_ops_s { 279 efx_rc_t (*efo_init)(efx_nic_t *); 280 void (*efo_fini)(efx_nic_t *); 281 efx_rc_t (*efo_restore)(efx_nic_t *); 282 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 283 efx_filter_replacement_policy_t policy); 284 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 285 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 286 size_t, size_t *); 287 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 288 boolean_t, boolean_t, boolean_t, 289 uint8_t const *, uint32_t); 290 } efx_filter_ops_t; 291 292 LIBEFX_INTERNAL 293 extern __checkReturn efx_rc_t 294 efx_filter_reconfigure( 295 __in efx_nic_t *enp, 296 __in_ecount(6) uint8_t const *mac_addr, 297 __in boolean_t all_unicst, 298 __in boolean_t mulcst, 299 __in boolean_t all_mulcst, 300 __in boolean_t brdcst, 301 __in_ecount(6*count) uint8_t const *addrs, 302 __in uint32_t count); 303 304 #endif /* EFSYS_OPT_FILTER */ 305 306 #if EFSYS_OPT_TUNNEL 307 typedef struct efx_tunnel_ops_s { 308 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 309 void (*eto_fini)(efx_nic_t *); 310 } efx_tunnel_ops_t; 311 #endif /* EFSYS_OPT_TUNNEL */ 312 313 #if EFSYS_OPT_VIRTIO 314 typedef struct efx_virtio_ops_s { 315 efx_rc_t (*evo_virtio_qstart)(efx_virtio_vq_t *, 316 efx_virtio_vq_cfg_t *, 317 efx_virtio_vq_dyncfg_t *); 318 efx_rc_t (*evo_virtio_qstop)(efx_virtio_vq_t *, 319 efx_virtio_vq_dyncfg_t *); 320 efx_rc_t (*evo_get_doorbell_offset)(efx_virtio_vq_t *, 321 uint32_t *); 322 efx_rc_t (*evo_get_features)(efx_nic_t *, 323 efx_virtio_device_type_t, uint64_t *); 324 efx_rc_t (*evo_verify_features)(efx_nic_t *, 325 efx_virtio_device_type_t, uint64_t); 326 } efx_virtio_ops_t; 327 #endif /* EFSYS_OPT_VIRTIO */ 328 329 typedef struct efx_port_s { 330 efx_mac_type_t ep_mac_type; 331 uint32_t ep_phy_type; 332 uint8_t ep_port; 333 uint32_t ep_mac_pdu; 334 uint8_t ep_mac_addr[6]; 335 efx_link_mode_t ep_link_mode; 336 boolean_t ep_all_unicst; 337 boolean_t ep_all_unicst_inserted; 338 boolean_t ep_mulcst; 339 boolean_t ep_all_mulcst; 340 boolean_t ep_all_mulcst_inserted; 341 boolean_t ep_brdcst; 342 unsigned int ep_fcntl; 343 boolean_t ep_fcntl_autoneg; 344 efx_oword_t ep_multicst_hash[2]; 345 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 346 EFX_MAC_MULTICAST_LIST_MAX]; 347 uint32_t ep_mulcst_addr_count; 348 #if EFSYS_OPT_LOOPBACK 349 efx_loopback_type_t ep_loopback_type; 350 efx_link_mode_t ep_loopback_link_mode; 351 #endif /* EFSYS_OPT_LOOPBACK */ 352 #if EFSYS_OPT_PHY_FLAGS 353 uint32_t ep_phy_flags; 354 #endif /* EFSYS_OPT_PHY_FLAGS */ 355 #if EFSYS_OPT_PHY_LED_CONTROL 356 efx_phy_led_mode_t ep_phy_led_mode; 357 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 358 efx_phy_media_type_t ep_fixed_port_type; 359 efx_phy_media_type_t ep_module_type; 360 uint32_t ep_adv_cap_mask; 361 uint32_t ep_lp_cap_mask; 362 uint32_t ep_default_adv_cap_mask; 363 uint32_t ep_phy_cap_mask; 364 boolean_t ep_mac_drain; 365 #if EFSYS_OPT_BIST 366 efx_bist_type_t ep_current_bist; 367 #endif 368 const efx_mac_ops_t *ep_emop; 369 const efx_phy_ops_t *ep_epop; 370 } efx_port_t; 371 372 typedef struct efx_mon_ops_s { 373 #if EFSYS_OPT_MON_STATS 374 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 375 efx_mon_stat_value_t *); 376 efx_rc_t (*emo_limits_update)(efx_nic_t *, 377 efx_mon_stat_limits_t *); 378 #endif /* EFSYS_OPT_MON_STATS */ 379 } efx_mon_ops_t; 380 381 typedef struct efx_mon_s { 382 efx_mon_type_t em_type; 383 const efx_mon_ops_t *em_emop; 384 } efx_mon_t; 385 386 typedef struct efx_intr_ops_s { 387 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 388 void (*eio_enable)(efx_nic_t *); 389 void (*eio_disable)(efx_nic_t *); 390 void (*eio_disable_unlocked)(efx_nic_t *); 391 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 392 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 393 void (*eio_status_message)(efx_nic_t *, unsigned int, 394 boolean_t *); 395 void (*eio_fatal)(efx_nic_t *); 396 void (*eio_fini)(efx_nic_t *); 397 } efx_intr_ops_t; 398 399 typedef struct efx_intr_s { 400 const efx_intr_ops_t *ei_eiop; 401 efsys_mem_t *ei_esmp; 402 efx_intr_type_t ei_type; 403 unsigned int ei_level; 404 } efx_intr_t; 405 406 typedef struct efx_nic_ops_s { 407 efx_rc_t (*eno_probe)(efx_nic_t *); 408 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 409 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 410 efx_rc_t (*eno_reset)(efx_nic_t *); 411 efx_rc_t (*eno_init)(efx_nic_t *); 412 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 413 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 414 uint32_t *, size_t *); 415 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 416 void (*eno_set_hw_unavailable)(efx_nic_t *); 417 #if EFSYS_OPT_DIAG 418 efx_rc_t (*eno_register_test)(efx_nic_t *); 419 #endif /* EFSYS_OPT_DIAG */ 420 void (*eno_fini)(efx_nic_t *); 421 void (*eno_unprobe)(efx_nic_t *); 422 } efx_nic_ops_t; 423 424 #ifndef EFX_TXQ_LIMIT_TARGET 425 #define EFX_TXQ_LIMIT_TARGET 259 426 #endif 427 #ifndef EFX_RXQ_LIMIT_TARGET 428 #define EFX_RXQ_LIMIT_TARGET 512 429 #endif 430 431 typedef struct efx_nic_dma_region_s { 432 efsys_dma_addr_t endr_nic_base; 433 efsys_dma_addr_t endr_trgt_base; 434 unsigned int endr_window_log2; 435 unsigned int endr_align_log2; 436 boolean_t endr_inuse; 437 } efx_nic_dma_region_t; 438 439 typedef struct efx_nic_dma_region_info_s { 440 unsigned int endri_count; 441 efx_nic_dma_region_t *endri_regions; 442 } efx_nic_dma_region_info_t; 443 444 typedef struct efx_nic_dma_s { 445 union { 446 /* No configuration in the case flat mapping type */ 447 efx_nic_dma_region_info_t endu_region_info; 448 } end_u; 449 } efx_nic_dma_t; 450 451 #if EFSYS_OPT_FILTER 452 453 #if EFSYS_OPT_SIENA 454 455 typedef struct siena_filter_spec_s { 456 uint8_t sfs_type; 457 uint32_t sfs_flags; 458 uint32_t sfs_dmaq_id; 459 uint32_t sfs_dword[3]; 460 } siena_filter_spec_t; 461 462 typedef enum siena_filter_type_e { 463 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 464 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 465 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 466 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 467 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 468 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 469 470 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 471 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 472 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 473 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 474 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 475 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 476 477 EFX_SIENA_FILTER_NTYPES 478 } siena_filter_type_t; 479 480 typedef enum siena_filter_tbl_id_e { 481 EFX_SIENA_FILTER_TBL_RX_IP = 0, 482 EFX_SIENA_FILTER_TBL_RX_MAC, 483 EFX_SIENA_FILTER_TBL_TX_IP, 484 EFX_SIENA_FILTER_TBL_TX_MAC, 485 EFX_SIENA_FILTER_NTBLS 486 } siena_filter_tbl_id_t; 487 488 typedef struct siena_filter_tbl_s { 489 int sft_size; /* number of entries */ 490 int sft_used; /* active count */ 491 uint32_t *sft_bitmap; /* active bitmap */ 492 siena_filter_spec_t *sft_spec; /* array of saved specs */ 493 } siena_filter_tbl_t; 494 495 typedef struct siena_filter_s { 496 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 497 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 498 } siena_filter_t; 499 500 #endif /* EFSYS_OPT_SIENA */ 501 502 typedef struct efx_filter_s { 503 #if EFSYS_OPT_SIENA 504 siena_filter_t *ef_siena_filter; 505 #endif /* EFSYS_OPT_SIENA */ 506 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 507 ef10_filter_table_t *ef_ef10_filter_table; 508 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 509 } efx_filter_t; 510 511 #if EFSYS_OPT_SIENA 512 513 LIBEFX_INTERNAL 514 extern void 515 siena_filter_tbl_clear( 516 __in efx_nic_t *enp, 517 __in siena_filter_tbl_id_t tbl); 518 519 #endif /* EFSYS_OPT_SIENA */ 520 521 #endif /* EFSYS_OPT_FILTER */ 522 523 #if EFSYS_OPT_MCDI 524 525 #define EFX_TUNNEL_MAXNENTRIES (16) 526 527 #if EFSYS_OPT_TUNNEL 528 529 /* State of a UDP tunnel table entry */ 530 typedef enum efx_tunnel_udp_entry_state_e { 531 EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */ 532 EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */ 533 EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */ 534 } efx_tunnel_udp_entry_state_t; 535 536 #if EFSYS_OPT_RIVERHEAD 537 typedef uint32_t efx_vnic_encap_rule_handle_t; 538 #endif /* EFSYS_OPT_RIVERHEAD */ 539 540 typedef struct efx_tunnel_udp_entry_s { 541 uint16_t etue_port; /* host/cpu-endian */ 542 uint16_t etue_protocol; 543 boolean_t etue_busy; 544 efx_tunnel_udp_entry_state_t etue_state; 545 #if EFSYS_OPT_RIVERHEAD 546 efx_vnic_encap_rule_handle_t etue_handle; 547 #endif /* EFSYS_OPT_RIVERHEAD */ 548 } efx_tunnel_udp_entry_t; 549 550 typedef struct efx_tunnel_cfg_s { 551 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 552 unsigned int etc_udp_entries_num; 553 } efx_tunnel_cfg_t; 554 555 #endif /* EFSYS_OPT_TUNNEL */ 556 557 typedef struct efx_mcdi_ops_s { 558 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 559 void (*emco_send_request)(efx_nic_t *, void *, size_t, 560 void *, size_t); 561 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 562 boolean_t (*emco_poll_response)(efx_nic_t *); 563 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 564 void (*emco_fini)(efx_nic_t *); 565 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 566 efx_mcdi_feature_id_t, boolean_t *); 567 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 568 uint32_t *); 569 } efx_mcdi_ops_t; 570 571 typedef struct efx_mcdi_s { 572 const efx_mcdi_ops_t *em_emcop; 573 const efx_mcdi_transport_t *em_emtp; 574 efx_mcdi_iface_t em_emip; 575 } efx_mcdi_t; 576 577 #endif /* EFSYS_OPT_MCDI */ 578 579 #if EFSYS_OPT_NVRAM 580 581 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 582 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 583 584 typedef struct efx_nvram_ops_s { 585 #if EFSYS_OPT_DIAG 586 efx_rc_t (*envo_test)(efx_nic_t *); 587 #endif /* EFSYS_OPT_DIAG */ 588 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 589 uint32_t *); 590 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, 591 efx_nvram_info_t *); 592 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 593 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 594 unsigned int, caddr_t, size_t); 595 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 596 unsigned int, caddr_t, size_t); 597 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 598 unsigned int, size_t); 599 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 600 unsigned int, caddr_t, size_t); 601 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 602 uint32_t *); 603 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 604 uint32_t *, uint16_t *); 605 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 606 uint16_t *); 607 efx_rc_t (*envo_buffer_validate)(uint32_t, 608 caddr_t, size_t); 609 } efx_nvram_ops_t; 610 #endif /* EFSYS_OPT_NVRAM */ 611 612 #if EFSYS_OPT_VPD 613 typedef struct efx_vpd_ops_s { 614 efx_rc_t (*evpdo_init)(efx_nic_t *); 615 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 616 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 617 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 618 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 619 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 620 efx_vpd_value_t *); 621 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 622 efx_vpd_value_t *); 623 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 624 efx_vpd_value_t *, unsigned int *); 625 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 626 void (*evpdo_fini)(efx_nic_t *); 627 } efx_vpd_ops_t; 628 #endif /* EFSYS_OPT_VPD */ 629 630 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 631 632 LIBEFX_INTERNAL 633 extern __checkReturn efx_rc_t 634 efx_mcdi_nvram_partitions( 635 __in efx_nic_t *enp, 636 __out_bcount(size) caddr_t data, 637 __in size_t size, 638 __out unsigned int *npartnp); 639 640 LIBEFX_INTERNAL 641 extern __checkReturn efx_rc_t 642 efx_mcdi_nvram_metadata( 643 __in efx_nic_t *enp, 644 __in uint32_t partn, 645 __out uint32_t *subtypep, 646 __out_ecount(4) uint16_t version[4], 647 __out_bcount_opt(size) char *descp, 648 __in size_t size); 649 650 LIBEFX_INTERNAL 651 extern __checkReturn efx_rc_t 652 efx_mcdi_nvram_info( 653 __in efx_nic_t *enp, 654 __in uint32_t partn, 655 __out efx_nvram_info_t *eni); 656 657 LIBEFX_INTERNAL 658 extern __checkReturn efx_rc_t 659 efx_mcdi_nvram_update_start( 660 __in efx_nic_t *enp, 661 __in uint32_t partn); 662 663 LIBEFX_INTERNAL 664 extern __checkReturn efx_rc_t 665 efx_mcdi_nvram_read( 666 __in efx_nic_t *enp, 667 __in uint32_t partn, 668 __in uint32_t offset, 669 __out_bcount(size) caddr_t data, 670 __in size_t size, 671 __in uint32_t mode); 672 673 LIBEFX_INTERNAL 674 extern __checkReturn efx_rc_t 675 efx_mcdi_nvram_erase( 676 __in efx_nic_t *enp, 677 __in uint32_t partn, 678 __in uint32_t offset, 679 __in size_t size); 680 681 LIBEFX_INTERNAL 682 extern __checkReturn efx_rc_t 683 efx_mcdi_nvram_write( 684 __in efx_nic_t *enp, 685 __in uint32_t partn, 686 __in uint32_t offset, 687 __in_bcount(size) caddr_t data, 688 __in size_t size); 689 690 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 691 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 692 693 LIBEFX_INTERNAL 694 extern __checkReturn efx_rc_t 695 efx_mcdi_nvram_update_finish( 696 __in efx_nic_t *enp, 697 __in uint32_t partn, 698 __in boolean_t reboot, 699 __in uint32_t flags, 700 __out_opt uint32_t *verify_resultp); 701 702 #if EFSYS_OPT_DIAG 703 704 LIBEFX_INTERNAL 705 extern __checkReturn efx_rc_t 706 efx_mcdi_nvram_test( 707 __in efx_nic_t *enp, 708 __in uint32_t partn); 709 710 #endif /* EFSYS_OPT_DIAG */ 711 712 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 713 714 #if EFSYS_OPT_LICENSING 715 716 typedef struct efx_lic_ops_s { 717 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 718 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 719 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 720 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 721 size_t *, uint8_t *); 722 efx_rc_t (*elo_find_start) 723 (efx_nic_t *, caddr_t, size_t, uint32_t *); 724 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 725 uint32_t, uint32_t *); 726 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 727 uint32_t, uint32_t *, uint32_t *); 728 boolean_t (*elo_validate_key)(efx_nic_t *, 729 caddr_t, uint32_t); 730 efx_rc_t (*elo_read_key)(efx_nic_t *, 731 caddr_t, size_t, uint32_t, uint32_t, 732 caddr_t, size_t, uint32_t *); 733 efx_rc_t (*elo_write_key)(efx_nic_t *, 734 caddr_t, size_t, uint32_t, 735 caddr_t, uint32_t, uint32_t *); 736 efx_rc_t (*elo_delete_key)(efx_nic_t *, 737 caddr_t, size_t, uint32_t, 738 uint32_t, uint32_t, uint32_t *); 739 efx_rc_t (*elo_create_partition)(efx_nic_t *, 740 caddr_t, size_t); 741 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 742 caddr_t, size_t); 743 } efx_lic_ops_t; 744 745 #endif 746 747 #if EFSYS_OPT_EVB 748 749 struct efx_vswitch_s { 750 efx_nic_t *ev_enp; 751 efx_vswitch_id_t ev_vswitch_id; 752 uint32_t ev_num_vports; 753 /* 754 * Vport configuration array: index 0 to store PF configuration 755 * and next ev_num_vports-1 entries hold VFs configuration. 756 */ 757 efx_vport_config_t *ev_evcp; 758 }; 759 760 typedef struct efx_evb_ops_s { 761 efx_rc_t (*eeo_init)(efx_nic_t *); 762 void (*eeo_fini)(efx_nic_t *); 763 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); 764 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); 765 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, 766 efx_vport_type_t, uint16_t, 767 boolean_t, efx_vport_id_t *); 768 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, 769 efx_vport_id_t); 770 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, 771 efx_vport_id_t, uint8_t *); 772 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, 773 efx_vport_id_t, uint8_t *); 774 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, 775 efx_vport_id_t); 776 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, 777 efx_vport_id_t); 778 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, 779 efx_vport_id_t, uint32_t); 780 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t, 781 efx_vport_id_t, 782 uint16_t *, uint8_t *, 783 boolean_t *); 784 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t, 785 efx_vport_id_t, efsys_mem_t *); 786 } efx_evb_ops_t; 787 788 LIBEFX_INTERNAL 789 extern __checkReturn boolean_t 790 efx_is_zero_eth_addr( 791 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); 792 793 #endif /* EFSYS_OPT_EVB */ 794 795 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 796 797 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF 798 799 800 typedef struct efx_proxy_ops_s { 801 efx_rc_t (*epo_init)(efx_nic_t *); 802 void (*epo_fini)(efx_nic_t *); 803 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *, 804 efsys_mem_t *, efsys_mem_t *, 805 uint32_t, uint32_t *, size_t); 806 efx_rc_t (*epo_disable)(efx_nic_t *); 807 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t, 808 uint32_t, uint32_t, uint32_t); 809 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t, 810 uint32_t, uint32_t); 811 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t, 812 uint32_t, uint32_t); 813 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *); 814 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t, 815 uint32_t, uint32_t *); 816 } efx_proxy_ops_t; 817 818 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 819 820 #if EFSYS_OPT_MAE 821 822 typedef struct efx_mae_field_cap_s { 823 uint32_t emfc_support; 824 boolean_t emfc_mask_affects_class; 825 boolean_t emfc_match_affects_class; 826 } efx_mae_field_cap_t; 827 828 typedef struct efx_mae_s { 829 uint32_t em_max_n_action_prios; 830 /* 831 * The number of MAE field IDs recognised by the FW implementation. 832 * Any field ID greater than or equal to this value is unsupported. 833 */ 834 uint32_t em_max_nfields; 835 /** Action rule match field capabilities. */ 836 efx_mae_field_cap_t *em_action_rule_field_caps; 837 size_t em_action_rule_field_caps_size; 838 uint32_t em_max_n_outer_prios; 839 uint32_t em_encap_types_supported; 840 /** Outer rule match field capabilities. */ 841 efx_mae_field_cap_t *em_outer_rule_field_caps; 842 size_t em_outer_rule_field_caps_size; 843 uint32_t em_max_ncounters; 844 } efx_mae_t; 845 846 #endif /* EFSYS_OPT_MAE */ 847 848 #define EFX_DRV_VER_MAX 20 849 850 typedef struct efx_drv_cfg_s { 851 uint32_t edc_min_vi_count; 852 uint32_t edc_max_vi_count; 853 854 uint32_t edc_max_piobuf_count; 855 uint32_t edc_pio_alloc_size; 856 } efx_drv_cfg_t; 857 858 struct efx_nic_s { 859 uint32_t en_magic; 860 efx_family_t en_family; 861 uint32_t en_features; 862 efsys_identifier_t *en_esip; 863 efsys_lock_t *en_eslp; 864 efsys_bar_t *en_esbp; 865 unsigned int en_mod_flags; 866 unsigned int en_reset_flags; 867 efx_nic_cfg_t en_nic_cfg; 868 efx_drv_cfg_t en_drv_cfg; 869 efx_port_t en_port; 870 efx_mon_t en_mon; 871 efx_intr_t en_intr; 872 uint32_t en_ev_qcount; 873 uint32_t en_rx_qcount; 874 uint32_t en_tx_qcount; 875 const efx_nic_ops_t *en_enop; 876 const efx_ev_ops_t *en_eevop; 877 const efx_tx_ops_t *en_etxop; 878 const efx_rx_ops_t *en_erxop; 879 efx_fw_variant_t efv; 880 char en_drv_version[EFX_DRV_VER_MAX]; 881 efx_nic_dma_t en_dma; 882 #if EFSYS_OPT_FILTER 883 efx_filter_t en_filter; 884 const efx_filter_ops_t *en_efop; 885 #endif /* EFSYS_OPT_FILTER */ 886 #if EFSYS_OPT_TUNNEL 887 efx_tunnel_cfg_t en_tunnel_cfg; 888 const efx_tunnel_ops_t *en_etop; 889 #endif /* EFSYS_OPT_TUNNEL */ 890 #if EFSYS_OPT_MCDI 891 efx_mcdi_t en_mcdi; 892 #endif /* EFSYS_OPT_MCDI */ 893 #if EFSYS_OPT_NVRAM 894 uint32_t en_nvram_partn_locked; 895 const efx_nvram_ops_t *en_envop; 896 #endif /* EFSYS_OPT_NVRAM */ 897 #if EFSYS_OPT_VPD 898 const efx_vpd_ops_t *en_evpdop; 899 #endif /* EFSYS_OPT_VPD */ 900 #if EFSYS_OPT_VIRTIO 901 const efx_virtio_ops_t *en_evop; 902 #endif /* EFSYS_OPT_VPD */ 903 #if EFSYS_OPT_RX_SCALE 904 efx_rx_hash_support_t en_hash_support; 905 efx_rx_scale_context_type_t en_rss_context_type; 906 uint32_t en_rss_context; 907 #endif /* EFSYS_OPT_RX_SCALE */ 908 uint32_t en_vport_id; 909 #if EFSYS_OPT_LICENSING 910 const efx_lic_ops_t *en_elop; 911 boolean_t en_licensing_supported; 912 #endif 913 union { 914 #if EFSYS_OPT_SIENA 915 struct { 916 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 917 unsigned int enu_partn_mask; 918 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 919 #if EFSYS_OPT_VPD 920 caddr_t enu_svpd; 921 size_t enu_svpd_length; 922 #endif /* EFSYS_OPT_VPD */ 923 int enu_unused; 924 } siena; 925 #endif /* EFSYS_OPT_SIENA */ 926 int enu_unused; 927 } en_u; 928 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 929 union en_arch { 930 struct { 931 int ena_vi_base; 932 int ena_vi_count; 933 int ena_vi_shift; 934 uint32_t ena_fcw_base; 935 #if EFSYS_OPT_VPD 936 caddr_t ena_svpd; 937 size_t ena_svpd_length; 938 #endif /* EFSYS_OPT_VPD */ 939 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 940 uint32_t ena_piobuf_count; 941 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 942 uint32_t ena_pio_write_vi_base; 943 /* Memory BAR mapping regions */ 944 uint32_t ena_uc_mem_map_offset; 945 size_t ena_uc_mem_map_size; 946 uint32_t ena_wc_mem_map_offset; 947 size_t ena_wc_mem_map_size; 948 } ef10; 949 } en_arch; 950 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 951 #if EFSYS_OPT_EVB 952 const efx_evb_ops_t *en_eeop; 953 struct efx_vswitch_s *en_vswitchp; 954 #endif /* EFSYS_OPT_EVB */ 955 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 956 const efx_proxy_ops_t *en_epop; 957 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 958 #if EFSYS_OPT_MAE 959 efx_mae_t *en_maep; 960 #endif /* EFSYS_OPT_MAE */ 961 }; 962 963 #define EFX_FAMILY_IS_EF10(_enp) \ 964 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ 965 (_enp)->en_family == EFX_FAMILY_MEDFORD || \ 966 (_enp)->en_family == EFX_FAMILY_HUNTINGTON) 967 968 #define EFX_FAMILY_IS_EF100(_enp) \ 969 ((_enp)->en_family == EFX_FAMILY_RIVERHEAD) 970 971 972 #define EFX_NIC_MAGIC 0x02121996 973 974 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 975 const efx_ev_callbacks_t *, void *); 976 977 #if EFSYS_OPT_EV_EXTENDED_WIDTH 978 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *, 979 const efx_ev_callbacks_t *, void *); 980 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */ 981 982 typedef struct efx_evq_rxq_state_s { 983 unsigned int eers_rx_read_ptr; 984 unsigned int eers_rx_mask; 985 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 986 unsigned int eers_rx_stream_npackets; 987 boolean_t eers_rx_packed_stream; 988 #endif 989 #if EFSYS_OPT_RX_PACKED_STREAM 990 unsigned int eers_rx_packed_stream_credits; 991 #endif 992 } efx_evq_rxq_state_t; 993 994 struct efx_evq_s { 995 uint32_t ee_magic; 996 uint32_t ee_flags; 997 efx_nic_t *ee_enp; 998 unsigned int ee_index; 999 unsigned int ee_mask; 1000 efsys_mem_t *ee_esmp; 1001 #if EFSYS_OPT_QSTATS 1002 uint32_t ee_stat[EV_NQSTATS]; 1003 #endif /* EFSYS_OPT_QSTATS */ 1004 1005 efx_ev_handler_t ee_rx; 1006 efx_ev_handler_t ee_tx; 1007 efx_ev_handler_t ee_driver; 1008 efx_ev_handler_t ee_global; 1009 efx_ev_handler_t ee_drv_gen; 1010 #if EFSYS_OPT_MCDI 1011 efx_ev_handler_t ee_mcdi; 1012 #endif /* EFSYS_OPT_MCDI */ 1013 1014 #if EFSYS_OPT_DESC_PROXY 1015 efx_ev_ew_handler_t ee_ew_txq_desc; 1016 efx_ev_ew_handler_t ee_ew_virtq_desc; 1017 #endif /* EFSYS_OPT_DESC_PROXY */ 1018 1019 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 1020 }; 1021 1022 #define EFX_EVQ_MAGIC 0x08081997 1023 1024 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 1025 1026 #if EFSYS_OPT_QSTATS 1027 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 1028 do { \ 1029 (_eep)->ee_stat[_stat]++; \ 1030 _NOTE(CONSTANTCONDITION) \ 1031 } while (B_FALSE) 1032 #else 1033 #define EFX_EV_QSTAT_INCR(_eep, _stat) 1034 #endif 1035 1036 struct efx_rxq_s { 1037 uint32_t er_magic; 1038 efx_nic_t *er_enp; 1039 efx_evq_t *er_eep; 1040 unsigned int er_index; 1041 unsigned int er_label; 1042 unsigned int er_mask; 1043 size_t er_buf_size; 1044 efsys_mem_t *er_esmp; 1045 efx_evq_rxq_state_t *er_ev_qstate; 1046 efx_rx_prefix_layout_t er_prefix_layout; 1047 }; 1048 1049 #define EFX_RXQ_MAGIC 0x15022005 1050 1051 struct efx_txq_s { 1052 uint32_t et_magic; 1053 efx_nic_t *et_enp; 1054 unsigned int et_index; 1055 unsigned int et_mask; 1056 efsys_mem_t *et_esmp; 1057 #if EFSYS_OPT_HUNTINGTON 1058 uint32_t et_pio_bufnum; 1059 uint32_t et_pio_blknum; 1060 uint32_t et_pio_write_offset; 1061 uint32_t et_pio_offset; 1062 size_t et_pio_size; 1063 #endif 1064 #if EFSYS_OPT_QSTATS 1065 uint32_t et_stat[TX_NQSTATS]; 1066 #endif /* EFSYS_OPT_QSTATS */ 1067 }; 1068 1069 #define EFX_TXQ_MAGIC 0x05092005 1070 1071 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 1072 do { \ 1073 (_dst)[0] = (_src)[0]; \ 1074 (_dst)[1] = (_src)[1]; \ 1075 (_dst)[2] = (_src)[2]; \ 1076 (_dst)[3] = (_src)[3]; \ 1077 (_dst)[4] = (_src)[4]; \ 1078 (_dst)[5] = (_src)[5]; \ 1079 _NOTE(CONSTANTCONDITION) \ 1080 } while (B_FALSE) 1081 1082 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 1083 do { \ 1084 uint16_t *_d = (uint16_t *)(_dst); \ 1085 _d[0] = 0xffff; \ 1086 _d[1] = 0xffff; \ 1087 _d[2] = 0xffff; \ 1088 _NOTE(CONSTANTCONDITION) \ 1089 } while (B_FALSE) 1090 1091 #if EFSYS_OPT_CHECK_REG 1092 #define EFX_CHECK_REG(_enp, _reg) \ 1093 do { \ 1094 const char *name = #_reg; \ 1095 char min = name[4]; \ 1096 char max = name[5]; \ 1097 char rev; \ 1098 \ 1099 switch ((_enp)->en_family) { \ 1100 case EFX_FAMILY_SIENA: \ 1101 rev = 'C'; \ 1102 break; \ 1103 \ 1104 case EFX_FAMILY_HUNTINGTON: \ 1105 rev = 'D'; \ 1106 break; \ 1107 \ 1108 case EFX_FAMILY_MEDFORD: \ 1109 rev = 'E'; \ 1110 break; \ 1111 \ 1112 case EFX_FAMILY_MEDFORD2: \ 1113 rev = 'F'; \ 1114 break; \ 1115 \ 1116 case EFX_FAMILY_RIVERHEAD: \ 1117 rev = 'G'; \ 1118 break; \ 1119 \ 1120 default: \ 1121 rev = '?'; \ 1122 break; \ 1123 } \ 1124 \ 1125 EFSYS_ASSERT3S(rev, >=, min); \ 1126 EFSYS_ASSERT3S(rev, <=, max); \ 1127 \ 1128 _NOTE(CONSTANTCONDITION) \ 1129 } while (B_FALSE) 1130 #else 1131 #define EFX_CHECK_REG(_enp, _reg) do { \ 1132 _NOTE(CONSTANTCONDITION) \ 1133 } while (B_FALSE) 1134 #endif 1135 1136 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 1137 do { \ 1138 EFX_CHECK_REG((_enp), (_reg)); \ 1139 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 1140 (_edp), (_lock)); \ 1141 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 1142 uint32_t, _reg ## _OFST, \ 1143 uint32_t, (_edp)->ed_u32[0]); \ 1144 _NOTE(CONSTANTCONDITION) \ 1145 } while (B_FALSE) 1146 1147 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 1148 do { \ 1149 EFX_CHECK_REG((_enp), (_reg)); \ 1150 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 1151 uint32_t, _reg ## _OFST, \ 1152 uint32_t, (_edp)->ed_u32[0]); \ 1153 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 1154 (_edp), (_lock)); \ 1155 _NOTE(CONSTANTCONDITION) \ 1156 } while (B_FALSE) 1157 1158 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 1159 do { \ 1160 EFX_CHECK_REG((_enp), (_reg)); \ 1161 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 1162 (_eqp)); \ 1163 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 1164 uint32_t, _reg ## _OFST, \ 1165 uint32_t, (_eqp)->eq_u32[1], \ 1166 uint32_t, (_eqp)->eq_u32[0]); \ 1167 _NOTE(CONSTANTCONDITION) \ 1168 } while (B_FALSE) 1169 1170 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 1171 do { \ 1172 EFX_CHECK_REG((_enp), (_reg)); \ 1173 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 1174 uint32_t, _reg ## _OFST, \ 1175 uint32_t, (_eqp)->eq_u32[1], \ 1176 uint32_t, (_eqp)->eq_u32[0]); \ 1177 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 1178 (_eqp)); \ 1179 _NOTE(CONSTANTCONDITION) \ 1180 } while (B_FALSE) 1181 1182 #define EFX_BAR_READO(_enp, _reg, _eop) \ 1183 do { \ 1184 EFX_CHECK_REG((_enp), (_reg)); \ 1185 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 1186 (_eop), B_TRUE); \ 1187 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 1188 uint32_t, _reg ## _OFST, \ 1189 uint32_t, (_eop)->eo_u32[3], \ 1190 uint32_t, (_eop)->eo_u32[2], \ 1191 uint32_t, (_eop)->eo_u32[1], \ 1192 uint32_t, (_eop)->eo_u32[0]); \ 1193 _NOTE(CONSTANTCONDITION) \ 1194 } while (B_FALSE) 1195 1196 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 1197 do { \ 1198 EFX_CHECK_REG((_enp), (_reg)); \ 1199 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 1200 uint32_t, _reg ## _OFST, \ 1201 uint32_t, (_eop)->eo_u32[3], \ 1202 uint32_t, (_eop)->eo_u32[2], \ 1203 uint32_t, (_eop)->eo_u32[1], \ 1204 uint32_t, (_eop)->eo_u32[0]); \ 1205 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 1206 (_eop), B_TRUE); \ 1207 _NOTE(CONSTANTCONDITION) \ 1208 } while (B_FALSE) 1209 1210 /* 1211 * Accessors for memory BAR non-VI tables. 1212 * 1213 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 1214 * to ensure the correct runtime VI window size is used on Medford2. 1215 * 1216 * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control 1217 * window registers, to ensure the correct starting offset is used. 1218 * 1219 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 1220 */ 1221 1222 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 1223 do { \ 1224 EFX_CHECK_REG((_enp), (_reg)); \ 1225 EFSYS_BAR_READD((_enp)->en_esbp, \ 1226 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1227 (_edp), (_lock)); \ 1228 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 1229 uint32_t, (_index), \ 1230 uint32_t, _reg ## _OFST, \ 1231 uint32_t, (_edp)->ed_u32[0]); \ 1232 _NOTE(CONSTANTCONDITION) \ 1233 } while (B_FALSE) 1234 1235 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1236 do { \ 1237 EFX_CHECK_REG((_enp), (_reg)); \ 1238 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1239 uint32_t, (_index), \ 1240 uint32_t, _reg ## _OFST, \ 1241 uint32_t, (_edp)->ed_u32[0]); \ 1242 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1243 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1244 (_edp), (_lock)); \ 1245 _NOTE(CONSTANTCONDITION) \ 1246 } while (B_FALSE) 1247 1248 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1249 do { \ 1250 EFX_CHECK_REG((_enp), (_reg)); \ 1251 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1252 uint32_t, (_index), \ 1253 uint32_t, _reg ## _OFST, \ 1254 uint32_t, (_edp)->ed_u32[0]); \ 1255 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1256 (_reg ## _OFST + \ 1257 (3 * sizeof (efx_dword_t)) + \ 1258 ((_index) * _reg ## _STEP)), \ 1259 (_edp), (_lock)); \ 1260 _NOTE(CONSTANTCONDITION) \ 1261 } while (B_FALSE) 1262 1263 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1264 do { \ 1265 EFX_CHECK_REG((_enp), (_reg)); \ 1266 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1267 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1268 (_eqp)); \ 1269 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1270 uint32_t, (_index), \ 1271 uint32_t, _reg ## _OFST, \ 1272 uint32_t, (_eqp)->eq_u32[1], \ 1273 uint32_t, (_eqp)->eq_u32[0]); \ 1274 _NOTE(CONSTANTCONDITION) \ 1275 } while (B_FALSE) 1276 1277 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1278 do { \ 1279 EFX_CHECK_REG((_enp), (_reg)); \ 1280 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1281 uint32_t, (_index), \ 1282 uint32_t, _reg ## _OFST, \ 1283 uint32_t, (_eqp)->eq_u32[1], \ 1284 uint32_t, (_eqp)->eq_u32[0]); \ 1285 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1286 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1287 (_eqp)); \ 1288 _NOTE(CONSTANTCONDITION) \ 1289 } while (B_FALSE) 1290 1291 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1292 do { \ 1293 EFX_CHECK_REG((_enp), (_reg)); \ 1294 EFSYS_BAR_READO((_enp)->en_esbp, \ 1295 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1296 (_eop), (_lock)); \ 1297 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1298 uint32_t, (_index), \ 1299 uint32_t, _reg ## _OFST, \ 1300 uint32_t, (_eop)->eo_u32[3], \ 1301 uint32_t, (_eop)->eo_u32[2], \ 1302 uint32_t, (_eop)->eo_u32[1], \ 1303 uint32_t, (_eop)->eo_u32[0]); \ 1304 _NOTE(CONSTANTCONDITION) \ 1305 } while (B_FALSE) 1306 1307 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1308 do { \ 1309 EFX_CHECK_REG((_enp), (_reg)); \ 1310 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1311 uint32_t, (_index), \ 1312 uint32_t, _reg ## _OFST, \ 1313 uint32_t, (_eop)->eo_u32[3], \ 1314 uint32_t, (_eop)->eo_u32[2], \ 1315 uint32_t, (_eop)->eo_u32[1], \ 1316 uint32_t, (_eop)->eo_u32[0]); \ 1317 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1318 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1319 (_eop), (_lock)); \ 1320 _NOTE(CONSTANTCONDITION) \ 1321 } while (B_FALSE) 1322 1323 /* 1324 * Accessors for memory BAR function control window registers. 1325 * 1326 * The function control window is located at an offset which can be 1327 * non-zero in case of Riverhead. 1328 */ 1329 1330 #if EFSYS_OPT_RIVERHEAD 1331 1332 #define EFX_BAR_FCW_READD(_enp, _reg, _edp) \ 1333 do { \ 1334 EFX_CHECK_REG((_enp), (_reg)); \ 1335 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST + \ 1336 (_enp)->en_arch.ef10.ena_fcw_base, \ 1337 (_edp), B_FALSE); \ 1338 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg, \ 1339 uint32_t, _reg ## _OFST, \ 1340 uint32_t, (_edp)->ed_u32[0]); \ 1341 _NOTE(CONSTANTCONDITION) \ 1342 } while (B_FALSE) 1343 1344 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp) \ 1345 do { \ 1346 EFX_CHECK_REG((_enp), (_reg)); \ 1347 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg, \ 1348 uint32_t, _reg ## _OFST, \ 1349 uint32_t, (_edp)->ed_u32[0]); \ 1350 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST + \ 1351 (_enp)->en_arch.ef10.ena_fcw_base, \ 1352 (_edp), B_FALSE); \ 1353 _NOTE(CONSTANTCONDITION) \ 1354 } while (B_FALSE) 1355 1356 #endif /* EFSYS_OPT_RIVERHEAD */ 1357 1358 /* 1359 * Accessors for memory BAR per-VI registers. 1360 * 1361 * The VI window size is 8KB for Medford and all earlier controllers. 1362 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1363 */ 1364 1365 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1366 do { \ 1367 EFX_CHECK_REG((_enp), (_reg)); \ 1368 EFSYS_BAR_READD((_enp)->en_esbp, \ 1369 ((_reg ## _OFST) + \ 1370 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1371 (_edp), (_lock)); \ 1372 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1373 uint32_t, (_index), \ 1374 uint32_t, _reg ## _OFST, \ 1375 uint32_t, (_edp)->ed_u32[0]); \ 1376 _NOTE(CONSTANTCONDITION) \ 1377 } while (B_FALSE) 1378 1379 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1380 do { \ 1381 EFX_CHECK_REG((_enp), (_reg)); \ 1382 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1383 uint32_t, (_index), \ 1384 uint32_t, _reg ## _OFST, \ 1385 uint32_t, (_edp)->ed_u32[0]); \ 1386 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1387 ((_reg ## _OFST) + \ 1388 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1389 (_edp), (_lock)); \ 1390 _NOTE(CONSTANTCONDITION) \ 1391 } while (B_FALSE) 1392 1393 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1394 do { \ 1395 EFX_CHECK_REG((_enp), (_reg)); \ 1396 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1397 uint32_t, (_index), \ 1398 uint32_t, _reg ## _OFST, \ 1399 uint32_t, (_edp)->ed_u32[0]); \ 1400 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1401 ((_reg ## _OFST) + \ 1402 (2 * sizeof (efx_dword_t)) + \ 1403 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1404 (_edp), (_lock)); \ 1405 _NOTE(CONSTANTCONDITION) \ 1406 } while (B_FALSE) 1407 1408 /* 1409 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1410 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1411 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1412 * the need for locking in the host, and are the only ones known to be safe to 1413 * use 128-bites write with. 1414 */ 1415 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1416 do { \ 1417 EFX_CHECK_REG((_enp), (_reg)); \ 1418 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1419 const char *, #_reg, \ 1420 uint32_t, (_index), \ 1421 uint32_t, _reg ## _OFST, \ 1422 uint32_t, (_eop)->eo_u32[3], \ 1423 uint32_t, (_eop)->eo_u32[2], \ 1424 uint32_t, (_eop)->eo_u32[1], \ 1425 uint32_t, (_eop)->eo_u32[0]); \ 1426 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1427 (_reg ## _OFST + \ 1428 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1429 (_eop)); \ 1430 _NOTE(CONSTANTCONDITION) \ 1431 } while (B_FALSE) 1432 1433 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \ 1434 _wptr, _owptr) \ 1435 do { \ 1436 unsigned int _new = (_wptr); \ 1437 unsigned int _old = (_owptr); \ 1438 \ 1439 if ((_new) >= (_old)) \ 1440 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1441 (_old) * (_desc_size), \ 1442 ((_new) - (_old)) * (_desc_size)); \ 1443 else \ 1444 /* \ 1445 * It is cheaper to sync entire map than sync \ 1446 * two parts especially when offset/size are \ 1447 * ignored and entire map is synced in any case.\ 1448 */ \ 1449 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1450 0, \ 1451 (_entries) * (_desc_size)); \ 1452 _NOTE(CONSTANTCONDITION) \ 1453 } while (B_FALSE) 1454 1455 LIBEFX_INTERNAL 1456 extern __checkReturn efx_rc_t 1457 efx_mac_select( 1458 __in efx_nic_t *enp); 1459 1460 LIBEFX_INTERNAL 1461 extern void 1462 efx_mac_multicast_hash_compute( 1463 __in_ecount(6*count) uint8_t const *addrs, 1464 __in int count, 1465 __out efx_oword_t *hash_low, 1466 __out efx_oword_t *hash_high); 1467 1468 LIBEFX_INTERNAL 1469 extern __checkReturn efx_rc_t 1470 efx_phy_probe( 1471 __in efx_nic_t *enp); 1472 1473 LIBEFX_INTERNAL 1474 extern void 1475 efx_phy_unprobe( 1476 __in efx_nic_t *enp); 1477 1478 #if EFSYS_OPT_VPD 1479 1480 /* VPD utility functions */ 1481 1482 LIBEFX_INTERNAL 1483 extern __checkReturn efx_rc_t 1484 efx_vpd_hunk_length( 1485 __in_bcount(size) caddr_t data, 1486 __in size_t size, 1487 __out size_t *lengthp); 1488 1489 LIBEFX_INTERNAL 1490 extern __checkReturn efx_rc_t 1491 efx_vpd_hunk_verify( 1492 __in_bcount(size) caddr_t data, 1493 __in size_t size, 1494 __out_opt boolean_t *cksummedp); 1495 1496 LIBEFX_INTERNAL 1497 extern __checkReturn efx_rc_t 1498 efx_vpd_hunk_reinit( 1499 __in_bcount(size) caddr_t data, 1500 __in size_t size, 1501 __in boolean_t wantpid); 1502 1503 LIBEFX_INTERNAL 1504 extern __checkReturn efx_rc_t 1505 efx_vpd_hunk_get( 1506 __in_bcount(size) caddr_t data, 1507 __in size_t size, 1508 __in efx_vpd_tag_t tag, 1509 __in efx_vpd_keyword_t keyword, 1510 __out unsigned int *payloadp, 1511 __out uint8_t *paylenp); 1512 1513 LIBEFX_INTERNAL 1514 extern __checkReturn efx_rc_t 1515 efx_vpd_hunk_next( 1516 __in_bcount(size) caddr_t data, 1517 __in size_t size, 1518 __out efx_vpd_tag_t *tagp, 1519 __out efx_vpd_keyword_t *keyword, 1520 __out_opt unsigned int *payloadp, 1521 __out_opt uint8_t *paylenp, 1522 __inout unsigned int *contp); 1523 1524 LIBEFX_INTERNAL 1525 extern __checkReturn efx_rc_t 1526 efx_vpd_hunk_set( 1527 __in_bcount(size) caddr_t data, 1528 __in size_t size, 1529 __in efx_vpd_value_t *evvp); 1530 1531 #endif /* EFSYS_OPT_VPD */ 1532 1533 #if EFSYS_OPT_MCDI 1534 1535 LIBEFX_INTERNAL 1536 extern __checkReturn efx_rc_t 1537 efx_mcdi_set_workaround( 1538 __in efx_nic_t *enp, 1539 __in uint32_t type, 1540 __in boolean_t enabled, 1541 __out_opt uint32_t *flagsp); 1542 1543 LIBEFX_INTERNAL 1544 extern __checkReturn efx_rc_t 1545 efx_mcdi_get_workarounds( 1546 __in efx_nic_t *enp, 1547 __out_opt uint32_t *implementedp, 1548 __out_opt uint32_t *enabledp); 1549 1550 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1551 1552 LIBEFX_INTERNAL 1553 extern __checkReturn efx_rc_t 1554 efx_mcdi_intf_from_pcie( 1555 __in uint32_t pcie_intf, 1556 __out efx_pcie_interface_t *efx_intf); 1557 1558 LIBEFX_INTERNAL 1559 extern __checkReturn efx_rc_t 1560 efx_mcdi_init_evq( 1561 __in efx_nic_t *enp, 1562 __in unsigned int instance, 1563 __in efsys_mem_t *esmp, 1564 __in size_t nevs, 1565 __in uint32_t irq, 1566 __in uint32_t target_evq, 1567 __in uint32_t us, 1568 __in uint32_t flags, 1569 __in boolean_t low_latency); 1570 1571 LIBEFX_INTERNAL 1572 extern __checkReturn efx_rc_t 1573 efx_mcdi_fini_evq( 1574 __in efx_nic_t *enp, 1575 __in uint32_t instance); 1576 1577 typedef struct efx_mcdi_init_rxq_params_s { 1578 boolean_t disable_scatter; 1579 boolean_t want_inner_classes; 1580 uint32_t buf_size; 1581 uint32_t ps_buf_size; 1582 uint32_t es_bufs_per_desc; 1583 uint32_t es_max_dma_len; 1584 uint32_t es_buf_stride; 1585 uint32_t hol_block_timeout; 1586 uint32_t prefix_id; 1587 } efx_mcdi_init_rxq_params_t; 1588 1589 LIBEFX_INTERNAL 1590 extern __checkReturn efx_rc_t 1591 efx_mcdi_init_rxq( 1592 __in efx_nic_t *enp, 1593 __in uint32_t ndescs, 1594 __in efx_evq_t *eep, 1595 __in uint32_t label, 1596 __in uint32_t instance, 1597 __in efsys_mem_t *esmp, 1598 __in const efx_mcdi_init_rxq_params_t *params); 1599 1600 LIBEFX_INTERNAL 1601 extern __checkReturn efx_rc_t 1602 efx_mcdi_fini_rxq( 1603 __in efx_nic_t *enp, 1604 __in uint32_t instance); 1605 1606 LIBEFX_INTERNAL 1607 extern __checkReturn efx_rc_t 1608 efx_mcdi_init_txq( 1609 __in efx_nic_t *enp, 1610 __in uint32_t ndescs, 1611 __in uint32_t target_evq, 1612 __in uint32_t label, 1613 __in uint32_t instance, 1614 __in uint16_t flags, 1615 __in efsys_mem_t *esmp); 1616 1617 LIBEFX_INTERNAL 1618 extern __checkReturn efx_rc_t 1619 efx_mcdi_fini_txq( 1620 __in efx_nic_t *enp, 1621 __in uint32_t instance); 1622 1623 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1624 1625 #endif /* EFSYS_OPT_MCDI */ 1626 1627 #if EFSYS_OPT_MAC_STATS 1628 1629 /* 1630 * Closed range of stats (i.e. the first and the last are included). 1631 * The last must be greater or equal (if the range is one item only) to 1632 * the first. 1633 */ 1634 struct efx_mac_stats_range { 1635 efx_mac_stat_t first; 1636 efx_mac_stat_t last; 1637 }; 1638 1639 typedef enum efx_stats_action_e { 1640 EFX_STATS_CLEAR, 1641 EFX_STATS_UPLOAD, 1642 EFX_STATS_ENABLE_NOEVENTS, 1643 EFX_STATS_ENABLE_EVENTS, 1644 EFX_STATS_DISABLE, 1645 } efx_stats_action_t; 1646 1647 LIBEFX_INTERNAL 1648 extern efx_rc_t 1649 efx_mac_stats_mask_add_ranges( 1650 __inout_bcount(mask_size) uint32_t *maskp, 1651 __in size_t mask_size, 1652 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1653 __in unsigned int rng_count); 1654 1655 LIBEFX_INTERNAL 1656 extern __checkReturn efx_rc_t 1657 efx_mcdi_mac_stats( 1658 __in efx_nic_t *enp, 1659 __in uint32_t vport_id, 1660 __in_opt efsys_mem_t *esmp, 1661 __in efx_stats_action_t action, 1662 __in uint16_t period_ms); 1663 1664 #endif /* EFSYS_OPT_MAC_STATS */ 1665 1666 #if EFSYS_OPT_PCI 1667 1668 /* 1669 * Find the next extended capability in a PCI device's config space 1670 * with specified capability id. 1671 * Passing 0 offset makes the function search from the start. 1672 * If search succeeds, found capability is in modified offset. 1673 * 1674 * Returns ENOENT if a capability is not found. 1675 */ 1676 LIBEFX_INTERNAL 1677 extern __checkReturn efx_rc_t 1678 efx_pci_config_find_next_ext_cap( 1679 __in efsys_pci_config_t *espcp, 1680 __in const efx_pci_ops_t *epop, 1681 __in uint16_t cap_id, 1682 __inout size_t *offsetp); 1683 1684 /* 1685 * Get the next extended capability in a PCI device's config space. 1686 * Passing 0 offset makes the function get the first capability. 1687 * If search succeeds, the capability is in modified offset. 1688 * 1689 * Returns ENOENT if there is no next capability. 1690 */ 1691 LIBEFX_INTERNAL 1692 extern __checkReturn efx_rc_t 1693 efx_pci_config_next_ext_cap( 1694 __in efsys_pci_config_t *espcp, 1695 __in const efx_pci_ops_t *epop, 1696 __inout size_t *offsetp); 1697 1698 /* 1699 * Find the next Xilinx capabilities table location by searching 1700 * PCI extended capabilities. 1701 * 1702 * Returns ENOENT if a table location is not found. 1703 */ 1704 LIBEFX_INTERNAL 1705 extern __checkReturn efx_rc_t 1706 efx_pci_find_next_xilinx_cap_table( 1707 __in efsys_pci_config_t *espcp, 1708 __in const efx_pci_ops_t *epop, 1709 __inout size_t *pci_cap_offsetp, 1710 __out unsigned int *xilinx_tbl_barp, 1711 __out efsys_dma_addr_t *xilinx_tbl_offsetp); 1712 1713 /* 1714 * Read a Xilinx extended PCI capability that gives the location 1715 * of a Xilinx capabilities table. 1716 * 1717 * Returns ENOENT if the extended PCI capability does not contain 1718 * Xilinx capabilities table locator. 1719 */ 1720 LIBEFX_INTERNAL 1721 extern __checkReturn efx_rc_t 1722 efx_pci_read_ext_cap_xilinx_table( 1723 __in efsys_pci_config_t *espcp, 1724 __in const efx_pci_ops_t *epop, 1725 __in size_t cap_offset, 1726 __out unsigned int *barp, 1727 __out efsys_dma_addr_t *offsetp); 1728 1729 /* 1730 * Find a capability with specified format_id in a Xilinx capabilities table. 1731 * Searching is started from provided offset, taking skip_first into account. 1732 * If search succeeds, found capability is in modified offset. 1733 * 1734 * Returns ENOENT if an entry with specified format id is not found. 1735 */ 1736 LIBEFX_INTERNAL 1737 extern __checkReturn efx_rc_t 1738 efx_pci_xilinx_cap_tbl_find( 1739 __in efsys_bar_t *esbp, 1740 __in uint32_t format_id, 1741 __in boolean_t skip_first, 1742 __inout efsys_dma_addr_t *entry_offsetp); 1743 1744 #endif /* EFSYS_OPT_PCI */ 1745 1746 #if EFSYS_OPT_MAE 1747 1748 struct efx_mae_match_spec_s { 1749 efx_mae_rule_type_t emms_type; 1750 uint32_t emms_prio; 1751 union emms_mask_value_pairs { 1752 uint8_t action[ 1753 MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN]; 1754 uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN]; 1755 } emms_mask_value_pairs; 1756 uint8_t emms_outer_rule_recirc_id; 1757 }; 1758 1759 typedef enum efx_mae_action_e { 1760 /* These actions are strictly ordered. */ 1761 EFX_MAE_ACTION_DECAP, 1762 EFX_MAE_ACTION_VLAN_POP, 1763 EFX_MAE_ACTION_SET_DST_MAC, 1764 EFX_MAE_ACTION_SET_SRC_MAC, 1765 EFX_MAE_ACTION_DECR_IP_TTL, 1766 EFX_MAE_ACTION_VLAN_PUSH, 1767 EFX_MAE_ACTION_COUNT, 1768 EFX_MAE_ACTION_ENCAP, 1769 1770 /* 1771 * These actions are not strictly ordered and can 1772 * be passed by a client in any order (before DELIVER). 1773 * However, these enumerants must be kept compactly 1774 * in the end of the enumeration (before DELIVER). 1775 */ 1776 EFX_MAE_ACTION_FLAG, 1777 EFX_MAE_ACTION_MARK, 1778 1779 /* DELIVER is always the last action. */ 1780 EFX_MAE_ACTION_DELIVER, 1781 1782 EFX_MAE_NACTIONS 1783 } efx_mae_action_t; 1784 1785 /* MAE VLAN_POP action can handle 1 or 2 tags. */ 1786 #define EFX_MAE_VLAN_POP_MAX_NTAGS (2) 1787 1788 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */ 1789 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS (2) 1790 1791 typedef struct efx_mae_action_vlan_push_s { 1792 uint16_t emavp_tpid_be; 1793 uint16_t emavp_tci_be; 1794 } efx_mae_action_vlan_push_t; 1795 1796 typedef struct efx_mae_actions_rsrc_s { 1797 efx_mae_mac_id_t emar_dst_mac_id; 1798 efx_mae_mac_id_t emar_src_mac_id; 1799 efx_mae_eh_id_t emar_eh_id; 1800 efx_counter_t emar_counter_id; 1801 } efx_mae_actions_rsrc_t; 1802 1803 struct efx_mae_actions_s { 1804 /* Bitmap of actions in spec, indexed by action type */ 1805 uint32_t ema_actions; 1806 1807 unsigned int ema_n_vlan_tags_to_pop; 1808 unsigned int ema_n_vlan_tags_to_push; 1809 efx_mae_action_vlan_push_t ema_vlan_push_descs[ 1810 EFX_MAE_VLAN_PUSH_MAX_NTAGS]; 1811 unsigned int ema_n_count_actions; 1812 uint32_t ema_mark_value; 1813 efx_mport_sel_t ema_deliver_mport; 1814 1815 /* 1816 * Always keep this at the end of the struct since 1817 * efx_mae_action_set_specs_equal() relies on that 1818 * to make sure that resource IDs are not compared. 1819 */ 1820 efx_mae_actions_rsrc_t ema_rsrc; 1821 1822 /* 1823 * A copy of encp->enc_mae_aset_v2_supported. 1824 * It is set by efx_mae_action_set_spec_init(). 1825 * This value is ignored on spec comparisons. 1826 */ 1827 boolean_t ema_v2_is_supported; 1828 }; 1829 1830 #endif /* EFSYS_OPT_MAE */ 1831 1832 #if EFSYS_OPT_VIRTIO 1833 1834 #define EFX_VQ_MAGIC 0x026011950 1835 1836 typedef enum efx_virtio_vq_state_e { 1837 EFX_VIRTIO_VQ_STATE_UNKNOWN = 0, 1838 EFX_VIRTIO_VQ_STATE_INITIALIZED, 1839 EFX_VIRTIO_VQ_STATE_STARTED, 1840 EFX_VIRTIO_VQ_NSTATES 1841 } efx_virtio_vq_state_t; 1842 1843 struct efx_virtio_vq_s { 1844 uint32_t evv_magic; 1845 efx_nic_t *evv_enp; 1846 efx_virtio_vq_state_t evv_state; 1847 uint32_t evv_vi_index; 1848 efx_virtio_vq_type_t evv_type; 1849 uint16_t evv_target_vf; 1850 }; 1851 1852 #endif /* EFSYS_OPT_VIRTIO */ 1853 1854 #ifdef __cplusplus 1855 } 1856 #endif 1857 1858 #endif /* _SYS_EFX_IMPL_H */ 1859