1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2020 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_IMPL_H 8 #define _SYS_EFX_IMPL_H 9 10 #include "efx.h" 11 #include "efx_regs.h" 12 #include "efx_regs_ef10.h" 13 #include "efx_regs_ef100.h" 14 #if EFSYS_OPT_MCDI 15 #include "efx_mcdi.h" 16 #endif /* EFSYS_OPT_MCDI */ 17 18 /* FIXME: Add definition for driver generated software events */ 19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 21 #endif 22 23 24 #if EFSYS_OPT_SIENA 25 #include "siena_impl.h" 26 #endif /* EFSYS_OPT_SIENA */ 27 28 #if EFSYS_OPT_HUNTINGTON 29 #include "hunt_impl.h" 30 #endif /* EFSYS_OPT_HUNTINGTON */ 31 32 #if EFSYS_OPT_MEDFORD 33 #include "medford_impl.h" 34 #endif /* EFSYS_OPT_MEDFORD */ 35 36 #if EFSYS_OPT_MEDFORD2 37 #include "medford2_impl.h" 38 #endif /* EFSYS_OPT_MEDFORD2 */ 39 40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 41 #include "ef10_impl.h" 42 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 43 44 #if EFSYS_OPT_RIVERHEAD 45 #include "rhead_impl.h" 46 #endif /* EFSYS_OPT_RIVERHEAD */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #define EFX_MOD_MCDI 0x00000001 53 #define EFX_MOD_PROBE 0x00000002 54 #define EFX_MOD_NVRAM 0x00000004 55 #define EFX_MOD_VPD 0x00000008 56 #define EFX_MOD_NIC 0x00000010 57 #define EFX_MOD_INTR 0x00000020 58 #define EFX_MOD_EV 0x00000040 59 #define EFX_MOD_RX 0x00000080 60 #define EFX_MOD_TX 0x00000100 61 #define EFX_MOD_PORT 0x00000200 62 #define EFX_MOD_MON 0x00000400 63 #define EFX_MOD_FILTER 0x00001000 64 #define EFX_MOD_LIC 0x00002000 65 #define EFX_MOD_TUNNEL 0x00004000 66 #define EFX_MOD_EVB 0x00008000 67 #define EFX_MOD_PROXY 0x00010000 68 69 #define EFX_RESET_PHY 0x00000001 70 #define EFX_RESET_RXQ_ERR 0x00000002 71 #define EFX_RESET_TXQ_ERR 0x00000004 72 #define EFX_RESET_HW_UNAVAIL 0x00000008 73 74 typedef enum efx_mac_type_e { 75 EFX_MAC_INVALID = 0, 76 EFX_MAC_SIENA, 77 EFX_MAC_HUNTINGTON, 78 EFX_MAC_MEDFORD, 79 EFX_MAC_MEDFORD2, 80 EFX_MAC_RIVERHEAD, 81 EFX_MAC_NTYPES 82 } efx_mac_type_t; 83 84 typedef struct efx_ev_ops_s { 85 efx_rc_t (*eevo_init)(efx_nic_t *); 86 void (*eevo_fini)(efx_nic_t *); 87 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 88 efsys_mem_t *, size_t, uint32_t, 89 uint32_t, uint32_t, efx_evq_t *); 90 void (*eevo_qdestroy)(efx_evq_t *); 91 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 92 void (*eevo_qpost)(efx_evq_t *, uint16_t); 93 void (*eevo_qpoll)(efx_evq_t *, unsigned int *, 94 const efx_ev_callbacks_t *, void *); 95 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 96 #if EFSYS_OPT_QSTATS 97 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 98 #endif 99 } efx_ev_ops_t; 100 101 typedef struct efx_tx_ops_s { 102 efx_rc_t (*etxo_init)(efx_nic_t *); 103 void (*etxo_fini)(efx_nic_t *); 104 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 105 unsigned int, unsigned int, 106 efsys_mem_t *, size_t, 107 uint32_t, uint16_t, 108 efx_evq_t *, efx_txq_t *, 109 unsigned int *); 110 void (*etxo_qdestroy)(efx_txq_t *); 111 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 112 unsigned int, unsigned int, 113 unsigned int *); 114 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 115 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 116 efx_rc_t (*etxo_qflush)(efx_txq_t *); 117 void (*etxo_qenable)(efx_txq_t *); 118 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 119 void (*etxo_qpio_disable)(efx_txq_t *); 120 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 121 size_t); 122 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 123 unsigned int *); 124 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 125 unsigned int, unsigned int, 126 unsigned int *); 127 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 128 size_t, boolean_t, 129 efx_desc_t *); 130 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 131 uint32_t, uint8_t, 132 efx_desc_t *); 133 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 134 uint16_t, uint32_t, uint16_t, 135 efx_desc_t *, int); 136 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 137 efx_desc_t *); 138 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 139 efx_desc_t *); 140 #if EFSYS_OPT_QSTATS 141 void (*etxo_qstats_update)(efx_txq_t *, 142 efsys_stat_t *); 143 #endif 144 } efx_tx_ops_t; 145 146 typedef union efx_rxq_type_data_u { 147 struct { 148 size_t ed_buf_size; 149 } ertd_default; 150 #if EFSYS_OPT_RX_PACKED_STREAM 151 struct { 152 uint32_t eps_buf_size; 153 } ertd_packed_stream; 154 #endif 155 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 156 struct { 157 uint32_t eessb_bufs_per_desc; 158 uint32_t eessb_max_dma_len; 159 uint32_t eessb_buf_stride; 160 uint32_t eessb_hol_block_timeout; 161 } ertd_es_super_buffer; 162 #endif 163 } efx_rxq_type_data_t; 164 165 typedef struct efx_rx_ops_s { 166 efx_rc_t (*erxo_init)(efx_nic_t *); 167 void (*erxo_fini)(efx_nic_t *); 168 #if EFSYS_OPT_RX_SCATTER 169 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 170 #endif 171 #if EFSYS_OPT_RX_SCALE 172 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 173 efx_rx_scale_context_type_t, 174 uint32_t, uint32_t *); 175 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 176 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 177 efx_rx_hash_alg_t, 178 efx_rx_hash_type_t, boolean_t); 179 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 180 uint8_t *, size_t); 181 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 182 unsigned int *, size_t); 183 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 184 uint8_t *); 185 #endif /* EFSYS_OPT_RX_SCALE */ 186 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 187 uint16_t *); 188 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 189 unsigned int, unsigned int, 190 unsigned int); 191 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 192 #if EFSYS_OPT_RX_PACKED_STREAM 193 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 194 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 195 uint32_t, uint32_t, 196 uint16_t *, uint32_t *, uint32_t *); 197 #endif 198 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 199 void (*erxo_qenable)(efx_rxq_t *); 200 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 201 unsigned int, efx_rxq_type_t, 202 const efx_rxq_type_data_t *, 203 efsys_mem_t *, size_t, uint32_t, 204 unsigned int, 205 efx_evq_t *, efx_rxq_t *); 206 void (*erxo_qdestroy)(efx_rxq_t *); 207 } efx_rx_ops_t; 208 209 typedef struct efx_mac_ops_s { 210 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 211 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 212 efx_rc_t (*emo_addr_set)(efx_nic_t *); 213 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 214 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 215 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 216 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 217 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 218 efx_rxq_t *, boolean_t); 219 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 220 #if EFSYS_OPT_LOOPBACK 221 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 222 efx_loopback_type_t); 223 #endif /* EFSYS_OPT_LOOPBACK */ 224 #if EFSYS_OPT_MAC_STATS 225 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 226 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 227 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 228 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 229 uint16_t, boolean_t); 230 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 231 efsys_stat_t *, uint32_t *); 232 #endif /* EFSYS_OPT_MAC_STATS */ 233 } efx_mac_ops_t; 234 235 typedef struct efx_phy_ops_s { 236 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 237 efx_rc_t (*epo_reset)(efx_nic_t *); 238 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 239 efx_rc_t (*epo_verify)(efx_nic_t *); 240 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 241 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 242 #if EFSYS_OPT_PHY_STATS 243 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 244 uint32_t *); 245 #endif /* EFSYS_OPT_PHY_STATS */ 246 #if EFSYS_OPT_BIST 247 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 248 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 249 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 250 efx_bist_result_t *, uint32_t *, 251 unsigned long *, size_t); 252 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 253 #endif /* EFSYS_OPT_BIST */ 254 } efx_phy_ops_t; 255 256 #if EFSYS_OPT_FILTER 257 258 /* 259 * Policy for replacing existing filter when inserting a new one. 260 * Note that all policies allow for storing the new lower priority 261 * filters as overridden by existing higher priority ones. It is needed 262 * to restore the lower priority filters on higher priority ones removal. 263 */ 264 typedef enum efx_filter_replacement_policy_e { 265 /* Cannot replace existing filter */ 266 EFX_FILTER_REPLACEMENT_NEVER, 267 /* Higher priority filters can replace lower priotiry ones */ 268 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY, 269 /* 270 * Higher priority filters can replace lower priority ones and 271 * equal priority filters can replace each other. 272 */ 273 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY, 274 } efx_filter_replacement_policy_t; 275 276 typedef struct efx_filter_ops_s { 277 efx_rc_t (*efo_init)(efx_nic_t *); 278 void (*efo_fini)(efx_nic_t *); 279 efx_rc_t (*efo_restore)(efx_nic_t *); 280 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 281 efx_filter_replacement_policy_t policy); 282 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 283 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 284 size_t, size_t *); 285 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 286 boolean_t, boolean_t, boolean_t, 287 uint8_t const *, uint32_t); 288 } efx_filter_ops_t; 289 290 LIBEFX_INTERNAL 291 extern __checkReturn efx_rc_t 292 efx_filter_reconfigure( 293 __in efx_nic_t *enp, 294 __in_ecount(6) uint8_t const *mac_addr, 295 __in boolean_t all_unicst, 296 __in boolean_t mulcst, 297 __in boolean_t all_mulcst, 298 __in boolean_t brdcst, 299 __in_ecount(6*count) uint8_t const *addrs, 300 __in uint32_t count); 301 302 #endif /* EFSYS_OPT_FILTER */ 303 304 #if EFSYS_OPT_TUNNEL 305 typedef struct efx_tunnel_ops_s { 306 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 307 void (*eto_fini)(efx_nic_t *); 308 } efx_tunnel_ops_t; 309 #endif /* EFSYS_OPT_TUNNEL */ 310 311 typedef struct efx_port_s { 312 efx_mac_type_t ep_mac_type; 313 uint32_t ep_phy_type; 314 uint8_t ep_port; 315 uint32_t ep_mac_pdu; 316 uint8_t ep_mac_addr[6]; 317 efx_link_mode_t ep_link_mode; 318 boolean_t ep_all_unicst; 319 boolean_t ep_all_unicst_inserted; 320 boolean_t ep_mulcst; 321 boolean_t ep_all_mulcst; 322 boolean_t ep_all_mulcst_inserted; 323 boolean_t ep_brdcst; 324 unsigned int ep_fcntl; 325 boolean_t ep_fcntl_autoneg; 326 efx_oword_t ep_multicst_hash[2]; 327 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 328 EFX_MAC_MULTICAST_LIST_MAX]; 329 uint32_t ep_mulcst_addr_count; 330 #if EFSYS_OPT_LOOPBACK 331 efx_loopback_type_t ep_loopback_type; 332 efx_link_mode_t ep_loopback_link_mode; 333 #endif /* EFSYS_OPT_LOOPBACK */ 334 #if EFSYS_OPT_PHY_FLAGS 335 uint32_t ep_phy_flags; 336 #endif /* EFSYS_OPT_PHY_FLAGS */ 337 #if EFSYS_OPT_PHY_LED_CONTROL 338 efx_phy_led_mode_t ep_phy_led_mode; 339 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 340 efx_phy_media_type_t ep_fixed_port_type; 341 efx_phy_media_type_t ep_module_type; 342 uint32_t ep_adv_cap_mask; 343 uint32_t ep_lp_cap_mask; 344 uint32_t ep_default_adv_cap_mask; 345 uint32_t ep_phy_cap_mask; 346 boolean_t ep_mac_drain; 347 #if EFSYS_OPT_BIST 348 efx_bist_type_t ep_current_bist; 349 #endif 350 const efx_mac_ops_t *ep_emop; 351 const efx_phy_ops_t *ep_epop; 352 } efx_port_t; 353 354 typedef struct efx_mon_ops_s { 355 #if EFSYS_OPT_MON_STATS 356 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 357 efx_mon_stat_value_t *); 358 efx_rc_t (*emo_limits_update)(efx_nic_t *, 359 efx_mon_stat_limits_t *); 360 #endif /* EFSYS_OPT_MON_STATS */ 361 } efx_mon_ops_t; 362 363 typedef struct efx_mon_s { 364 efx_mon_type_t em_type; 365 const efx_mon_ops_t *em_emop; 366 } efx_mon_t; 367 368 typedef struct efx_intr_ops_s { 369 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 370 void (*eio_enable)(efx_nic_t *); 371 void (*eio_disable)(efx_nic_t *); 372 void (*eio_disable_unlocked)(efx_nic_t *); 373 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 374 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 375 void (*eio_status_message)(efx_nic_t *, unsigned int, 376 boolean_t *); 377 void (*eio_fatal)(efx_nic_t *); 378 void (*eio_fini)(efx_nic_t *); 379 } efx_intr_ops_t; 380 381 typedef struct efx_intr_s { 382 const efx_intr_ops_t *ei_eiop; 383 efsys_mem_t *ei_esmp; 384 efx_intr_type_t ei_type; 385 unsigned int ei_level; 386 } efx_intr_t; 387 388 typedef struct efx_nic_ops_s { 389 efx_rc_t (*eno_probe)(efx_nic_t *); 390 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 391 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 392 efx_rc_t (*eno_reset)(efx_nic_t *); 393 efx_rc_t (*eno_init)(efx_nic_t *); 394 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 395 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 396 uint32_t *, size_t *); 397 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 398 void (*eno_set_hw_unavailable)(efx_nic_t *); 399 #if EFSYS_OPT_DIAG 400 efx_rc_t (*eno_register_test)(efx_nic_t *); 401 #endif /* EFSYS_OPT_DIAG */ 402 void (*eno_fini)(efx_nic_t *); 403 void (*eno_unprobe)(efx_nic_t *); 404 } efx_nic_ops_t; 405 406 #ifndef EFX_TXQ_LIMIT_TARGET 407 #define EFX_TXQ_LIMIT_TARGET 259 408 #endif 409 #ifndef EFX_RXQ_LIMIT_TARGET 410 #define EFX_RXQ_LIMIT_TARGET 512 411 #endif 412 413 414 #if EFSYS_OPT_FILTER 415 416 #if EFSYS_OPT_SIENA 417 418 typedef struct siena_filter_spec_s { 419 uint8_t sfs_type; 420 uint32_t sfs_flags; 421 uint32_t sfs_dmaq_id; 422 uint32_t sfs_dword[3]; 423 } siena_filter_spec_t; 424 425 typedef enum siena_filter_type_e { 426 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 427 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 428 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 429 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 430 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 431 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 432 433 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 434 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 435 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 436 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 437 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 438 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 439 440 EFX_SIENA_FILTER_NTYPES 441 } siena_filter_type_t; 442 443 typedef enum siena_filter_tbl_id_e { 444 EFX_SIENA_FILTER_TBL_RX_IP = 0, 445 EFX_SIENA_FILTER_TBL_RX_MAC, 446 EFX_SIENA_FILTER_TBL_TX_IP, 447 EFX_SIENA_FILTER_TBL_TX_MAC, 448 EFX_SIENA_FILTER_NTBLS 449 } siena_filter_tbl_id_t; 450 451 typedef struct siena_filter_tbl_s { 452 int sft_size; /* number of entries */ 453 int sft_used; /* active count */ 454 uint32_t *sft_bitmap; /* active bitmap */ 455 siena_filter_spec_t *sft_spec; /* array of saved specs */ 456 } siena_filter_tbl_t; 457 458 typedef struct siena_filter_s { 459 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 460 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 461 } siena_filter_t; 462 463 #endif /* EFSYS_OPT_SIENA */ 464 465 typedef struct efx_filter_s { 466 #if EFSYS_OPT_SIENA 467 siena_filter_t *ef_siena_filter; 468 #endif /* EFSYS_OPT_SIENA */ 469 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 470 ef10_filter_table_t *ef_ef10_filter_table; 471 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 472 } efx_filter_t; 473 474 #if EFSYS_OPT_SIENA 475 476 LIBEFX_INTERNAL 477 extern void 478 siena_filter_tbl_clear( 479 __in efx_nic_t *enp, 480 __in siena_filter_tbl_id_t tbl); 481 482 #endif /* EFSYS_OPT_SIENA */ 483 484 #endif /* EFSYS_OPT_FILTER */ 485 486 #if EFSYS_OPT_MCDI 487 488 #define EFX_TUNNEL_MAXNENTRIES (16) 489 490 #if EFSYS_OPT_TUNNEL 491 492 /* State of a UDP tunnel table entry */ 493 typedef enum efx_tunnel_udp_entry_state_e { 494 EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */ 495 EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */ 496 EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */ 497 } efx_tunnel_udp_entry_state_t; 498 499 #if EFSYS_OPT_RIVERHEAD 500 typedef uint32_t efx_vnic_encap_rule_handle_t; 501 #endif /* EFSYS_OPT_RIVERHEAD */ 502 503 typedef struct efx_tunnel_udp_entry_s { 504 uint16_t etue_port; /* host/cpu-endian */ 505 uint16_t etue_protocol; 506 boolean_t etue_busy; 507 efx_tunnel_udp_entry_state_t etue_state; 508 #if EFSYS_OPT_RIVERHEAD 509 efx_vnic_encap_rule_handle_t etue_handle; 510 #endif /* EFSYS_OPT_RIVERHEAD */ 511 } efx_tunnel_udp_entry_t; 512 513 typedef struct efx_tunnel_cfg_s { 514 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 515 unsigned int etc_udp_entries_num; 516 } efx_tunnel_cfg_t; 517 518 #endif /* EFSYS_OPT_TUNNEL */ 519 520 typedef struct efx_mcdi_ops_s { 521 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 522 void (*emco_send_request)(efx_nic_t *, void *, size_t, 523 void *, size_t); 524 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 525 boolean_t (*emco_poll_response)(efx_nic_t *); 526 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 527 void (*emco_fini)(efx_nic_t *); 528 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 529 efx_mcdi_feature_id_t, boolean_t *); 530 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 531 uint32_t *); 532 } efx_mcdi_ops_t; 533 534 typedef struct efx_mcdi_s { 535 const efx_mcdi_ops_t *em_emcop; 536 const efx_mcdi_transport_t *em_emtp; 537 efx_mcdi_iface_t em_emip; 538 } efx_mcdi_t; 539 540 #endif /* EFSYS_OPT_MCDI */ 541 542 #if EFSYS_OPT_NVRAM 543 544 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 545 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 546 547 typedef struct efx_nvram_ops_s { 548 #if EFSYS_OPT_DIAG 549 efx_rc_t (*envo_test)(efx_nic_t *); 550 #endif /* EFSYS_OPT_DIAG */ 551 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 552 uint32_t *); 553 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, 554 efx_nvram_info_t *); 555 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 556 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 557 unsigned int, caddr_t, size_t); 558 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 559 unsigned int, caddr_t, size_t); 560 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 561 unsigned int, size_t); 562 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 563 unsigned int, caddr_t, size_t); 564 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 565 uint32_t *); 566 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 567 uint32_t *, uint16_t *); 568 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 569 uint16_t *); 570 efx_rc_t (*envo_buffer_validate)(uint32_t, 571 caddr_t, size_t); 572 } efx_nvram_ops_t; 573 #endif /* EFSYS_OPT_NVRAM */ 574 575 #if EFSYS_OPT_VPD 576 typedef struct efx_vpd_ops_s { 577 efx_rc_t (*evpdo_init)(efx_nic_t *); 578 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 579 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 580 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 581 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 582 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 583 efx_vpd_value_t *); 584 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 585 efx_vpd_value_t *); 586 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 587 efx_vpd_value_t *, unsigned int *); 588 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 589 void (*evpdo_fini)(efx_nic_t *); 590 } efx_vpd_ops_t; 591 #endif /* EFSYS_OPT_VPD */ 592 593 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 594 595 LIBEFX_INTERNAL 596 extern __checkReturn efx_rc_t 597 efx_mcdi_nvram_partitions( 598 __in efx_nic_t *enp, 599 __out_bcount(size) caddr_t data, 600 __in size_t size, 601 __out unsigned int *npartnp); 602 603 LIBEFX_INTERNAL 604 extern __checkReturn efx_rc_t 605 efx_mcdi_nvram_metadata( 606 __in efx_nic_t *enp, 607 __in uint32_t partn, 608 __out uint32_t *subtypep, 609 __out_ecount(4) uint16_t version[4], 610 __out_bcount_opt(size) char *descp, 611 __in size_t size); 612 613 LIBEFX_INTERNAL 614 extern __checkReturn efx_rc_t 615 efx_mcdi_nvram_info( 616 __in efx_nic_t *enp, 617 __in uint32_t partn, 618 __out efx_nvram_info_t *eni); 619 620 LIBEFX_INTERNAL 621 extern __checkReturn efx_rc_t 622 efx_mcdi_nvram_update_start( 623 __in efx_nic_t *enp, 624 __in uint32_t partn); 625 626 LIBEFX_INTERNAL 627 extern __checkReturn efx_rc_t 628 efx_mcdi_nvram_read( 629 __in efx_nic_t *enp, 630 __in uint32_t partn, 631 __in uint32_t offset, 632 __out_bcount(size) caddr_t data, 633 __in size_t size, 634 __in uint32_t mode); 635 636 LIBEFX_INTERNAL 637 extern __checkReturn efx_rc_t 638 efx_mcdi_nvram_erase( 639 __in efx_nic_t *enp, 640 __in uint32_t partn, 641 __in uint32_t offset, 642 __in size_t size); 643 644 LIBEFX_INTERNAL 645 extern __checkReturn efx_rc_t 646 efx_mcdi_nvram_write( 647 __in efx_nic_t *enp, 648 __in uint32_t partn, 649 __in uint32_t offset, 650 __in_bcount(size) caddr_t data, 651 __in size_t size); 652 653 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 654 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 655 656 LIBEFX_INTERNAL 657 extern __checkReturn efx_rc_t 658 efx_mcdi_nvram_update_finish( 659 __in efx_nic_t *enp, 660 __in uint32_t partn, 661 __in boolean_t reboot, 662 __in uint32_t flags, 663 __out_opt uint32_t *verify_resultp); 664 665 #if EFSYS_OPT_DIAG 666 667 LIBEFX_INTERNAL 668 extern __checkReturn efx_rc_t 669 efx_mcdi_nvram_test( 670 __in efx_nic_t *enp, 671 __in uint32_t partn); 672 673 #endif /* EFSYS_OPT_DIAG */ 674 675 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 676 677 #if EFSYS_OPT_LICENSING 678 679 typedef struct efx_lic_ops_s { 680 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 681 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 682 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 683 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 684 size_t *, uint8_t *); 685 efx_rc_t (*elo_find_start) 686 (efx_nic_t *, caddr_t, size_t, uint32_t *); 687 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 688 uint32_t, uint32_t *); 689 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 690 uint32_t, uint32_t *, uint32_t *); 691 boolean_t (*elo_validate_key)(efx_nic_t *, 692 caddr_t, uint32_t); 693 efx_rc_t (*elo_read_key)(efx_nic_t *, 694 caddr_t, size_t, uint32_t, uint32_t, 695 caddr_t, size_t, uint32_t *); 696 efx_rc_t (*elo_write_key)(efx_nic_t *, 697 caddr_t, size_t, uint32_t, 698 caddr_t, uint32_t, uint32_t *); 699 efx_rc_t (*elo_delete_key)(efx_nic_t *, 700 caddr_t, size_t, uint32_t, 701 uint32_t, uint32_t, uint32_t *); 702 efx_rc_t (*elo_create_partition)(efx_nic_t *, 703 caddr_t, size_t); 704 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 705 caddr_t, size_t); 706 } efx_lic_ops_t; 707 708 #endif 709 710 #if EFSYS_OPT_EVB 711 712 struct efx_vswitch_s { 713 efx_nic_t *ev_enp; 714 efx_vswitch_id_t ev_vswitch_id; 715 uint32_t ev_num_vports; 716 /* 717 * Vport configuration array: index 0 to store PF configuration 718 * and next ev_num_vports-1 entries hold VFs configuration. 719 */ 720 efx_vport_config_t *ev_evcp; 721 }; 722 723 typedef struct efx_evb_ops_s { 724 efx_rc_t (*eeo_init)(efx_nic_t *); 725 void (*eeo_fini)(efx_nic_t *); 726 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); 727 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); 728 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, 729 efx_vport_type_t, uint16_t, 730 boolean_t, efx_vport_id_t *); 731 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, 732 efx_vport_id_t); 733 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, 734 efx_vport_id_t, uint8_t *); 735 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, 736 efx_vport_id_t, uint8_t *); 737 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, 738 efx_vport_id_t); 739 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, 740 efx_vport_id_t); 741 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, 742 efx_vport_id_t, uint32_t); 743 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t, 744 efx_vport_id_t, 745 uint16_t *, uint8_t *, 746 boolean_t *); 747 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t, 748 efx_vport_id_t, efsys_mem_t *); 749 } efx_evb_ops_t; 750 751 LIBEFX_INTERNAL 752 extern __checkReturn boolean_t 753 efx_is_zero_eth_addr( 754 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); 755 756 #endif /* EFSYS_OPT_EVB */ 757 758 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 759 760 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF 761 762 763 typedef struct efx_proxy_ops_s { 764 efx_rc_t (*epo_init)(efx_nic_t *); 765 void (*epo_fini)(efx_nic_t *); 766 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *, 767 efsys_mem_t *, efsys_mem_t *, 768 uint32_t, uint32_t *, size_t); 769 efx_rc_t (*epo_disable)(efx_nic_t *); 770 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t, 771 uint32_t, uint32_t, uint32_t); 772 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t, 773 uint32_t, uint32_t); 774 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t, 775 uint32_t, uint32_t); 776 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *); 777 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t, 778 uint32_t, uint32_t *); 779 } efx_proxy_ops_t; 780 781 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 782 783 #define EFX_DRV_VER_MAX 20 784 785 typedef struct efx_drv_cfg_s { 786 uint32_t edc_min_vi_count; 787 uint32_t edc_max_vi_count; 788 789 uint32_t edc_max_piobuf_count; 790 uint32_t edc_pio_alloc_size; 791 } efx_drv_cfg_t; 792 793 struct efx_nic_s { 794 uint32_t en_magic; 795 efx_family_t en_family; 796 uint32_t en_features; 797 efsys_identifier_t *en_esip; 798 efsys_lock_t *en_eslp; 799 efsys_bar_t *en_esbp; 800 unsigned int en_mod_flags; 801 unsigned int en_reset_flags; 802 efx_nic_cfg_t en_nic_cfg; 803 efx_drv_cfg_t en_drv_cfg; 804 efx_port_t en_port; 805 efx_mon_t en_mon; 806 efx_intr_t en_intr; 807 uint32_t en_ev_qcount; 808 uint32_t en_rx_qcount; 809 uint32_t en_tx_qcount; 810 const efx_nic_ops_t *en_enop; 811 const efx_ev_ops_t *en_eevop; 812 const efx_tx_ops_t *en_etxop; 813 const efx_rx_ops_t *en_erxop; 814 efx_fw_variant_t efv; 815 char en_drv_version[EFX_DRV_VER_MAX]; 816 #if EFSYS_OPT_FILTER 817 efx_filter_t en_filter; 818 const efx_filter_ops_t *en_efop; 819 #endif /* EFSYS_OPT_FILTER */ 820 #if EFSYS_OPT_TUNNEL 821 efx_tunnel_cfg_t en_tunnel_cfg; 822 const efx_tunnel_ops_t *en_etop; 823 #endif /* EFSYS_OPT_TUNNEL */ 824 #if EFSYS_OPT_MCDI 825 efx_mcdi_t en_mcdi; 826 #endif /* EFSYS_OPT_MCDI */ 827 #if EFSYS_OPT_NVRAM 828 uint32_t en_nvram_partn_locked; 829 const efx_nvram_ops_t *en_envop; 830 #endif /* EFSYS_OPT_NVRAM */ 831 #if EFSYS_OPT_VPD 832 const efx_vpd_ops_t *en_evpdop; 833 #endif /* EFSYS_OPT_VPD */ 834 #if EFSYS_OPT_RX_SCALE 835 efx_rx_hash_support_t en_hash_support; 836 efx_rx_scale_context_type_t en_rss_context_type; 837 uint32_t en_rss_context; 838 #endif /* EFSYS_OPT_RX_SCALE */ 839 uint32_t en_vport_id; 840 #if EFSYS_OPT_LICENSING 841 const efx_lic_ops_t *en_elop; 842 boolean_t en_licensing_supported; 843 #endif 844 union { 845 #if EFSYS_OPT_SIENA 846 struct { 847 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 848 unsigned int enu_partn_mask; 849 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 850 #if EFSYS_OPT_VPD 851 caddr_t enu_svpd; 852 size_t enu_svpd_length; 853 #endif /* EFSYS_OPT_VPD */ 854 int enu_unused; 855 } siena; 856 #endif /* EFSYS_OPT_SIENA */ 857 int enu_unused; 858 } en_u; 859 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 860 union en_arch { 861 struct { 862 int ena_vi_base; 863 int ena_vi_count; 864 int ena_vi_shift; 865 uint32_t ena_fcw_base; 866 #if EFSYS_OPT_VPD 867 caddr_t ena_svpd; 868 size_t ena_svpd_length; 869 #endif /* EFSYS_OPT_VPD */ 870 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 871 uint32_t ena_piobuf_count; 872 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 873 uint32_t ena_pio_write_vi_base; 874 /* Memory BAR mapping regions */ 875 uint32_t ena_uc_mem_map_offset; 876 size_t ena_uc_mem_map_size; 877 uint32_t ena_wc_mem_map_offset; 878 size_t ena_wc_mem_map_size; 879 } ef10; 880 } en_arch; 881 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 882 #if EFSYS_OPT_EVB 883 const efx_evb_ops_t *en_eeop; 884 struct efx_vswitch_s *en_vswitchp; 885 #endif /* EFSYS_OPT_EVB */ 886 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 887 const efx_proxy_ops_t *en_epop; 888 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 889 }; 890 891 #define EFX_FAMILY_IS_EF10(_enp) \ 892 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ 893 (_enp)->en_family == EFX_FAMILY_MEDFORD || \ 894 (_enp)->en_family == EFX_FAMILY_HUNTINGTON) 895 896 #define EFX_FAMILY_IS_EF100(_enp) \ 897 ((_enp)->en_family == EFX_FAMILY_RIVERHEAD) 898 899 900 #define EFX_NIC_MAGIC 0x02121996 901 902 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 903 const efx_ev_callbacks_t *, void *); 904 905 #if EFSYS_OPT_EV_EXTENDED_WIDTH 906 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *, 907 const efx_ev_callbacks_t *, void *); 908 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */ 909 910 typedef struct efx_evq_rxq_state_s { 911 unsigned int eers_rx_read_ptr; 912 unsigned int eers_rx_mask; 913 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 914 unsigned int eers_rx_stream_npackets; 915 boolean_t eers_rx_packed_stream; 916 #endif 917 #if EFSYS_OPT_RX_PACKED_STREAM 918 unsigned int eers_rx_packed_stream_credits; 919 #endif 920 } efx_evq_rxq_state_t; 921 922 struct efx_evq_s { 923 uint32_t ee_magic; 924 uint32_t ee_flags; 925 efx_nic_t *ee_enp; 926 unsigned int ee_index; 927 unsigned int ee_mask; 928 efsys_mem_t *ee_esmp; 929 #if EFSYS_OPT_QSTATS 930 uint32_t ee_stat[EV_NQSTATS]; 931 #endif /* EFSYS_OPT_QSTATS */ 932 933 efx_ev_handler_t ee_rx; 934 efx_ev_handler_t ee_tx; 935 efx_ev_handler_t ee_driver; 936 efx_ev_handler_t ee_global; 937 efx_ev_handler_t ee_drv_gen; 938 #if EFSYS_OPT_MCDI 939 efx_ev_handler_t ee_mcdi; 940 #endif /* EFSYS_OPT_MCDI */ 941 942 #if EFSYS_OPT_DESC_PROXY 943 efx_ev_ew_handler_t ee_ew_txq_desc; 944 efx_ev_ew_handler_t ee_ew_virtq_desc; 945 #endif /* EFSYS_OPT_DESC_PROXY */ 946 947 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 948 }; 949 950 #define EFX_EVQ_MAGIC 0x08081997 951 952 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 953 954 #if EFSYS_OPT_QSTATS 955 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 956 do { \ 957 (_eep)->ee_stat[_stat]++; \ 958 _NOTE(CONSTANTCONDITION) \ 959 } while (B_FALSE) 960 #else 961 #define EFX_EV_QSTAT_INCR(_eep, _stat) 962 #endif 963 964 struct efx_rxq_s { 965 uint32_t er_magic; 966 efx_nic_t *er_enp; 967 efx_evq_t *er_eep; 968 unsigned int er_index; 969 unsigned int er_label; 970 unsigned int er_mask; 971 size_t er_buf_size; 972 efsys_mem_t *er_esmp; 973 efx_evq_rxq_state_t *er_ev_qstate; 974 efx_rx_prefix_layout_t er_prefix_layout; 975 }; 976 977 #define EFX_RXQ_MAGIC 0x15022005 978 979 struct efx_txq_s { 980 uint32_t et_magic; 981 efx_nic_t *et_enp; 982 unsigned int et_index; 983 unsigned int et_mask; 984 efsys_mem_t *et_esmp; 985 #if EFSYS_OPT_HUNTINGTON 986 uint32_t et_pio_bufnum; 987 uint32_t et_pio_blknum; 988 uint32_t et_pio_write_offset; 989 uint32_t et_pio_offset; 990 size_t et_pio_size; 991 #endif 992 #if EFSYS_OPT_QSTATS 993 uint32_t et_stat[TX_NQSTATS]; 994 #endif /* EFSYS_OPT_QSTATS */ 995 }; 996 997 #define EFX_TXQ_MAGIC 0x05092005 998 999 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 1000 do { \ 1001 (_dst)[0] = (_src)[0]; \ 1002 (_dst)[1] = (_src)[1]; \ 1003 (_dst)[2] = (_src)[2]; \ 1004 (_dst)[3] = (_src)[3]; \ 1005 (_dst)[4] = (_src)[4]; \ 1006 (_dst)[5] = (_src)[5]; \ 1007 _NOTE(CONSTANTCONDITION) \ 1008 } while (B_FALSE) 1009 1010 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 1011 do { \ 1012 uint16_t *_d = (uint16_t *)(_dst); \ 1013 _d[0] = 0xffff; \ 1014 _d[1] = 0xffff; \ 1015 _d[2] = 0xffff; \ 1016 _NOTE(CONSTANTCONDITION) \ 1017 } while (B_FALSE) 1018 1019 #if EFSYS_OPT_CHECK_REG 1020 #define EFX_CHECK_REG(_enp, _reg) \ 1021 do { \ 1022 const char *name = #_reg; \ 1023 char min = name[4]; \ 1024 char max = name[5]; \ 1025 char rev; \ 1026 \ 1027 switch ((_enp)->en_family) { \ 1028 case EFX_FAMILY_SIENA: \ 1029 rev = 'C'; \ 1030 break; \ 1031 \ 1032 case EFX_FAMILY_HUNTINGTON: \ 1033 rev = 'D'; \ 1034 break; \ 1035 \ 1036 case EFX_FAMILY_MEDFORD: \ 1037 rev = 'E'; \ 1038 break; \ 1039 \ 1040 case EFX_FAMILY_MEDFORD2: \ 1041 rev = 'F'; \ 1042 break; \ 1043 \ 1044 case EFX_FAMILY_RIVERHEAD: \ 1045 rev = 'G'; \ 1046 break; \ 1047 \ 1048 default: \ 1049 rev = '?'; \ 1050 break; \ 1051 } \ 1052 \ 1053 EFSYS_ASSERT3S(rev, >=, min); \ 1054 EFSYS_ASSERT3S(rev, <=, max); \ 1055 \ 1056 _NOTE(CONSTANTCONDITION) \ 1057 } while (B_FALSE) 1058 #else 1059 #define EFX_CHECK_REG(_enp, _reg) do { \ 1060 _NOTE(CONSTANTCONDITION) \ 1061 } while (B_FALSE) 1062 #endif 1063 1064 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 1065 do { \ 1066 EFX_CHECK_REG((_enp), (_reg)); \ 1067 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 1068 (_edp), (_lock)); \ 1069 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 1070 uint32_t, _reg ## _OFST, \ 1071 uint32_t, (_edp)->ed_u32[0]); \ 1072 _NOTE(CONSTANTCONDITION) \ 1073 } while (B_FALSE) 1074 1075 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 1076 do { \ 1077 EFX_CHECK_REG((_enp), (_reg)); \ 1078 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 1079 uint32_t, _reg ## _OFST, \ 1080 uint32_t, (_edp)->ed_u32[0]); \ 1081 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 1082 (_edp), (_lock)); \ 1083 _NOTE(CONSTANTCONDITION) \ 1084 } while (B_FALSE) 1085 1086 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 1087 do { \ 1088 EFX_CHECK_REG((_enp), (_reg)); \ 1089 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 1090 (_eqp)); \ 1091 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 1092 uint32_t, _reg ## _OFST, \ 1093 uint32_t, (_eqp)->eq_u32[1], \ 1094 uint32_t, (_eqp)->eq_u32[0]); \ 1095 _NOTE(CONSTANTCONDITION) \ 1096 } while (B_FALSE) 1097 1098 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 1099 do { \ 1100 EFX_CHECK_REG((_enp), (_reg)); \ 1101 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 1102 uint32_t, _reg ## _OFST, \ 1103 uint32_t, (_eqp)->eq_u32[1], \ 1104 uint32_t, (_eqp)->eq_u32[0]); \ 1105 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 1106 (_eqp)); \ 1107 _NOTE(CONSTANTCONDITION) \ 1108 } while (B_FALSE) 1109 1110 #define EFX_BAR_READO(_enp, _reg, _eop) \ 1111 do { \ 1112 EFX_CHECK_REG((_enp), (_reg)); \ 1113 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 1114 (_eop), B_TRUE); \ 1115 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 1116 uint32_t, _reg ## _OFST, \ 1117 uint32_t, (_eop)->eo_u32[3], \ 1118 uint32_t, (_eop)->eo_u32[2], \ 1119 uint32_t, (_eop)->eo_u32[1], \ 1120 uint32_t, (_eop)->eo_u32[0]); \ 1121 _NOTE(CONSTANTCONDITION) \ 1122 } while (B_FALSE) 1123 1124 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 1125 do { \ 1126 EFX_CHECK_REG((_enp), (_reg)); \ 1127 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 1128 uint32_t, _reg ## _OFST, \ 1129 uint32_t, (_eop)->eo_u32[3], \ 1130 uint32_t, (_eop)->eo_u32[2], \ 1131 uint32_t, (_eop)->eo_u32[1], \ 1132 uint32_t, (_eop)->eo_u32[0]); \ 1133 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 1134 (_eop), B_TRUE); \ 1135 _NOTE(CONSTANTCONDITION) \ 1136 } while (B_FALSE) 1137 1138 /* 1139 * Accessors for memory BAR non-VI tables. 1140 * 1141 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 1142 * to ensure the correct runtime VI window size is used on Medford2. 1143 * 1144 * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control 1145 * window registers, to ensure the correct starting offset is used. 1146 * 1147 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 1148 */ 1149 1150 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 1151 do { \ 1152 EFX_CHECK_REG((_enp), (_reg)); \ 1153 EFSYS_BAR_READD((_enp)->en_esbp, \ 1154 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1155 (_edp), (_lock)); \ 1156 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 1157 uint32_t, (_index), \ 1158 uint32_t, _reg ## _OFST, \ 1159 uint32_t, (_edp)->ed_u32[0]); \ 1160 _NOTE(CONSTANTCONDITION) \ 1161 } while (B_FALSE) 1162 1163 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1164 do { \ 1165 EFX_CHECK_REG((_enp), (_reg)); \ 1166 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1167 uint32_t, (_index), \ 1168 uint32_t, _reg ## _OFST, \ 1169 uint32_t, (_edp)->ed_u32[0]); \ 1170 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1171 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1172 (_edp), (_lock)); \ 1173 _NOTE(CONSTANTCONDITION) \ 1174 } while (B_FALSE) 1175 1176 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1177 do { \ 1178 EFX_CHECK_REG((_enp), (_reg)); \ 1179 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1180 uint32_t, (_index), \ 1181 uint32_t, _reg ## _OFST, \ 1182 uint32_t, (_edp)->ed_u32[0]); \ 1183 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1184 (_reg ## _OFST + \ 1185 (3 * sizeof (efx_dword_t)) + \ 1186 ((_index) * _reg ## _STEP)), \ 1187 (_edp), (_lock)); \ 1188 _NOTE(CONSTANTCONDITION) \ 1189 } while (B_FALSE) 1190 1191 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1192 do { \ 1193 EFX_CHECK_REG((_enp), (_reg)); \ 1194 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1195 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1196 (_eqp)); \ 1197 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1198 uint32_t, (_index), \ 1199 uint32_t, _reg ## _OFST, \ 1200 uint32_t, (_eqp)->eq_u32[1], \ 1201 uint32_t, (_eqp)->eq_u32[0]); \ 1202 _NOTE(CONSTANTCONDITION) \ 1203 } while (B_FALSE) 1204 1205 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1206 do { \ 1207 EFX_CHECK_REG((_enp), (_reg)); \ 1208 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1209 uint32_t, (_index), \ 1210 uint32_t, _reg ## _OFST, \ 1211 uint32_t, (_eqp)->eq_u32[1], \ 1212 uint32_t, (_eqp)->eq_u32[0]); \ 1213 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1214 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1215 (_eqp)); \ 1216 _NOTE(CONSTANTCONDITION) \ 1217 } while (B_FALSE) 1218 1219 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1220 do { \ 1221 EFX_CHECK_REG((_enp), (_reg)); \ 1222 EFSYS_BAR_READO((_enp)->en_esbp, \ 1223 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1224 (_eop), (_lock)); \ 1225 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1226 uint32_t, (_index), \ 1227 uint32_t, _reg ## _OFST, \ 1228 uint32_t, (_eop)->eo_u32[3], \ 1229 uint32_t, (_eop)->eo_u32[2], \ 1230 uint32_t, (_eop)->eo_u32[1], \ 1231 uint32_t, (_eop)->eo_u32[0]); \ 1232 _NOTE(CONSTANTCONDITION) \ 1233 } while (B_FALSE) 1234 1235 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1236 do { \ 1237 EFX_CHECK_REG((_enp), (_reg)); \ 1238 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1239 uint32_t, (_index), \ 1240 uint32_t, _reg ## _OFST, \ 1241 uint32_t, (_eop)->eo_u32[3], \ 1242 uint32_t, (_eop)->eo_u32[2], \ 1243 uint32_t, (_eop)->eo_u32[1], \ 1244 uint32_t, (_eop)->eo_u32[0]); \ 1245 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1246 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1247 (_eop), (_lock)); \ 1248 _NOTE(CONSTANTCONDITION) \ 1249 } while (B_FALSE) 1250 1251 /* 1252 * Accessors for memory BAR function control window registers. 1253 * 1254 * The function control window is located at an offset which can be 1255 * non-zero in case of Riverhead. 1256 */ 1257 1258 #if EFSYS_OPT_RIVERHEAD 1259 1260 #define EFX_BAR_FCW_READD(_enp, _reg, _edp) \ 1261 do { \ 1262 EFX_CHECK_REG((_enp), (_reg)); \ 1263 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST + \ 1264 (_enp)->en_arch.ef10.ena_fcw_base, \ 1265 (_edp), B_FALSE); \ 1266 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg, \ 1267 uint32_t, _reg ## _OFST, \ 1268 uint32_t, (_edp)->ed_u32[0]); \ 1269 _NOTE(CONSTANTCONDITION) \ 1270 } while (B_FALSE) 1271 1272 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp) \ 1273 do { \ 1274 EFX_CHECK_REG((_enp), (_reg)); \ 1275 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg, \ 1276 uint32_t, _reg ## _OFST, \ 1277 uint32_t, (_edp)->ed_u32[0]); \ 1278 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST + \ 1279 (_enp)->en_arch.ef10.ena_fcw_base, \ 1280 (_edp), B_FALSE); \ 1281 _NOTE(CONSTANTCONDITION) \ 1282 } while (B_FALSE) 1283 1284 #endif /* EFSYS_OPT_RIVERHEAD */ 1285 1286 /* 1287 * Accessors for memory BAR per-VI registers. 1288 * 1289 * The VI window size is 8KB for Medford and all earlier controllers. 1290 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1291 */ 1292 1293 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1294 do { \ 1295 EFX_CHECK_REG((_enp), (_reg)); \ 1296 EFSYS_BAR_READD((_enp)->en_esbp, \ 1297 ((_reg ## _OFST) + \ 1298 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1299 (_edp), (_lock)); \ 1300 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1301 uint32_t, (_index), \ 1302 uint32_t, _reg ## _OFST, \ 1303 uint32_t, (_edp)->ed_u32[0]); \ 1304 _NOTE(CONSTANTCONDITION) \ 1305 } while (B_FALSE) 1306 1307 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1308 do { \ 1309 EFX_CHECK_REG((_enp), (_reg)); \ 1310 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1311 uint32_t, (_index), \ 1312 uint32_t, _reg ## _OFST, \ 1313 uint32_t, (_edp)->ed_u32[0]); \ 1314 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1315 ((_reg ## _OFST) + \ 1316 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1317 (_edp), (_lock)); \ 1318 _NOTE(CONSTANTCONDITION) \ 1319 } while (B_FALSE) 1320 1321 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1322 do { \ 1323 EFX_CHECK_REG((_enp), (_reg)); \ 1324 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1325 uint32_t, (_index), \ 1326 uint32_t, _reg ## _OFST, \ 1327 uint32_t, (_edp)->ed_u32[0]); \ 1328 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1329 ((_reg ## _OFST) + \ 1330 (2 * sizeof (efx_dword_t)) + \ 1331 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1332 (_edp), (_lock)); \ 1333 _NOTE(CONSTANTCONDITION) \ 1334 } while (B_FALSE) 1335 1336 /* 1337 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1338 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1339 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1340 * the need for locking in the host, and are the only ones known to be safe to 1341 * use 128-bites write with. 1342 */ 1343 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1344 do { \ 1345 EFX_CHECK_REG((_enp), (_reg)); \ 1346 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1347 const char *, #_reg, \ 1348 uint32_t, (_index), \ 1349 uint32_t, _reg ## _OFST, \ 1350 uint32_t, (_eop)->eo_u32[3], \ 1351 uint32_t, (_eop)->eo_u32[2], \ 1352 uint32_t, (_eop)->eo_u32[1], \ 1353 uint32_t, (_eop)->eo_u32[0]); \ 1354 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1355 (_reg ## _OFST + \ 1356 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1357 (_eop)); \ 1358 _NOTE(CONSTANTCONDITION) \ 1359 } while (B_FALSE) 1360 1361 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \ 1362 _wptr, _owptr) \ 1363 do { \ 1364 unsigned int _new = (_wptr); \ 1365 unsigned int _old = (_owptr); \ 1366 \ 1367 if ((_new) >= (_old)) \ 1368 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1369 (_old) * (_desc_size), \ 1370 ((_new) - (_old)) * (_desc_size)); \ 1371 else \ 1372 /* \ 1373 * It is cheaper to sync entire map than sync \ 1374 * two parts especially when offset/size are \ 1375 * ignored and entire map is synced in any case.\ 1376 */ \ 1377 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1378 0, \ 1379 (_entries) * (_desc_size)); \ 1380 _NOTE(CONSTANTCONDITION) \ 1381 } while (B_FALSE) 1382 1383 LIBEFX_INTERNAL 1384 extern __checkReturn efx_rc_t 1385 efx_mac_select( 1386 __in efx_nic_t *enp); 1387 1388 LIBEFX_INTERNAL 1389 extern void 1390 efx_mac_multicast_hash_compute( 1391 __in_ecount(6*count) uint8_t const *addrs, 1392 __in int count, 1393 __out efx_oword_t *hash_low, 1394 __out efx_oword_t *hash_high); 1395 1396 LIBEFX_INTERNAL 1397 extern __checkReturn efx_rc_t 1398 efx_phy_probe( 1399 __in efx_nic_t *enp); 1400 1401 LIBEFX_INTERNAL 1402 extern void 1403 efx_phy_unprobe( 1404 __in efx_nic_t *enp); 1405 1406 #if EFSYS_OPT_VPD 1407 1408 /* VPD utility functions */ 1409 1410 LIBEFX_INTERNAL 1411 extern __checkReturn efx_rc_t 1412 efx_vpd_hunk_length( 1413 __in_bcount(size) caddr_t data, 1414 __in size_t size, 1415 __out size_t *lengthp); 1416 1417 LIBEFX_INTERNAL 1418 extern __checkReturn efx_rc_t 1419 efx_vpd_hunk_verify( 1420 __in_bcount(size) caddr_t data, 1421 __in size_t size, 1422 __out_opt boolean_t *cksummedp); 1423 1424 LIBEFX_INTERNAL 1425 extern __checkReturn efx_rc_t 1426 efx_vpd_hunk_reinit( 1427 __in_bcount(size) caddr_t data, 1428 __in size_t size, 1429 __in boolean_t wantpid); 1430 1431 LIBEFX_INTERNAL 1432 extern __checkReturn efx_rc_t 1433 efx_vpd_hunk_get( 1434 __in_bcount(size) caddr_t data, 1435 __in size_t size, 1436 __in efx_vpd_tag_t tag, 1437 __in efx_vpd_keyword_t keyword, 1438 __out unsigned int *payloadp, 1439 __out uint8_t *paylenp); 1440 1441 LIBEFX_INTERNAL 1442 extern __checkReturn efx_rc_t 1443 efx_vpd_hunk_next( 1444 __in_bcount(size) caddr_t data, 1445 __in size_t size, 1446 __out efx_vpd_tag_t *tagp, 1447 __out efx_vpd_keyword_t *keyword, 1448 __out_opt unsigned int *payloadp, 1449 __out_opt uint8_t *paylenp, 1450 __inout unsigned int *contp); 1451 1452 LIBEFX_INTERNAL 1453 extern __checkReturn efx_rc_t 1454 efx_vpd_hunk_set( 1455 __in_bcount(size) caddr_t data, 1456 __in size_t size, 1457 __in efx_vpd_value_t *evvp); 1458 1459 #endif /* EFSYS_OPT_VPD */ 1460 1461 #if EFSYS_OPT_MCDI 1462 1463 LIBEFX_INTERNAL 1464 extern __checkReturn efx_rc_t 1465 efx_mcdi_set_workaround( 1466 __in efx_nic_t *enp, 1467 __in uint32_t type, 1468 __in boolean_t enabled, 1469 __out_opt uint32_t *flagsp); 1470 1471 LIBEFX_INTERNAL 1472 extern __checkReturn efx_rc_t 1473 efx_mcdi_get_workarounds( 1474 __in efx_nic_t *enp, 1475 __out_opt uint32_t *implementedp, 1476 __out_opt uint32_t *enabledp); 1477 1478 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1479 1480 LIBEFX_INTERNAL 1481 extern __checkReturn efx_rc_t 1482 efx_mcdi_init_evq( 1483 __in efx_nic_t *enp, 1484 __in unsigned int instance, 1485 __in efsys_mem_t *esmp, 1486 __in size_t nevs, 1487 __in uint32_t irq, 1488 __in uint32_t us, 1489 __in uint32_t flags, 1490 __in boolean_t low_latency); 1491 1492 LIBEFX_INTERNAL 1493 extern __checkReturn efx_rc_t 1494 efx_mcdi_fini_evq( 1495 __in efx_nic_t *enp, 1496 __in uint32_t instance); 1497 1498 typedef struct efx_mcdi_init_rxq_params_s { 1499 boolean_t disable_scatter; 1500 boolean_t want_inner_classes; 1501 uint32_t buf_size; 1502 uint32_t ps_buf_size; 1503 uint32_t es_bufs_per_desc; 1504 uint32_t es_max_dma_len; 1505 uint32_t es_buf_stride; 1506 uint32_t hol_block_timeout; 1507 uint32_t prefix_id; 1508 } efx_mcdi_init_rxq_params_t; 1509 1510 LIBEFX_INTERNAL 1511 extern __checkReturn efx_rc_t 1512 efx_mcdi_init_rxq( 1513 __in efx_nic_t *enp, 1514 __in uint32_t ndescs, 1515 __in efx_evq_t *eep, 1516 __in uint32_t label, 1517 __in uint32_t instance, 1518 __in efsys_mem_t *esmp, 1519 __in const efx_mcdi_init_rxq_params_t *params); 1520 1521 LIBEFX_INTERNAL 1522 extern __checkReturn efx_rc_t 1523 efx_mcdi_fini_rxq( 1524 __in efx_nic_t *enp, 1525 __in uint32_t instance); 1526 1527 LIBEFX_INTERNAL 1528 extern __checkReturn efx_rc_t 1529 efx_mcdi_init_txq( 1530 __in efx_nic_t *enp, 1531 __in uint32_t ndescs, 1532 __in uint32_t target_evq, 1533 __in uint32_t label, 1534 __in uint32_t instance, 1535 __in uint16_t flags, 1536 __in efsys_mem_t *esmp); 1537 1538 LIBEFX_INTERNAL 1539 extern __checkReturn efx_rc_t 1540 efx_mcdi_fini_txq( 1541 __in efx_nic_t *enp, 1542 __in uint32_t instance); 1543 1544 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1545 1546 #endif /* EFSYS_OPT_MCDI */ 1547 1548 #if EFSYS_OPT_MAC_STATS 1549 1550 /* 1551 * Closed range of stats (i.e. the first and the last are included). 1552 * The last must be greater or equal (if the range is one item only) to 1553 * the first. 1554 */ 1555 struct efx_mac_stats_range { 1556 efx_mac_stat_t first; 1557 efx_mac_stat_t last; 1558 }; 1559 1560 typedef enum efx_stats_action_e { 1561 EFX_STATS_CLEAR, 1562 EFX_STATS_UPLOAD, 1563 EFX_STATS_ENABLE_NOEVENTS, 1564 EFX_STATS_ENABLE_EVENTS, 1565 EFX_STATS_DISABLE, 1566 } efx_stats_action_t; 1567 1568 LIBEFX_INTERNAL 1569 extern efx_rc_t 1570 efx_mac_stats_mask_add_ranges( 1571 __inout_bcount(mask_size) uint32_t *maskp, 1572 __in size_t mask_size, 1573 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1574 __in unsigned int rng_count); 1575 1576 LIBEFX_INTERNAL 1577 extern __checkReturn efx_rc_t 1578 efx_mcdi_mac_stats( 1579 __in efx_nic_t *enp, 1580 __in uint32_t vport_id, 1581 __in_opt efsys_mem_t *esmp, 1582 __in efx_stats_action_t action, 1583 __in uint16_t period_ms); 1584 1585 #endif /* EFSYS_OPT_MAC_STATS */ 1586 1587 #if EFSYS_OPT_PCI 1588 1589 /* 1590 * Find the next extended capability in a PCI device's config space 1591 * with specified capability id. 1592 * Passing 0 offset makes the function search from the start. 1593 * If search succeeds, found capability is in modified offset. 1594 * 1595 * Returns ENOENT if a capability is not found. 1596 */ 1597 LIBEFX_INTERNAL 1598 extern __checkReturn efx_rc_t 1599 efx_pci_config_find_next_ext_cap( 1600 __in efsys_pci_config_t *espcp, 1601 __in const efx_pci_ops_t *epop, 1602 __in uint16_t cap_id, 1603 __inout size_t *offsetp); 1604 1605 /* 1606 * Get the next extended capability in a PCI device's config space. 1607 * Passing 0 offset makes the function get the first capability. 1608 * If search succeeds, the capability is in modified offset. 1609 * 1610 * Returns ENOENT if there is no next capability. 1611 */ 1612 LIBEFX_INTERNAL 1613 extern __checkReturn efx_rc_t 1614 efx_pci_config_next_ext_cap( 1615 __in efsys_pci_config_t *espcp, 1616 __in const efx_pci_ops_t *epop, 1617 __inout size_t *offsetp); 1618 1619 /* 1620 * Find the next Xilinx capabilities table location by searching 1621 * PCI extended capabilities. 1622 * 1623 * Returns ENOENT if a table location is not found. 1624 */ 1625 LIBEFX_INTERNAL 1626 extern __checkReturn efx_rc_t 1627 efx_pci_find_next_xilinx_cap_table( 1628 __in efsys_pci_config_t *espcp, 1629 __in const efx_pci_ops_t *epop, 1630 __inout size_t *pci_cap_offsetp, 1631 __out unsigned int *xilinx_tbl_barp, 1632 __out efsys_dma_addr_t *xilinx_tbl_offsetp); 1633 1634 /* 1635 * Read a Xilinx extended PCI capability that gives the location 1636 * of a Xilinx capabilities table. 1637 * 1638 * Returns ENOENT if the extended PCI capability does not contain 1639 * Xilinx capabilities table locator. 1640 */ 1641 LIBEFX_INTERNAL 1642 extern __checkReturn efx_rc_t 1643 efx_pci_read_ext_cap_xilinx_table( 1644 __in efsys_pci_config_t *espcp, 1645 __in const efx_pci_ops_t *epop, 1646 __in size_t cap_offset, 1647 __out unsigned int *barp, 1648 __out efsys_dma_addr_t *offsetp); 1649 1650 /* 1651 * Find a capability with specified format_id in a Xilinx capabilities table. 1652 * Searching is started from provided offset, taking skip_first into account. 1653 * If search succeeds, found capability is in modified offset. 1654 * 1655 * Returns ENOENT if an entry with specified format id is not found. 1656 */ 1657 LIBEFX_INTERNAL 1658 extern __checkReturn efx_rc_t 1659 efx_pci_xilinx_cap_tbl_find( 1660 __in efsys_bar_t *esbp, 1661 __in uint32_t format_id, 1662 __in boolean_t skip_first, 1663 __inout efsys_dma_addr_t *entry_offsetp); 1664 1665 #endif /* EFSYS_OPT_PCI */ 1666 1667 #ifdef __cplusplus 1668 } 1669 #endif 1670 1671 #endif /* _SYS_EFX_IMPL_H */ 1672