1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_IMPL_H 8 #define _SYS_EFX_IMPL_H 9 10 #include "efx.h" 11 #include "efx_regs.h" 12 #include "efx_regs_ef10.h" 13 #include "efx_regs_ef100.h" 14 #if EFSYS_OPT_MCDI 15 #include "efx_mcdi.h" 16 #endif /* EFSYS_OPT_MCDI */ 17 18 /* FIXME: Add definition for driver generated software events */ 19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 21 #endif 22 23 24 #if EFSYS_OPT_SIENA 25 #include "siena_impl.h" 26 #endif /* EFSYS_OPT_SIENA */ 27 28 #if EFSYS_OPT_HUNTINGTON 29 #include "hunt_impl.h" 30 #endif /* EFSYS_OPT_HUNTINGTON */ 31 32 #if EFSYS_OPT_MEDFORD 33 #include "medford_impl.h" 34 #endif /* EFSYS_OPT_MEDFORD */ 35 36 #if EFSYS_OPT_MEDFORD2 37 #include "medford2_impl.h" 38 #endif /* EFSYS_OPT_MEDFORD2 */ 39 40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 41 #include "ef10_impl.h" 42 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 43 44 #if EFSYS_OPT_RIVERHEAD 45 #include "rhead_impl.h" 46 #endif /* EFSYS_OPT_RIVERHEAD */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #define EFX_MOD_MCDI 0x00000001 53 #define EFX_MOD_PROBE 0x00000002 54 #define EFX_MOD_NVRAM 0x00000004 55 #define EFX_MOD_VPD 0x00000008 56 #define EFX_MOD_NIC 0x00000010 57 #define EFX_MOD_INTR 0x00000020 58 #define EFX_MOD_EV 0x00000040 59 #define EFX_MOD_RX 0x00000080 60 #define EFX_MOD_TX 0x00000100 61 #define EFX_MOD_PORT 0x00000200 62 #define EFX_MOD_MON 0x00000400 63 #define EFX_MOD_FILTER 0x00001000 64 #define EFX_MOD_LIC 0x00002000 65 #define EFX_MOD_TUNNEL 0x00004000 66 #define EFX_MOD_EVB 0x00008000 67 #define EFX_MOD_PROXY 0x00010000 68 #define EFX_MOD_VIRTIO 0x00020000 69 70 #define EFX_RESET_PHY 0x00000001 71 #define EFX_RESET_RXQ_ERR 0x00000002 72 #define EFX_RESET_TXQ_ERR 0x00000004 73 #define EFX_RESET_HW_UNAVAIL 0x00000008 74 75 typedef enum efx_mac_type_e { 76 EFX_MAC_INVALID = 0, 77 EFX_MAC_SIENA, 78 EFX_MAC_HUNTINGTON, 79 EFX_MAC_MEDFORD, 80 EFX_MAC_MEDFORD2, 81 EFX_MAC_RIVERHEAD, 82 EFX_MAC_NTYPES 83 } efx_mac_type_t; 84 85 typedef struct efx_ev_ops_s { 86 efx_rc_t (*eevo_init)(efx_nic_t *); 87 void (*eevo_fini)(efx_nic_t *); 88 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 89 efsys_mem_t *, size_t, uint32_t, 90 uint32_t, uint32_t, uint32_t, 91 efx_evq_t *); 92 void (*eevo_qdestroy)(efx_evq_t *); 93 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 94 void (*eevo_qpost)(efx_evq_t *, uint16_t); 95 void (*eevo_qpoll)(efx_evq_t *, unsigned int *, 96 const efx_ev_callbacks_t *, void *); 97 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 98 #if EFSYS_OPT_QSTATS 99 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 100 #endif 101 } efx_ev_ops_t; 102 103 typedef struct efx_tx_ops_s { 104 efx_rc_t (*etxo_init)(efx_nic_t *); 105 void (*etxo_fini)(efx_nic_t *); 106 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 107 unsigned int, unsigned int, 108 efsys_mem_t *, size_t, 109 uint32_t, uint16_t, 110 efx_evq_t *, efx_txq_t *, 111 unsigned int *); 112 void (*etxo_qdestroy)(efx_txq_t *); 113 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 114 unsigned int, unsigned int, 115 unsigned int *); 116 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 117 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 118 efx_rc_t (*etxo_qflush)(efx_txq_t *); 119 void (*etxo_qenable)(efx_txq_t *); 120 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 121 void (*etxo_qpio_disable)(efx_txq_t *); 122 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 123 size_t); 124 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 125 unsigned int *); 126 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 127 unsigned int, unsigned int, 128 unsigned int *); 129 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 130 size_t, boolean_t, 131 efx_desc_t *); 132 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 133 uint32_t, uint8_t, 134 efx_desc_t *); 135 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 136 uint16_t, uint32_t, uint16_t, 137 efx_desc_t *, int); 138 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 139 efx_desc_t *); 140 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 141 efx_desc_t *); 142 #if EFSYS_OPT_QSTATS 143 void (*etxo_qstats_update)(efx_txq_t *, 144 efsys_stat_t *); 145 #endif 146 } efx_tx_ops_t; 147 148 typedef union efx_rxq_type_data_u { 149 struct { 150 size_t ed_buf_size; 151 } ertd_default; 152 #if EFSYS_OPT_RX_PACKED_STREAM 153 struct { 154 uint32_t eps_buf_size; 155 } ertd_packed_stream; 156 #endif 157 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 158 struct { 159 uint32_t eessb_bufs_per_desc; 160 uint32_t eessb_max_dma_len; 161 uint32_t eessb_buf_stride; 162 uint32_t eessb_hol_block_timeout; 163 } ertd_es_super_buffer; 164 #endif 165 } efx_rxq_type_data_t; 166 167 typedef struct efx_rx_ops_s { 168 efx_rc_t (*erxo_init)(efx_nic_t *); 169 void (*erxo_fini)(efx_nic_t *); 170 #if EFSYS_OPT_RX_SCATTER 171 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 172 #endif 173 #if EFSYS_OPT_RX_SCALE 174 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 175 efx_rx_scale_context_type_t, 176 uint32_t, uint32_t, 177 uint32_t *); 178 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 179 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 180 efx_rx_hash_alg_t, 181 efx_rx_hash_type_t, boolean_t); 182 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 183 uint8_t *, size_t); 184 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 185 unsigned int *, size_t); 186 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 187 uint8_t *); 188 #endif /* EFSYS_OPT_RX_SCALE */ 189 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 190 uint16_t *); 191 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 192 unsigned int, unsigned int, 193 unsigned int); 194 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 195 #if EFSYS_OPT_RX_PACKED_STREAM 196 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 197 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 198 uint32_t, uint32_t, 199 uint16_t *, uint32_t *, uint32_t *); 200 #endif 201 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 202 void (*erxo_qenable)(efx_rxq_t *); 203 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 204 unsigned int, efx_rxq_type_t, 205 const efx_rxq_type_data_t *, 206 efsys_mem_t *, size_t, uint32_t, 207 unsigned int, 208 efx_evq_t *, efx_rxq_t *); 209 void (*erxo_qdestroy)(efx_rxq_t *); 210 } efx_rx_ops_t; 211 212 typedef struct efx_mac_ops_s { 213 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 214 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 215 efx_rc_t (*emo_addr_set)(efx_nic_t *); 216 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 217 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 218 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 219 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 220 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 221 efx_rxq_t *, boolean_t); 222 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 223 #if EFSYS_OPT_LOOPBACK 224 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 225 efx_loopback_type_t); 226 #endif /* EFSYS_OPT_LOOPBACK */ 227 #if EFSYS_OPT_MAC_STATS 228 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 229 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 230 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 231 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 232 uint16_t, boolean_t); 233 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 234 efsys_stat_t *, uint32_t *); 235 #endif /* EFSYS_OPT_MAC_STATS */ 236 } efx_mac_ops_t; 237 238 typedef struct efx_phy_ops_s { 239 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 240 efx_rc_t (*epo_reset)(efx_nic_t *); 241 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 242 efx_rc_t (*epo_verify)(efx_nic_t *); 243 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 244 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 245 #if EFSYS_OPT_PHY_STATS 246 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 247 uint32_t *); 248 #endif /* EFSYS_OPT_PHY_STATS */ 249 #if EFSYS_OPT_BIST 250 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 251 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 252 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 253 efx_bist_result_t *, uint32_t *, 254 unsigned long *, size_t); 255 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 256 #endif /* EFSYS_OPT_BIST */ 257 } efx_phy_ops_t; 258 259 #if EFSYS_OPT_FILTER 260 261 /* 262 * Policy for replacing existing filter when inserting a new one. 263 * Note that all policies allow for storing the new lower priority 264 * filters as overridden by existing higher priority ones. It is needed 265 * to restore the lower priority filters on higher priority ones removal. 266 */ 267 typedef enum efx_filter_replacement_policy_e { 268 /* Cannot replace existing filter */ 269 EFX_FILTER_REPLACEMENT_NEVER, 270 /* Higher priority filters can replace lower priotiry ones */ 271 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY, 272 /* 273 * Higher priority filters can replace lower priority ones and 274 * equal priority filters can replace each other. 275 */ 276 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY, 277 } efx_filter_replacement_policy_t; 278 279 typedef struct efx_filter_ops_s { 280 efx_rc_t (*efo_init)(efx_nic_t *); 281 void (*efo_fini)(efx_nic_t *); 282 efx_rc_t (*efo_restore)(efx_nic_t *); 283 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 284 efx_filter_replacement_policy_t policy); 285 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 286 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 287 size_t, size_t *); 288 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 289 boolean_t, boolean_t, boolean_t, 290 uint8_t const *, uint32_t); 291 } efx_filter_ops_t; 292 293 LIBEFX_INTERNAL 294 extern __checkReturn efx_rc_t 295 efx_filter_reconfigure( 296 __in efx_nic_t *enp, 297 __in_ecount(6) uint8_t const *mac_addr, 298 __in boolean_t all_unicst, 299 __in boolean_t mulcst, 300 __in boolean_t all_mulcst, 301 __in boolean_t brdcst, 302 __in_ecount(6*count) uint8_t const *addrs, 303 __in uint32_t count); 304 305 #endif /* EFSYS_OPT_FILTER */ 306 307 #if EFSYS_OPT_TUNNEL 308 typedef struct efx_tunnel_ops_s { 309 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 310 void (*eto_fini)(efx_nic_t *); 311 } efx_tunnel_ops_t; 312 #endif /* EFSYS_OPT_TUNNEL */ 313 314 #if EFSYS_OPT_VIRTIO 315 typedef struct efx_virtio_ops_s { 316 efx_rc_t (*evo_virtio_qstart)(efx_virtio_vq_t *, 317 efx_virtio_vq_cfg_t *, 318 efx_virtio_vq_dyncfg_t *); 319 efx_rc_t (*evo_virtio_qstop)(efx_virtio_vq_t *, 320 efx_virtio_vq_dyncfg_t *); 321 efx_rc_t (*evo_get_doorbell_offset)(efx_virtio_vq_t *, 322 uint32_t *); 323 efx_rc_t (*evo_get_features)(efx_nic_t *, 324 efx_virtio_device_type_t, uint64_t *); 325 efx_rc_t (*evo_verify_features)(efx_nic_t *, 326 efx_virtio_device_type_t, uint64_t); 327 } efx_virtio_ops_t; 328 #endif /* EFSYS_OPT_VIRTIO */ 329 330 typedef struct efx_port_s { 331 efx_mac_type_t ep_mac_type; 332 uint32_t ep_phy_type; 333 uint8_t ep_port; 334 uint32_t ep_mac_pdu; 335 uint8_t ep_mac_addr[6]; 336 efx_link_mode_t ep_link_mode; 337 boolean_t ep_all_unicst; 338 boolean_t ep_all_unicst_inserted; 339 boolean_t ep_mulcst; 340 boolean_t ep_all_mulcst; 341 boolean_t ep_all_mulcst_inserted; 342 boolean_t ep_brdcst; 343 unsigned int ep_fcntl; 344 boolean_t ep_fcntl_autoneg; 345 efx_oword_t ep_multicst_hash[2]; 346 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 347 EFX_MAC_MULTICAST_LIST_MAX]; 348 uint32_t ep_mulcst_addr_count; 349 #if EFSYS_OPT_LOOPBACK 350 efx_loopback_type_t ep_loopback_type; 351 efx_link_mode_t ep_loopback_link_mode; 352 #endif /* EFSYS_OPT_LOOPBACK */ 353 #if EFSYS_OPT_PHY_FLAGS 354 uint32_t ep_phy_flags; 355 #endif /* EFSYS_OPT_PHY_FLAGS */ 356 #if EFSYS_OPT_PHY_LED_CONTROL 357 efx_phy_led_mode_t ep_phy_led_mode; 358 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 359 efx_phy_media_type_t ep_fixed_port_type; 360 efx_phy_media_type_t ep_module_type; 361 uint32_t ep_adv_cap_mask; 362 uint32_t ep_lp_cap_mask; 363 uint32_t ep_default_adv_cap_mask; 364 uint32_t ep_phy_cap_mask; 365 boolean_t ep_mac_drain; 366 #if EFSYS_OPT_BIST 367 efx_bist_type_t ep_current_bist; 368 #endif 369 const efx_mac_ops_t *ep_emop; 370 const efx_phy_ops_t *ep_epop; 371 } efx_port_t; 372 373 typedef struct efx_mon_ops_s { 374 #if EFSYS_OPT_MON_STATS 375 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 376 efx_mon_stat_value_t *); 377 efx_rc_t (*emo_limits_update)(efx_nic_t *, 378 efx_mon_stat_limits_t *); 379 #endif /* EFSYS_OPT_MON_STATS */ 380 } efx_mon_ops_t; 381 382 typedef struct efx_mon_s { 383 efx_mon_type_t em_type; 384 const efx_mon_ops_t *em_emop; 385 } efx_mon_t; 386 387 typedef struct efx_intr_ops_s { 388 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 389 void (*eio_enable)(efx_nic_t *); 390 void (*eio_disable)(efx_nic_t *); 391 void (*eio_disable_unlocked)(efx_nic_t *); 392 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 393 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 394 void (*eio_status_message)(efx_nic_t *, unsigned int, 395 boolean_t *); 396 void (*eio_fatal)(efx_nic_t *); 397 void (*eio_fini)(efx_nic_t *); 398 } efx_intr_ops_t; 399 400 typedef struct efx_intr_s { 401 const efx_intr_ops_t *ei_eiop; 402 efsys_mem_t *ei_esmp; 403 efx_intr_type_t ei_type; 404 unsigned int ei_level; 405 } efx_intr_t; 406 407 typedef struct efx_nic_ops_s { 408 efx_rc_t (*eno_probe)(efx_nic_t *); 409 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 410 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 411 efx_rc_t (*eno_reset)(efx_nic_t *); 412 efx_rc_t (*eno_init)(efx_nic_t *); 413 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 414 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 415 uint32_t *, size_t *); 416 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 417 void (*eno_set_hw_unavailable)(efx_nic_t *); 418 #if EFSYS_OPT_DIAG 419 efx_rc_t (*eno_register_test)(efx_nic_t *); 420 #endif /* EFSYS_OPT_DIAG */ 421 void (*eno_fini)(efx_nic_t *); 422 void (*eno_unprobe)(efx_nic_t *); 423 } efx_nic_ops_t; 424 425 #ifndef EFX_TXQ_LIMIT_TARGET 426 #define EFX_TXQ_LIMIT_TARGET 259 427 #endif 428 #ifndef EFX_RXQ_LIMIT_TARGET 429 #define EFX_RXQ_LIMIT_TARGET 512 430 #endif 431 432 typedef struct efx_nic_dma_region_s { 433 efsys_dma_addr_t endr_nic_base; 434 efsys_dma_addr_t endr_trgt_base; 435 unsigned int endr_window_log2; 436 unsigned int endr_align_log2; 437 boolean_t endr_inuse; 438 } efx_nic_dma_region_t; 439 440 typedef struct efx_nic_dma_region_info_s { 441 unsigned int endri_count; 442 efx_nic_dma_region_t *endri_regions; 443 } efx_nic_dma_region_info_t; 444 445 typedef struct efx_nic_dma_s { 446 union { 447 /* No configuration in the case flat mapping type */ 448 efx_nic_dma_region_info_t endu_region_info; 449 } end_u; 450 } efx_nic_dma_t; 451 452 #if EFSYS_OPT_FILTER 453 454 #if EFSYS_OPT_SIENA 455 456 typedef struct siena_filter_spec_s { 457 uint8_t sfs_type; 458 uint32_t sfs_flags; 459 uint32_t sfs_dmaq_id; 460 uint32_t sfs_dword[3]; 461 } siena_filter_spec_t; 462 463 typedef enum siena_filter_type_e { 464 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 465 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 466 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 467 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 468 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 469 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 470 471 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 472 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 473 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 474 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 475 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 476 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 477 478 EFX_SIENA_FILTER_NTYPES 479 } siena_filter_type_t; 480 481 typedef enum siena_filter_tbl_id_e { 482 EFX_SIENA_FILTER_TBL_RX_IP = 0, 483 EFX_SIENA_FILTER_TBL_RX_MAC, 484 EFX_SIENA_FILTER_TBL_TX_IP, 485 EFX_SIENA_FILTER_TBL_TX_MAC, 486 EFX_SIENA_FILTER_NTBLS 487 } siena_filter_tbl_id_t; 488 489 typedef struct siena_filter_tbl_s { 490 int sft_size; /* number of entries */ 491 int sft_used; /* active count */ 492 uint32_t *sft_bitmap; /* active bitmap */ 493 siena_filter_spec_t *sft_spec; /* array of saved specs */ 494 } siena_filter_tbl_t; 495 496 typedef struct siena_filter_s { 497 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 498 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 499 } siena_filter_t; 500 501 #endif /* EFSYS_OPT_SIENA */ 502 503 typedef struct efx_filter_s { 504 #if EFSYS_OPT_SIENA 505 siena_filter_t *ef_siena_filter; 506 #endif /* EFSYS_OPT_SIENA */ 507 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 508 ef10_filter_table_t *ef_ef10_filter_table; 509 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 510 } efx_filter_t; 511 512 #if EFSYS_OPT_SIENA 513 514 LIBEFX_INTERNAL 515 extern void 516 siena_filter_tbl_clear( 517 __in efx_nic_t *enp, 518 __in siena_filter_tbl_id_t tbl); 519 520 #endif /* EFSYS_OPT_SIENA */ 521 522 #endif /* EFSYS_OPT_FILTER */ 523 524 #if EFSYS_OPT_MCDI 525 526 #define EFX_TUNNEL_MAXNENTRIES (16) 527 528 #if EFSYS_OPT_TUNNEL 529 530 /* State of a UDP tunnel table entry */ 531 typedef enum efx_tunnel_udp_entry_state_e { 532 EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */ 533 EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */ 534 EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */ 535 } efx_tunnel_udp_entry_state_t; 536 537 #if EFSYS_OPT_RIVERHEAD 538 typedef uint32_t efx_vnic_encap_rule_handle_t; 539 #endif /* EFSYS_OPT_RIVERHEAD */ 540 541 typedef struct efx_tunnel_udp_entry_s { 542 uint16_t etue_port; /* host/cpu-endian */ 543 uint16_t etue_protocol; 544 boolean_t etue_busy; 545 efx_tunnel_udp_entry_state_t etue_state; 546 #if EFSYS_OPT_RIVERHEAD 547 efx_vnic_encap_rule_handle_t etue_handle; 548 #endif /* EFSYS_OPT_RIVERHEAD */ 549 } efx_tunnel_udp_entry_t; 550 551 typedef struct efx_tunnel_cfg_s { 552 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 553 unsigned int etc_udp_entries_num; 554 } efx_tunnel_cfg_t; 555 556 #endif /* EFSYS_OPT_TUNNEL */ 557 558 typedef struct efx_mcdi_ops_s { 559 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 560 void (*emco_send_request)(efx_nic_t *, void *, size_t, 561 void *, size_t); 562 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 563 boolean_t (*emco_poll_response)(efx_nic_t *); 564 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 565 void (*emco_fini)(efx_nic_t *); 566 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 567 efx_mcdi_feature_id_t, boolean_t *); 568 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 569 uint32_t *); 570 } efx_mcdi_ops_t; 571 572 typedef struct efx_mcdi_s { 573 const efx_mcdi_ops_t *em_emcop; 574 const efx_mcdi_transport_t *em_emtp; 575 efx_mcdi_iface_t em_emip; 576 } efx_mcdi_t; 577 578 #endif /* EFSYS_OPT_MCDI */ 579 580 #if EFSYS_OPT_NVRAM 581 582 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 583 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 584 585 typedef struct efx_nvram_ops_s { 586 #if EFSYS_OPT_DIAG 587 efx_rc_t (*envo_test)(efx_nic_t *); 588 #endif /* EFSYS_OPT_DIAG */ 589 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 590 uint32_t *); 591 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, 592 efx_nvram_info_t *); 593 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 594 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 595 unsigned int, caddr_t, size_t); 596 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 597 unsigned int, caddr_t, size_t); 598 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 599 unsigned int, size_t); 600 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 601 unsigned int, caddr_t, size_t); 602 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 603 uint32_t *); 604 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 605 uint32_t *, uint16_t *); 606 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 607 uint16_t *); 608 efx_rc_t (*envo_buffer_validate)(uint32_t, 609 caddr_t, size_t); 610 } efx_nvram_ops_t; 611 #endif /* EFSYS_OPT_NVRAM */ 612 613 #if EFSYS_OPT_VPD 614 typedef struct efx_vpd_ops_s { 615 efx_rc_t (*evpdo_init)(efx_nic_t *); 616 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 617 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 618 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 619 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 620 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 621 efx_vpd_value_t *); 622 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 623 efx_vpd_value_t *); 624 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 625 efx_vpd_value_t *, unsigned int *); 626 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 627 void (*evpdo_fini)(efx_nic_t *); 628 } efx_vpd_ops_t; 629 #endif /* EFSYS_OPT_VPD */ 630 631 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 632 633 LIBEFX_INTERNAL 634 extern __checkReturn efx_rc_t 635 efx_mcdi_nvram_partitions( 636 __in efx_nic_t *enp, 637 __out_bcount(size) caddr_t data, 638 __in size_t size, 639 __out unsigned int *npartnp); 640 641 LIBEFX_INTERNAL 642 extern __checkReturn efx_rc_t 643 efx_mcdi_nvram_metadata( 644 __in efx_nic_t *enp, 645 __in uint32_t partn, 646 __out uint32_t *subtypep, 647 __out_ecount(4) uint16_t version[4], 648 __out_bcount_opt(size) char *descp, 649 __in size_t size); 650 651 LIBEFX_INTERNAL 652 extern __checkReturn efx_rc_t 653 efx_mcdi_nvram_info( 654 __in efx_nic_t *enp, 655 __in uint32_t partn, 656 __out efx_nvram_info_t *eni); 657 658 LIBEFX_INTERNAL 659 extern __checkReturn efx_rc_t 660 efx_mcdi_nvram_update_start( 661 __in efx_nic_t *enp, 662 __in uint32_t partn); 663 664 LIBEFX_INTERNAL 665 extern __checkReturn efx_rc_t 666 efx_mcdi_nvram_read( 667 __in efx_nic_t *enp, 668 __in uint32_t partn, 669 __in uint32_t offset, 670 __out_bcount(size) caddr_t data, 671 __in size_t size, 672 __in uint32_t mode); 673 674 LIBEFX_INTERNAL 675 extern __checkReturn efx_rc_t 676 efx_mcdi_nvram_erase( 677 __in efx_nic_t *enp, 678 __in uint32_t partn, 679 __in uint32_t offset, 680 __in size_t size); 681 682 LIBEFX_INTERNAL 683 extern __checkReturn efx_rc_t 684 efx_mcdi_nvram_write( 685 __in efx_nic_t *enp, 686 __in uint32_t partn, 687 __in uint32_t offset, 688 __in_bcount(size) caddr_t data, 689 __in size_t size); 690 691 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 692 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 693 694 LIBEFX_INTERNAL 695 extern __checkReturn efx_rc_t 696 efx_mcdi_nvram_update_finish( 697 __in efx_nic_t *enp, 698 __in uint32_t partn, 699 __in boolean_t reboot, 700 __in uint32_t flags, 701 __out_opt uint32_t *verify_resultp); 702 703 #if EFSYS_OPT_DIAG 704 705 LIBEFX_INTERNAL 706 extern __checkReturn efx_rc_t 707 efx_mcdi_nvram_test( 708 __in efx_nic_t *enp, 709 __in uint32_t partn); 710 711 #endif /* EFSYS_OPT_DIAG */ 712 713 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 714 715 #if EFSYS_OPT_LICENSING 716 717 typedef struct efx_lic_ops_s { 718 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 719 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 720 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 721 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 722 size_t *, uint8_t *); 723 efx_rc_t (*elo_find_start) 724 (efx_nic_t *, caddr_t, size_t, uint32_t *); 725 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 726 uint32_t, uint32_t *); 727 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 728 uint32_t, uint32_t *, uint32_t *); 729 boolean_t (*elo_validate_key)(efx_nic_t *, 730 caddr_t, uint32_t); 731 efx_rc_t (*elo_read_key)(efx_nic_t *, 732 caddr_t, size_t, uint32_t, uint32_t, 733 caddr_t, size_t, uint32_t *); 734 efx_rc_t (*elo_write_key)(efx_nic_t *, 735 caddr_t, size_t, uint32_t, 736 caddr_t, uint32_t, uint32_t *); 737 efx_rc_t (*elo_delete_key)(efx_nic_t *, 738 caddr_t, size_t, uint32_t, 739 uint32_t, uint32_t, uint32_t *); 740 efx_rc_t (*elo_create_partition)(efx_nic_t *, 741 caddr_t, size_t); 742 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 743 caddr_t, size_t); 744 } efx_lic_ops_t; 745 746 #endif 747 748 #if EFSYS_OPT_EVB 749 750 struct efx_vswitch_s { 751 efx_nic_t *ev_enp; 752 efx_vswitch_id_t ev_vswitch_id; 753 uint32_t ev_num_vports; 754 /* 755 * Vport configuration array: index 0 to store PF configuration 756 * and next ev_num_vports-1 entries hold VFs configuration. 757 */ 758 efx_vport_config_t *ev_evcp; 759 }; 760 761 typedef struct efx_evb_ops_s { 762 efx_rc_t (*eeo_init)(efx_nic_t *); 763 void (*eeo_fini)(efx_nic_t *); 764 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); 765 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); 766 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, 767 efx_vport_type_t, uint16_t, 768 boolean_t, efx_vport_id_t *); 769 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, 770 efx_vport_id_t); 771 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, 772 efx_vport_id_t, uint8_t *); 773 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, 774 efx_vport_id_t, uint8_t *); 775 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, 776 efx_vport_id_t); 777 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, 778 efx_vport_id_t); 779 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, 780 efx_vport_id_t, uint32_t); 781 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t, 782 efx_vport_id_t, 783 uint16_t *, uint8_t *, 784 boolean_t *); 785 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t, 786 efx_vport_id_t, efsys_mem_t *); 787 } efx_evb_ops_t; 788 789 LIBEFX_INTERNAL 790 extern __checkReturn boolean_t 791 efx_is_zero_eth_addr( 792 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); 793 794 #endif /* EFSYS_OPT_EVB */ 795 796 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 797 798 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF 799 800 801 typedef struct efx_proxy_ops_s { 802 efx_rc_t (*epo_init)(efx_nic_t *); 803 void (*epo_fini)(efx_nic_t *); 804 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *, 805 efsys_mem_t *, efsys_mem_t *, 806 uint32_t, uint32_t *, size_t); 807 efx_rc_t (*epo_disable)(efx_nic_t *); 808 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t, 809 uint32_t, uint32_t, uint32_t); 810 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t, 811 uint32_t, uint32_t); 812 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t, 813 uint32_t, uint32_t); 814 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *); 815 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t, 816 uint32_t, uint32_t *); 817 } efx_proxy_ops_t; 818 819 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 820 821 #if EFSYS_OPT_MAE 822 823 typedef struct efx_mae_field_cap_s { 824 uint32_t emfc_support; 825 boolean_t emfc_mask_affects_class; 826 boolean_t emfc_match_affects_class; 827 } efx_mae_field_cap_t; 828 829 typedef struct efx_mae_s { 830 uint32_t em_max_n_action_prios; 831 /* 832 * The number of MAE field IDs recognised by the FW implementation. 833 * Any field ID greater than or equal to this value is unsupported. 834 */ 835 uint32_t em_max_nfields; 836 /** Action rule match field capabilities. */ 837 efx_mae_field_cap_t *em_action_rule_field_caps; 838 size_t em_action_rule_field_caps_size; 839 uint32_t em_max_n_outer_prios; 840 uint32_t em_encap_types_supported; 841 /** Outer rule match field capabilities. */ 842 efx_mae_field_cap_t *em_outer_rule_field_caps; 843 size_t em_outer_rule_field_caps_size; 844 uint32_t em_max_ncounters; 845 } efx_mae_t; 846 847 #endif /* EFSYS_OPT_MAE */ 848 849 #define EFX_DRV_VER_MAX 20 850 851 typedef struct efx_drv_cfg_s { 852 uint32_t edc_min_vi_count; 853 uint32_t edc_max_vi_count; 854 855 uint32_t edc_max_piobuf_count; 856 uint32_t edc_pio_alloc_size; 857 } efx_drv_cfg_t; 858 859 struct efx_nic_s { 860 uint32_t en_magic; 861 efx_family_t en_family; 862 uint32_t en_features; 863 efsys_identifier_t *en_esip; 864 efsys_lock_t *en_eslp; 865 efsys_bar_t *en_esbp; 866 unsigned int en_mod_flags; 867 unsigned int en_reset_flags; 868 efx_nic_cfg_t en_nic_cfg; 869 efx_drv_cfg_t en_drv_cfg; 870 efx_port_t en_port; 871 efx_mon_t en_mon; 872 efx_intr_t en_intr; 873 uint32_t en_ev_qcount; 874 uint32_t en_rx_qcount; 875 uint32_t en_tx_qcount; 876 const efx_nic_ops_t *en_enop; 877 const efx_ev_ops_t *en_eevop; 878 const efx_tx_ops_t *en_etxop; 879 const efx_rx_ops_t *en_erxop; 880 efx_fw_variant_t efv; 881 char en_drv_version[EFX_DRV_VER_MAX]; 882 efx_nic_dma_t en_dma; 883 #if EFSYS_OPT_FILTER 884 efx_filter_t en_filter; 885 const efx_filter_ops_t *en_efop; 886 #endif /* EFSYS_OPT_FILTER */ 887 #if EFSYS_OPT_TUNNEL 888 efx_tunnel_cfg_t en_tunnel_cfg; 889 const efx_tunnel_ops_t *en_etop; 890 #endif /* EFSYS_OPT_TUNNEL */ 891 #if EFSYS_OPT_MCDI 892 efx_mcdi_t en_mcdi; 893 #endif /* EFSYS_OPT_MCDI */ 894 #if EFSYS_OPT_NVRAM 895 uint32_t en_nvram_partn_locked; 896 const efx_nvram_ops_t *en_envop; 897 #endif /* EFSYS_OPT_NVRAM */ 898 #if EFSYS_OPT_VPD 899 const efx_vpd_ops_t *en_evpdop; 900 #endif /* EFSYS_OPT_VPD */ 901 #if EFSYS_OPT_VIRTIO 902 const efx_virtio_ops_t *en_evop; 903 #endif /* EFSYS_OPT_VPD */ 904 #if EFSYS_OPT_RX_SCALE 905 efx_rx_hash_support_t en_hash_support; 906 efx_rx_scale_context_type_t en_rss_context_type; 907 uint32_t en_rss_context; 908 #endif /* EFSYS_OPT_RX_SCALE */ 909 uint32_t en_vport_id; 910 #if EFSYS_OPT_LICENSING 911 const efx_lic_ops_t *en_elop; 912 boolean_t en_licensing_supported; 913 #endif 914 union { 915 #if EFSYS_OPT_SIENA 916 struct { 917 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 918 unsigned int enu_partn_mask; 919 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 920 #if EFSYS_OPT_VPD 921 caddr_t enu_svpd; 922 size_t enu_svpd_length; 923 #endif /* EFSYS_OPT_VPD */ 924 int enu_unused; 925 } siena; 926 #endif /* EFSYS_OPT_SIENA */ 927 int enu_unused; 928 } en_u; 929 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 930 union en_arch { 931 struct { 932 int ena_vi_base; 933 int ena_vi_count; 934 int ena_vi_shift; 935 uint32_t ena_fcw_base; 936 #if EFSYS_OPT_VPD 937 caddr_t ena_svpd; 938 size_t ena_svpd_length; 939 #endif /* EFSYS_OPT_VPD */ 940 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 941 uint32_t ena_piobuf_count; 942 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 943 uint32_t ena_pio_write_vi_base; 944 /* Memory BAR mapping regions */ 945 uint32_t ena_uc_mem_map_offset; 946 size_t ena_uc_mem_map_size; 947 uint32_t ena_wc_mem_map_offset; 948 size_t ena_wc_mem_map_size; 949 } ef10; 950 } en_arch; 951 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 952 #if EFSYS_OPT_EVB 953 const efx_evb_ops_t *en_eeop; 954 struct efx_vswitch_s *en_vswitchp; 955 #endif /* EFSYS_OPT_EVB */ 956 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 957 const efx_proxy_ops_t *en_epop; 958 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 959 #if EFSYS_OPT_MAE 960 efx_mae_t *en_maep; 961 #endif /* EFSYS_OPT_MAE */ 962 }; 963 964 #define EFX_FAMILY_IS_EF10(_enp) \ 965 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ 966 (_enp)->en_family == EFX_FAMILY_MEDFORD || \ 967 (_enp)->en_family == EFX_FAMILY_HUNTINGTON) 968 969 #define EFX_FAMILY_IS_EF100(_enp) \ 970 ((_enp)->en_family == EFX_FAMILY_RIVERHEAD) 971 972 973 #define EFX_NIC_MAGIC 0x02121996 974 975 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 976 const efx_ev_callbacks_t *, void *); 977 978 #if EFSYS_OPT_EV_EXTENDED_WIDTH 979 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *, 980 const efx_ev_callbacks_t *, void *); 981 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */ 982 983 typedef struct efx_evq_rxq_state_s { 984 unsigned int eers_rx_read_ptr; 985 unsigned int eers_rx_mask; 986 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 987 unsigned int eers_rx_stream_npackets; 988 boolean_t eers_rx_packed_stream; 989 #endif 990 #if EFSYS_OPT_RX_PACKED_STREAM 991 unsigned int eers_rx_packed_stream_credits; 992 #endif 993 } efx_evq_rxq_state_t; 994 995 struct efx_evq_s { 996 uint32_t ee_magic; 997 uint32_t ee_flags; 998 efx_nic_t *ee_enp; 999 unsigned int ee_index; 1000 unsigned int ee_mask; 1001 efsys_mem_t *ee_esmp; 1002 #if EFSYS_OPT_QSTATS 1003 uint32_t ee_stat[EV_NQSTATS]; 1004 #endif /* EFSYS_OPT_QSTATS */ 1005 1006 efx_ev_handler_t ee_rx; 1007 efx_ev_handler_t ee_tx; 1008 efx_ev_handler_t ee_driver; 1009 efx_ev_handler_t ee_global; 1010 efx_ev_handler_t ee_drv_gen; 1011 #if EFSYS_OPT_MCDI 1012 efx_ev_handler_t ee_mcdi; 1013 #endif /* EFSYS_OPT_MCDI */ 1014 1015 #if EFSYS_OPT_DESC_PROXY 1016 efx_ev_ew_handler_t ee_ew_txq_desc; 1017 efx_ev_ew_handler_t ee_ew_virtq_desc; 1018 #endif /* EFSYS_OPT_DESC_PROXY */ 1019 1020 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 1021 }; 1022 1023 #define EFX_EVQ_MAGIC 0x08081997 1024 1025 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 1026 1027 #if EFSYS_OPT_QSTATS 1028 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 1029 do { \ 1030 (_eep)->ee_stat[_stat]++; \ 1031 _NOTE(CONSTANTCONDITION) \ 1032 } while (B_FALSE) 1033 #else 1034 #define EFX_EV_QSTAT_INCR(_eep, _stat) 1035 #endif 1036 1037 struct efx_rxq_s { 1038 uint32_t er_magic; 1039 efx_nic_t *er_enp; 1040 efx_evq_t *er_eep; 1041 unsigned int er_index; 1042 unsigned int er_label; 1043 unsigned int er_mask; 1044 size_t er_buf_size; 1045 efsys_mem_t *er_esmp; 1046 efx_evq_rxq_state_t *er_ev_qstate; 1047 efx_rx_prefix_layout_t er_prefix_layout; 1048 }; 1049 1050 #define EFX_RXQ_MAGIC 0x15022005 1051 1052 struct efx_txq_s { 1053 uint32_t et_magic; 1054 efx_nic_t *et_enp; 1055 unsigned int et_index; 1056 unsigned int et_mask; 1057 efsys_mem_t *et_esmp; 1058 #if EFSYS_OPT_HUNTINGTON 1059 uint32_t et_pio_bufnum; 1060 uint32_t et_pio_blknum; 1061 uint32_t et_pio_write_offset; 1062 uint32_t et_pio_offset; 1063 size_t et_pio_size; 1064 #endif 1065 #if EFSYS_OPT_QSTATS 1066 uint32_t et_stat[TX_NQSTATS]; 1067 #endif /* EFSYS_OPT_QSTATS */ 1068 }; 1069 1070 #define EFX_TXQ_MAGIC 0x05092005 1071 1072 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 1073 do { \ 1074 (_dst)[0] = (_src)[0]; \ 1075 (_dst)[1] = (_src)[1]; \ 1076 (_dst)[2] = (_src)[2]; \ 1077 (_dst)[3] = (_src)[3]; \ 1078 (_dst)[4] = (_src)[4]; \ 1079 (_dst)[5] = (_src)[5]; \ 1080 _NOTE(CONSTANTCONDITION) \ 1081 } while (B_FALSE) 1082 1083 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 1084 do { \ 1085 uint16_t *_d = (uint16_t *)(_dst); \ 1086 _d[0] = 0xffff; \ 1087 _d[1] = 0xffff; \ 1088 _d[2] = 0xffff; \ 1089 _NOTE(CONSTANTCONDITION) \ 1090 } while (B_FALSE) 1091 1092 #if EFSYS_OPT_CHECK_REG 1093 #define EFX_CHECK_REG(_enp, _reg) \ 1094 do { \ 1095 const char *name = #_reg; \ 1096 char min = name[4]; \ 1097 char max = name[5]; \ 1098 char rev; \ 1099 \ 1100 switch ((_enp)->en_family) { \ 1101 case EFX_FAMILY_SIENA: \ 1102 rev = 'C'; \ 1103 break; \ 1104 \ 1105 case EFX_FAMILY_HUNTINGTON: \ 1106 rev = 'D'; \ 1107 break; \ 1108 \ 1109 case EFX_FAMILY_MEDFORD: \ 1110 rev = 'E'; \ 1111 break; \ 1112 \ 1113 case EFX_FAMILY_MEDFORD2: \ 1114 rev = 'F'; \ 1115 break; \ 1116 \ 1117 case EFX_FAMILY_RIVERHEAD: \ 1118 rev = 'G'; \ 1119 break; \ 1120 \ 1121 default: \ 1122 rev = '?'; \ 1123 break; \ 1124 } \ 1125 \ 1126 EFSYS_ASSERT3S(rev, >=, min); \ 1127 EFSYS_ASSERT3S(rev, <=, max); \ 1128 \ 1129 _NOTE(CONSTANTCONDITION) \ 1130 } while (B_FALSE) 1131 #else 1132 #define EFX_CHECK_REG(_enp, _reg) do { \ 1133 _NOTE(CONSTANTCONDITION) \ 1134 } while (B_FALSE) 1135 #endif 1136 1137 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 1138 do { \ 1139 EFX_CHECK_REG((_enp), (_reg)); \ 1140 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 1141 (_edp), (_lock)); \ 1142 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 1143 uint32_t, _reg ## _OFST, \ 1144 uint32_t, (_edp)->ed_u32[0]); \ 1145 _NOTE(CONSTANTCONDITION) \ 1146 } while (B_FALSE) 1147 1148 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 1149 do { \ 1150 EFX_CHECK_REG((_enp), (_reg)); \ 1151 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 1152 uint32_t, _reg ## _OFST, \ 1153 uint32_t, (_edp)->ed_u32[0]); \ 1154 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 1155 (_edp), (_lock)); \ 1156 _NOTE(CONSTANTCONDITION) \ 1157 } while (B_FALSE) 1158 1159 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 1160 do { \ 1161 EFX_CHECK_REG((_enp), (_reg)); \ 1162 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 1163 (_eqp)); \ 1164 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 1165 uint32_t, _reg ## _OFST, \ 1166 uint32_t, (_eqp)->eq_u32[1], \ 1167 uint32_t, (_eqp)->eq_u32[0]); \ 1168 _NOTE(CONSTANTCONDITION) \ 1169 } while (B_FALSE) 1170 1171 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 1172 do { \ 1173 EFX_CHECK_REG((_enp), (_reg)); \ 1174 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 1175 uint32_t, _reg ## _OFST, \ 1176 uint32_t, (_eqp)->eq_u32[1], \ 1177 uint32_t, (_eqp)->eq_u32[0]); \ 1178 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 1179 (_eqp)); \ 1180 _NOTE(CONSTANTCONDITION) \ 1181 } while (B_FALSE) 1182 1183 #define EFX_BAR_READO(_enp, _reg, _eop) \ 1184 do { \ 1185 EFX_CHECK_REG((_enp), (_reg)); \ 1186 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 1187 (_eop), B_TRUE); \ 1188 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 1189 uint32_t, _reg ## _OFST, \ 1190 uint32_t, (_eop)->eo_u32[3], \ 1191 uint32_t, (_eop)->eo_u32[2], \ 1192 uint32_t, (_eop)->eo_u32[1], \ 1193 uint32_t, (_eop)->eo_u32[0]); \ 1194 _NOTE(CONSTANTCONDITION) \ 1195 } while (B_FALSE) 1196 1197 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 1198 do { \ 1199 EFX_CHECK_REG((_enp), (_reg)); \ 1200 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 1201 uint32_t, _reg ## _OFST, \ 1202 uint32_t, (_eop)->eo_u32[3], \ 1203 uint32_t, (_eop)->eo_u32[2], \ 1204 uint32_t, (_eop)->eo_u32[1], \ 1205 uint32_t, (_eop)->eo_u32[0]); \ 1206 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 1207 (_eop), B_TRUE); \ 1208 _NOTE(CONSTANTCONDITION) \ 1209 } while (B_FALSE) 1210 1211 /* 1212 * Accessors for memory BAR non-VI tables. 1213 * 1214 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 1215 * to ensure the correct runtime VI window size is used on Medford2. 1216 * 1217 * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control 1218 * window registers, to ensure the correct starting offset is used. 1219 * 1220 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 1221 */ 1222 1223 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 1224 do { \ 1225 EFX_CHECK_REG((_enp), (_reg)); \ 1226 EFSYS_BAR_READD((_enp)->en_esbp, \ 1227 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1228 (_edp), (_lock)); \ 1229 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 1230 uint32_t, (_index), \ 1231 uint32_t, _reg ## _OFST, \ 1232 uint32_t, (_edp)->ed_u32[0]); \ 1233 _NOTE(CONSTANTCONDITION) \ 1234 } while (B_FALSE) 1235 1236 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1237 do { \ 1238 EFX_CHECK_REG((_enp), (_reg)); \ 1239 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1240 uint32_t, (_index), \ 1241 uint32_t, _reg ## _OFST, \ 1242 uint32_t, (_edp)->ed_u32[0]); \ 1243 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1244 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1245 (_edp), (_lock)); \ 1246 _NOTE(CONSTANTCONDITION) \ 1247 } while (B_FALSE) 1248 1249 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1250 do { \ 1251 EFX_CHECK_REG((_enp), (_reg)); \ 1252 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1253 uint32_t, (_index), \ 1254 uint32_t, _reg ## _OFST, \ 1255 uint32_t, (_edp)->ed_u32[0]); \ 1256 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1257 (_reg ## _OFST + \ 1258 (3 * sizeof (efx_dword_t)) + \ 1259 ((_index) * _reg ## _STEP)), \ 1260 (_edp), (_lock)); \ 1261 _NOTE(CONSTANTCONDITION) \ 1262 } while (B_FALSE) 1263 1264 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1265 do { \ 1266 EFX_CHECK_REG((_enp), (_reg)); \ 1267 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1268 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1269 (_eqp)); \ 1270 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1271 uint32_t, (_index), \ 1272 uint32_t, _reg ## _OFST, \ 1273 uint32_t, (_eqp)->eq_u32[1], \ 1274 uint32_t, (_eqp)->eq_u32[0]); \ 1275 _NOTE(CONSTANTCONDITION) \ 1276 } while (B_FALSE) 1277 1278 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1279 do { \ 1280 EFX_CHECK_REG((_enp), (_reg)); \ 1281 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1282 uint32_t, (_index), \ 1283 uint32_t, _reg ## _OFST, \ 1284 uint32_t, (_eqp)->eq_u32[1], \ 1285 uint32_t, (_eqp)->eq_u32[0]); \ 1286 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1287 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1288 (_eqp)); \ 1289 _NOTE(CONSTANTCONDITION) \ 1290 } while (B_FALSE) 1291 1292 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1293 do { \ 1294 EFX_CHECK_REG((_enp), (_reg)); \ 1295 EFSYS_BAR_READO((_enp)->en_esbp, \ 1296 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1297 (_eop), (_lock)); \ 1298 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1299 uint32_t, (_index), \ 1300 uint32_t, _reg ## _OFST, \ 1301 uint32_t, (_eop)->eo_u32[3], \ 1302 uint32_t, (_eop)->eo_u32[2], \ 1303 uint32_t, (_eop)->eo_u32[1], \ 1304 uint32_t, (_eop)->eo_u32[0]); \ 1305 _NOTE(CONSTANTCONDITION) \ 1306 } while (B_FALSE) 1307 1308 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1309 do { \ 1310 EFX_CHECK_REG((_enp), (_reg)); \ 1311 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1312 uint32_t, (_index), \ 1313 uint32_t, _reg ## _OFST, \ 1314 uint32_t, (_eop)->eo_u32[3], \ 1315 uint32_t, (_eop)->eo_u32[2], \ 1316 uint32_t, (_eop)->eo_u32[1], \ 1317 uint32_t, (_eop)->eo_u32[0]); \ 1318 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1319 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1320 (_eop), (_lock)); \ 1321 _NOTE(CONSTANTCONDITION) \ 1322 } while (B_FALSE) 1323 1324 /* 1325 * Accessors for memory BAR function control window registers. 1326 * 1327 * The function control window is located at an offset which can be 1328 * non-zero in case of Riverhead. 1329 */ 1330 1331 #if EFSYS_OPT_RIVERHEAD 1332 1333 #define EFX_BAR_FCW_READD(_enp, _reg, _edp) \ 1334 do { \ 1335 EFX_CHECK_REG((_enp), (_reg)); \ 1336 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST + \ 1337 (_enp)->en_arch.ef10.ena_fcw_base, \ 1338 (_edp), B_FALSE); \ 1339 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg, \ 1340 uint32_t, _reg ## _OFST, \ 1341 uint32_t, (_edp)->ed_u32[0]); \ 1342 _NOTE(CONSTANTCONDITION) \ 1343 } while (B_FALSE) 1344 1345 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp) \ 1346 do { \ 1347 EFX_CHECK_REG((_enp), (_reg)); \ 1348 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg, \ 1349 uint32_t, _reg ## _OFST, \ 1350 uint32_t, (_edp)->ed_u32[0]); \ 1351 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST + \ 1352 (_enp)->en_arch.ef10.ena_fcw_base, \ 1353 (_edp), B_FALSE); \ 1354 _NOTE(CONSTANTCONDITION) \ 1355 } while (B_FALSE) 1356 1357 #endif /* EFSYS_OPT_RIVERHEAD */ 1358 1359 /* 1360 * Accessors for memory BAR per-VI registers. 1361 * 1362 * The VI window size is 8KB for Medford and all earlier controllers. 1363 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1364 */ 1365 1366 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1367 do { \ 1368 EFX_CHECK_REG((_enp), (_reg)); \ 1369 EFSYS_BAR_READD((_enp)->en_esbp, \ 1370 ((_reg ## _OFST) + \ 1371 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1372 (_edp), (_lock)); \ 1373 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1374 uint32_t, (_index), \ 1375 uint32_t, _reg ## _OFST, \ 1376 uint32_t, (_edp)->ed_u32[0]); \ 1377 _NOTE(CONSTANTCONDITION) \ 1378 } while (B_FALSE) 1379 1380 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1381 do { \ 1382 EFX_CHECK_REG((_enp), (_reg)); \ 1383 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1384 uint32_t, (_index), \ 1385 uint32_t, _reg ## _OFST, \ 1386 uint32_t, (_edp)->ed_u32[0]); \ 1387 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1388 ((_reg ## _OFST) + \ 1389 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1390 (_edp), (_lock)); \ 1391 _NOTE(CONSTANTCONDITION) \ 1392 } while (B_FALSE) 1393 1394 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1395 do { \ 1396 EFX_CHECK_REG((_enp), (_reg)); \ 1397 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1398 uint32_t, (_index), \ 1399 uint32_t, _reg ## _OFST, \ 1400 uint32_t, (_edp)->ed_u32[0]); \ 1401 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1402 ((_reg ## _OFST) + \ 1403 (2 * sizeof (efx_dword_t)) + \ 1404 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1405 (_edp), (_lock)); \ 1406 _NOTE(CONSTANTCONDITION) \ 1407 } while (B_FALSE) 1408 1409 /* 1410 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1411 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1412 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1413 * the need for locking in the host, and are the only ones known to be safe to 1414 * use 128-bites write with. 1415 */ 1416 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1417 do { \ 1418 EFX_CHECK_REG((_enp), (_reg)); \ 1419 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1420 const char *, #_reg, \ 1421 uint32_t, (_index), \ 1422 uint32_t, _reg ## _OFST, \ 1423 uint32_t, (_eop)->eo_u32[3], \ 1424 uint32_t, (_eop)->eo_u32[2], \ 1425 uint32_t, (_eop)->eo_u32[1], \ 1426 uint32_t, (_eop)->eo_u32[0]); \ 1427 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1428 (_reg ## _OFST + \ 1429 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1430 (_eop)); \ 1431 _NOTE(CONSTANTCONDITION) \ 1432 } while (B_FALSE) 1433 1434 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \ 1435 _wptr, _owptr) \ 1436 do { \ 1437 unsigned int _new = (_wptr); \ 1438 unsigned int _old = (_owptr); \ 1439 \ 1440 if ((_new) >= (_old)) \ 1441 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1442 (_old) * (_desc_size), \ 1443 ((_new) - (_old)) * (_desc_size)); \ 1444 else \ 1445 /* \ 1446 * It is cheaper to sync entire map than sync \ 1447 * two parts especially when offset/size are \ 1448 * ignored and entire map is synced in any case.\ 1449 */ \ 1450 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1451 0, \ 1452 (_entries) * (_desc_size)); \ 1453 _NOTE(CONSTANTCONDITION) \ 1454 } while (B_FALSE) 1455 1456 LIBEFX_INTERNAL 1457 extern __checkReturn efx_rc_t 1458 efx_mac_select( 1459 __in efx_nic_t *enp); 1460 1461 LIBEFX_INTERNAL 1462 extern void 1463 efx_mac_multicast_hash_compute( 1464 __in_ecount(6*count) uint8_t const *addrs, 1465 __in int count, 1466 __out efx_oword_t *hash_low, 1467 __out efx_oword_t *hash_high); 1468 1469 LIBEFX_INTERNAL 1470 extern __checkReturn efx_rc_t 1471 efx_phy_probe( 1472 __in efx_nic_t *enp); 1473 1474 LIBEFX_INTERNAL 1475 extern void 1476 efx_phy_unprobe( 1477 __in efx_nic_t *enp); 1478 1479 #if EFSYS_OPT_VPD 1480 1481 /* VPD utility functions */ 1482 1483 LIBEFX_INTERNAL 1484 extern __checkReturn efx_rc_t 1485 efx_vpd_hunk_length( 1486 __in_bcount(size) caddr_t data, 1487 __in size_t size, 1488 __out size_t *lengthp); 1489 1490 LIBEFX_INTERNAL 1491 extern __checkReturn efx_rc_t 1492 efx_vpd_hunk_verify( 1493 __in_bcount(size) caddr_t data, 1494 __in size_t size, 1495 __out_opt boolean_t *cksummedp); 1496 1497 LIBEFX_INTERNAL 1498 extern __checkReturn efx_rc_t 1499 efx_vpd_hunk_reinit( 1500 __in_bcount(size) caddr_t data, 1501 __in size_t size, 1502 __in boolean_t wantpid); 1503 1504 LIBEFX_INTERNAL 1505 extern __checkReturn efx_rc_t 1506 efx_vpd_hunk_get( 1507 __in_bcount(size) caddr_t data, 1508 __in size_t size, 1509 __in efx_vpd_tag_t tag, 1510 __in efx_vpd_keyword_t keyword, 1511 __out unsigned int *payloadp, 1512 __out uint8_t *paylenp); 1513 1514 LIBEFX_INTERNAL 1515 extern __checkReturn efx_rc_t 1516 efx_vpd_hunk_next( 1517 __in_bcount(size) caddr_t data, 1518 __in size_t size, 1519 __out efx_vpd_tag_t *tagp, 1520 __out efx_vpd_keyword_t *keyword, 1521 __out_opt unsigned int *payloadp, 1522 __out_opt uint8_t *paylenp, 1523 __inout unsigned int *contp); 1524 1525 LIBEFX_INTERNAL 1526 extern __checkReturn efx_rc_t 1527 efx_vpd_hunk_set( 1528 __in_bcount(size) caddr_t data, 1529 __in size_t size, 1530 __in efx_vpd_value_t *evvp); 1531 1532 #endif /* EFSYS_OPT_VPD */ 1533 1534 #if EFSYS_OPT_MCDI 1535 1536 LIBEFX_INTERNAL 1537 extern __checkReturn efx_rc_t 1538 efx_mcdi_set_workaround( 1539 __in efx_nic_t *enp, 1540 __in uint32_t type, 1541 __in boolean_t enabled, 1542 __out_opt uint32_t *flagsp); 1543 1544 LIBEFX_INTERNAL 1545 extern __checkReturn efx_rc_t 1546 efx_mcdi_get_workarounds( 1547 __in efx_nic_t *enp, 1548 __out_opt uint32_t *implementedp, 1549 __out_opt uint32_t *enabledp); 1550 1551 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1552 1553 LIBEFX_INTERNAL 1554 extern __checkReturn efx_rc_t 1555 efx_mcdi_intf_from_pcie( 1556 __in uint32_t pcie_intf, 1557 __out efx_pcie_interface_t *efx_intf); 1558 1559 LIBEFX_INTERNAL 1560 extern __checkReturn efx_rc_t 1561 efx_mcdi_intf_to_pcie( 1562 __in efx_pcie_interface_t efx_intf, 1563 __out uint32_t *pcie_intf); 1564 1565 LIBEFX_INTERNAL 1566 extern __checkReturn efx_rc_t 1567 efx_mcdi_init_evq( 1568 __in efx_nic_t *enp, 1569 __in unsigned int instance, 1570 __in efsys_mem_t *esmp, 1571 __in size_t nevs, 1572 __in uint32_t irq, 1573 __in uint32_t target_evq, 1574 __in uint32_t us, 1575 __in uint32_t flags, 1576 __in boolean_t low_latency); 1577 1578 LIBEFX_INTERNAL 1579 extern __checkReturn efx_rc_t 1580 efx_mcdi_fini_evq( 1581 __in efx_nic_t *enp, 1582 __in uint32_t instance); 1583 1584 typedef struct efx_mcdi_init_rxq_params_s { 1585 boolean_t disable_scatter; 1586 boolean_t want_inner_classes; 1587 uint32_t buf_size; 1588 uint32_t ps_buf_size; 1589 uint32_t es_bufs_per_desc; 1590 uint32_t es_max_dma_len; 1591 uint32_t es_buf_stride; 1592 uint32_t hol_block_timeout; 1593 uint32_t prefix_id; 1594 } efx_mcdi_init_rxq_params_t; 1595 1596 LIBEFX_INTERNAL 1597 extern __checkReturn efx_rc_t 1598 efx_mcdi_init_rxq( 1599 __in efx_nic_t *enp, 1600 __in uint32_t ndescs, 1601 __in efx_evq_t *eep, 1602 __in uint32_t label, 1603 __in uint32_t instance, 1604 __in efsys_mem_t *esmp, 1605 __in const efx_mcdi_init_rxq_params_t *params); 1606 1607 LIBEFX_INTERNAL 1608 extern __checkReturn efx_rc_t 1609 efx_mcdi_fini_rxq( 1610 __in efx_nic_t *enp, 1611 __in uint32_t instance); 1612 1613 LIBEFX_INTERNAL 1614 extern __checkReturn efx_rc_t 1615 efx_mcdi_init_txq( 1616 __in efx_nic_t *enp, 1617 __in uint32_t ndescs, 1618 __in uint32_t target_evq, 1619 __in uint32_t label, 1620 __in uint32_t instance, 1621 __in uint16_t flags, 1622 __in efsys_mem_t *esmp); 1623 1624 LIBEFX_INTERNAL 1625 extern __checkReturn efx_rc_t 1626 efx_mcdi_fini_txq( 1627 __in efx_nic_t *enp, 1628 __in uint32_t instance); 1629 1630 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1631 1632 #endif /* EFSYS_OPT_MCDI */ 1633 1634 #if EFSYS_OPT_MAC_STATS 1635 1636 /* 1637 * Closed range of stats (i.e. the first and the last are included). 1638 * The last must be greater or equal (if the range is one item only) to 1639 * the first. 1640 */ 1641 struct efx_mac_stats_range { 1642 efx_mac_stat_t first; 1643 efx_mac_stat_t last; 1644 }; 1645 1646 typedef enum efx_stats_action_e { 1647 EFX_STATS_CLEAR, 1648 EFX_STATS_UPLOAD, 1649 EFX_STATS_ENABLE_NOEVENTS, 1650 EFX_STATS_ENABLE_EVENTS, 1651 EFX_STATS_DISABLE, 1652 } efx_stats_action_t; 1653 1654 LIBEFX_INTERNAL 1655 extern efx_rc_t 1656 efx_mac_stats_mask_add_ranges( 1657 __inout_bcount(mask_size) uint32_t *maskp, 1658 __in size_t mask_size, 1659 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1660 __in unsigned int rng_count); 1661 1662 LIBEFX_INTERNAL 1663 extern __checkReturn efx_rc_t 1664 efx_mcdi_mac_stats( 1665 __in efx_nic_t *enp, 1666 __in uint32_t vport_id, 1667 __in_opt efsys_mem_t *esmp, 1668 __in efx_stats_action_t action, 1669 __in uint16_t period_ms); 1670 1671 #endif /* EFSYS_OPT_MAC_STATS */ 1672 1673 #if EFSYS_OPT_PCI 1674 1675 /* 1676 * Find the next extended capability in a PCI device's config space 1677 * with specified capability id. 1678 * Passing 0 offset makes the function search from the start. 1679 * If search succeeds, found capability is in modified offset. 1680 * 1681 * Returns ENOENT if a capability is not found. 1682 */ 1683 LIBEFX_INTERNAL 1684 extern __checkReturn efx_rc_t 1685 efx_pci_config_find_next_ext_cap( 1686 __in efsys_pci_config_t *espcp, 1687 __in const efx_pci_ops_t *epop, 1688 __in uint16_t cap_id, 1689 __inout size_t *offsetp); 1690 1691 /* 1692 * Get the next extended capability in a PCI device's config space. 1693 * Passing 0 offset makes the function get the first capability. 1694 * If search succeeds, the capability is in modified offset. 1695 * 1696 * Returns ENOENT if there is no next capability. 1697 */ 1698 LIBEFX_INTERNAL 1699 extern __checkReturn efx_rc_t 1700 efx_pci_config_next_ext_cap( 1701 __in efsys_pci_config_t *espcp, 1702 __in const efx_pci_ops_t *epop, 1703 __inout size_t *offsetp); 1704 1705 /* 1706 * Find the next Xilinx capabilities table location by searching 1707 * PCI extended capabilities. 1708 * 1709 * Returns ENOENT if a table location is not found. 1710 */ 1711 LIBEFX_INTERNAL 1712 extern __checkReturn efx_rc_t 1713 efx_pci_find_next_xilinx_cap_table( 1714 __in efsys_pci_config_t *espcp, 1715 __in const efx_pci_ops_t *epop, 1716 __inout size_t *pci_cap_offsetp, 1717 __out unsigned int *xilinx_tbl_barp, 1718 __out efsys_dma_addr_t *xilinx_tbl_offsetp); 1719 1720 /* 1721 * Read a Xilinx extended PCI capability that gives the location 1722 * of a Xilinx capabilities table. 1723 * 1724 * Returns ENOENT if the extended PCI capability does not contain 1725 * Xilinx capabilities table locator. 1726 */ 1727 LIBEFX_INTERNAL 1728 extern __checkReturn efx_rc_t 1729 efx_pci_read_ext_cap_xilinx_table( 1730 __in efsys_pci_config_t *espcp, 1731 __in const efx_pci_ops_t *epop, 1732 __in size_t cap_offset, 1733 __out unsigned int *barp, 1734 __out efsys_dma_addr_t *offsetp); 1735 1736 /* 1737 * Find a capability with specified format_id in a Xilinx capabilities table. 1738 * Searching is started from provided offset, taking skip_first into account. 1739 * If search succeeds, found capability is in modified offset. 1740 * 1741 * Returns ENOENT if an entry with specified format id is not found. 1742 */ 1743 LIBEFX_INTERNAL 1744 extern __checkReturn efx_rc_t 1745 efx_pci_xilinx_cap_tbl_find( 1746 __in efsys_bar_t *esbp, 1747 __in uint32_t format_id, 1748 __in boolean_t skip_first, 1749 __inout efsys_dma_addr_t *entry_offsetp); 1750 1751 #endif /* EFSYS_OPT_PCI */ 1752 1753 #if EFSYS_OPT_MAE 1754 1755 struct efx_mae_match_spec_s { 1756 efx_mae_rule_type_t emms_type; 1757 uint32_t emms_prio; 1758 union emms_mask_value_pairs { 1759 uint8_t action[ 1760 MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN]; 1761 uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN]; 1762 } emms_mask_value_pairs; 1763 uint8_t emms_outer_rule_recirc_id; 1764 }; 1765 1766 typedef enum efx_mae_action_e { 1767 /* These actions are strictly ordered. */ 1768 EFX_MAE_ACTION_DECAP, 1769 EFX_MAE_ACTION_VLAN_POP, 1770 EFX_MAE_ACTION_SET_DST_MAC, 1771 EFX_MAE_ACTION_SET_SRC_MAC, 1772 EFX_MAE_ACTION_DECR_IP_TTL, 1773 EFX_MAE_ACTION_VLAN_PUSH, 1774 EFX_MAE_ACTION_COUNT, 1775 EFX_MAE_ACTION_ENCAP, 1776 1777 /* 1778 * These actions are not strictly ordered and can 1779 * be passed by a client in any order (before DELIVER). 1780 * However, these enumerants must be kept compactly 1781 * in the end of the enumeration (before DELIVER). 1782 */ 1783 EFX_MAE_ACTION_FLAG, 1784 EFX_MAE_ACTION_MARK, 1785 1786 /* DELIVER is always the last action. */ 1787 EFX_MAE_ACTION_DELIVER, 1788 1789 EFX_MAE_NACTIONS 1790 } efx_mae_action_t; 1791 1792 /* MAE VLAN_POP action can handle 1 or 2 tags. */ 1793 #define EFX_MAE_VLAN_POP_MAX_NTAGS (2) 1794 1795 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */ 1796 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS (2) 1797 1798 typedef struct efx_mae_action_vlan_push_s { 1799 uint16_t emavp_tpid_be; 1800 uint16_t emavp_tci_be; 1801 } efx_mae_action_vlan_push_t; 1802 1803 typedef struct efx_mae_actions_rsrc_s { 1804 efx_mae_mac_id_t emar_dst_mac_id; 1805 efx_mae_mac_id_t emar_src_mac_id; 1806 efx_mae_eh_id_t emar_eh_id; 1807 efx_counter_t emar_counter_id; 1808 } efx_mae_actions_rsrc_t; 1809 1810 struct efx_mae_actions_s { 1811 /* Bitmap of actions in spec, indexed by action type */ 1812 uint32_t ema_actions; 1813 1814 unsigned int ema_n_vlan_tags_to_pop; 1815 unsigned int ema_n_vlan_tags_to_push; 1816 efx_mae_action_vlan_push_t ema_vlan_push_descs[ 1817 EFX_MAE_VLAN_PUSH_MAX_NTAGS]; 1818 unsigned int ema_n_count_actions; 1819 uint32_t ema_mark_value; 1820 efx_mport_sel_t ema_deliver_mport; 1821 1822 /* 1823 * Always keep this at the end of the struct since 1824 * efx_mae_action_set_specs_equal() relies on that 1825 * to make sure that resource IDs are not compared. 1826 */ 1827 efx_mae_actions_rsrc_t ema_rsrc; 1828 1829 /* 1830 * A copy of encp->enc_mae_aset_v2_supported. 1831 * It is set by efx_mae_action_set_spec_init(). 1832 * This value is ignored on spec comparisons. 1833 */ 1834 boolean_t ema_v2_is_supported; 1835 }; 1836 1837 #endif /* EFSYS_OPT_MAE */ 1838 1839 #if EFSYS_OPT_VIRTIO 1840 1841 #define EFX_VQ_MAGIC 0x026011950 1842 1843 typedef enum efx_virtio_vq_state_e { 1844 EFX_VIRTIO_VQ_STATE_UNKNOWN = 0, 1845 EFX_VIRTIO_VQ_STATE_INITIALIZED, 1846 EFX_VIRTIO_VQ_STATE_STARTED, 1847 EFX_VIRTIO_VQ_NSTATES 1848 } efx_virtio_vq_state_t; 1849 1850 struct efx_virtio_vq_s { 1851 uint32_t evv_magic; 1852 efx_nic_t *evv_enp; 1853 efx_virtio_vq_state_t evv_state; 1854 uint32_t evv_vi_index; 1855 efx_virtio_vq_type_t evv_type; 1856 uint16_t evv_target_vf; 1857 }; 1858 1859 #endif /* EFSYS_OPT_VIRTIO */ 1860 1861 #ifdef __cplusplus 1862 } 1863 #endif 1864 1865 #endif /* _SYS_EFX_IMPL_H */ 1866