1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2012-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 10 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 11 12 static void 13 mcdi_phy_decode_cap( 14 __in uint32_t mcdi_cap, 15 __out uint32_t *maskp) 16 { 17 uint32_t mask; 18 19 #define CHECK_CAP(_cap) \ 20 EFX_STATIC_ASSERT(EFX_PHY_CAP_##_cap == MC_CMD_PHY_CAP_##_cap##_LBN) 21 22 CHECK_CAP(10HDX); 23 CHECK_CAP(10FDX); 24 CHECK_CAP(100HDX); 25 CHECK_CAP(100FDX); 26 CHECK_CAP(1000HDX); 27 CHECK_CAP(1000FDX); 28 CHECK_CAP(10000FDX); 29 CHECK_CAP(25000FDX); 30 CHECK_CAP(40000FDX); 31 CHECK_CAP(50000FDX); 32 CHECK_CAP(100000FDX); 33 CHECK_CAP(PAUSE); 34 CHECK_CAP(ASYM); 35 CHECK_CAP(AN); 36 CHECK_CAP(DDM); 37 CHECK_CAP(BASER_FEC); 38 CHECK_CAP(BASER_FEC_REQUESTED); 39 CHECK_CAP(RS_FEC); 40 CHECK_CAP(RS_FEC_REQUESTED); 41 CHECK_CAP(25G_BASER_FEC); 42 CHECK_CAP(25G_BASER_FEC_REQUESTED); 43 #undef CHECK_CAP 44 45 mask = 0; 46 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) 47 mask |= (1 << EFX_PHY_CAP_10HDX); 48 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) 49 mask |= (1 << EFX_PHY_CAP_10FDX); 50 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) 51 mask |= (1 << EFX_PHY_CAP_100HDX); 52 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) 53 mask |= (1 << EFX_PHY_CAP_100FDX); 54 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) 55 mask |= (1 << EFX_PHY_CAP_1000HDX); 56 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 57 mask |= (1 << EFX_PHY_CAP_1000FDX); 58 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 59 mask |= (1 << EFX_PHY_CAP_10000FDX); 60 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25000FDX_LBN)) 61 mask |= (1 << EFX_PHY_CAP_25000FDX); 62 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 63 mask |= (1 << EFX_PHY_CAP_40000FDX); 64 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_50000FDX_LBN)) 65 mask |= (1 << EFX_PHY_CAP_50000FDX); 66 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100000FDX_LBN)) 67 mask |= (1 << EFX_PHY_CAP_100000FDX); 68 69 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 70 mask |= (1 << EFX_PHY_CAP_PAUSE); 71 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 72 mask |= (1 << EFX_PHY_CAP_ASYM); 73 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 74 mask |= (1 << EFX_PHY_CAP_AN); 75 76 /* FEC caps (supported on Medford2 and later) */ 77 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN)) 78 mask |= (1 << EFX_PHY_CAP_BASER_FEC); 79 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN)) 80 mask |= (1 << EFX_PHY_CAP_BASER_FEC_REQUESTED); 81 82 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN)) 83 mask |= (1 << EFX_PHY_CAP_RS_FEC); 84 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN)) 85 mask |= (1 << EFX_PHY_CAP_RS_FEC_REQUESTED); 86 87 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN)) 88 mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC); 89 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN)) 90 mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED); 91 92 *maskp = mask; 93 } 94 95 static void 96 mcdi_phy_decode_link_mode( 97 __in efx_nic_t *enp, 98 __in uint32_t link_flags, 99 __in unsigned int speed, 100 __in unsigned int fcntl, 101 __in uint32_t fec, 102 __out efx_link_mode_t *link_modep, 103 __out unsigned int *fcntlp, 104 __out efx_phy_fec_type_t *fecp) 105 { 106 boolean_t fd = !!(link_flags & 107 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); 108 boolean_t up = !!(link_flags & 109 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); 110 111 _NOTE(ARGUNUSED(enp)) 112 113 if (!up) 114 *link_modep = EFX_LINK_DOWN; 115 else if (speed == 100000 && fd) 116 *link_modep = EFX_LINK_100000FDX; 117 else if (speed == 50000 && fd) 118 *link_modep = EFX_LINK_50000FDX; 119 else if (speed == 40000 && fd) 120 *link_modep = EFX_LINK_40000FDX; 121 else if (speed == 25000 && fd) 122 *link_modep = EFX_LINK_25000FDX; 123 else if (speed == 10000 && fd) 124 *link_modep = EFX_LINK_10000FDX; 125 else if (speed == 1000) 126 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; 127 else if (speed == 100) 128 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; 129 else if (speed == 10) 130 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; 131 else 132 *link_modep = EFX_LINK_UNKNOWN; 133 134 if (fcntl == MC_CMD_FCNTL_OFF) 135 *fcntlp = 0; 136 else if (fcntl == MC_CMD_FCNTL_RESPOND) 137 *fcntlp = EFX_FCNTL_RESPOND; 138 else if (fcntl == MC_CMD_FCNTL_GENERATE) 139 *fcntlp = EFX_FCNTL_GENERATE; 140 else if (fcntl == MC_CMD_FCNTL_BIDIR) 141 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 142 else { 143 EFSYS_PROBE1(mc_pcol_error, int, fcntl); 144 *fcntlp = 0; 145 } 146 147 switch (fec) { 148 case MC_CMD_FEC_NONE: 149 *fecp = EFX_PHY_FEC_NONE; 150 break; 151 case MC_CMD_FEC_BASER: 152 *fecp = EFX_PHY_FEC_BASER; 153 break; 154 case MC_CMD_FEC_RS: 155 *fecp = EFX_PHY_FEC_RS; 156 break; 157 default: 158 EFSYS_PROBE1(mc_pcol_error, int, fec); 159 *fecp = EFX_PHY_FEC_NONE; 160 break; 161 } 162 } 163 164 165 void 166 ef10_phy_link_ev( 167 __in efx_nic_t *enp, 168 __in efx_qword_t *eqp, 169 __in boolean_t ev_is_v2, 170 __out efx_link_mode_t *link_modep) 171 { 172 efx_port_t *epp = &(enp->en_port); 173 unsigned int link_flags; 174 unsigned int speed; 175 unsigned int fcntl; 176 efx_phy_fec_type_t fec = MC_CMD_FEC_NONE; 177 efx_link_mode_t link_mode; 178 unsigned int ev_lp_cap; 179 unsigned int ev_fcntl; 180 unsigned int ev_speed; 181 uint32_t lp_cap_mask; 182 183 if (ev_is_v2) { 184 link_flags = (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN); 185 if (MCDI_EV_FIELD(eqp, LINKCHANGE_V2_FLAGS_LINK_UP)) 186 link_flags |= (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN); 187 188 ev_lp_cap = MCDI_EV_FIELD(eqp, LINKCHANGE_V2_LP_CAP); 189 ev_fcntl = MCDI_EV_FIELD(eqp, LINKCHANGE_V2_FCNTL); 190 ev_speed = MCDI_EV_FIELD(eqp, LINKCHANGE_V2_SPEED); 191 } else { 192 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); 193 ev_lp_cap = MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP); 194 ev_fcntl = MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL); 195 ev_speed = MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED); 196 } 197 198 /* 199 * Convert the LINKCHANGE speed enumeration into mbit/s, in the 200 * same way as GET_LINK encodes the speed 201 */ 202 switch (ev_speed) { 203 case MCDI_EVENT_LINKCHANGE_SPEED_100M: 204 speed = 100; 205 break; 206 case MCDI_EVENT_LINKCHANGE_SPEED_1G: 207 speed = 1000; 208 break; 209 case MCDI_EVENT_LINKCHANGE_SPEED_10G: 210 speed = 10000; 211 break; 212 case MCDI_EVENT_LINKCHANGE_SPEED_25G: 213 speed = 25000; 214 break; 215 case MCDI_EVENT_LINKCHANGE_SPEED_40G: 216 speed = 40000; 217 break; 218 case MCDI_EVENT_LINKCHANGE_SPEED_50G: 219 speed = 50000; 220 break; 221 case MCDI_EVENT_LINKCHANGE_SPEED_100G: 222 speed = 100000; 223 break; 224 default: 225 speed = 0; 226 break; 227 } 228 229 mcdi_phy_decode_link_mode(enp, link_flags, speed, ev_fcntl, 230 MC_CMD_FEC_NONE, &link_mode, 231 &fcntl, &fec); 232 mcdi_phy_decode_cap(ev_lp_cap, &lp_cap_mask); 233 234 /* 235 * It's safe to update ep_lp_cap_mask without the driver's port lock 236 * because presumably any concurrently running efx_port_poll() is 237 * only going to arrive at the same value. 238 * 239 * ep_fcntl has two meanings. It's either the link common fcntl 240 * (if the PHY supports AN), or it's the forced link state. If 241 * the former, it's safe to update the value for the same reason as 242 * for ep_lp_cap_mask. If the latter, then just ignore the value, 243 * because we can race with efx_mac_fcntl_set(). 244 */ 245 epp->ep_lp_cap_mask = lp_cap_mask; 246 epp->ep_fcntl = fcntl; 247 248 *link_modep = link_mode; 249 } 250 251 __checkReturn efx_rc_t 252 ef10_phy_power( 253 __in efx_nic_t *enp, 254 __in boolean_t power) 255 { 256 efx_rc_t rc; 257 258 if (!power) 259 return (0); 260 261 /* Check if the PHY is a zombie */ 262 if ((rc = ef10_phy_verify(enp)) != 0) 263 goto fail1; 264 265 enp->en_reset_flags |= EFX_RESET_PHY; 266 267 return (0); 268 269 fail1: 270 EFSYS_PROBE1(fail1, efx_rc_t, rc); 271 272 return (rc); 273 } 274 275 __checkReturn efx_rc_t 276 ef10_phy_get_link( 277 __in efx_nic_t *enp, 278 __out ef10_link_state_t *elsp) 279 { 280 efx_mcdi_req_t req; 281 uint32_t fec; 282 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN, 283 MC_CMD_GET_LINK_OUT_V2_LEN); 284 efx_rc_t rc; 285 286 req.emr_cmd = MC_CMD_GET_LINK; 287 req.emr_in_buf = payload; 288 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; 289 req.emr_out_buf = payload; 290 req.emr_out_length = MC_CMD_GET_LINK_OUT_V2_LEN; 291 292 efx_mcdi_execute(enp, &req); 293 294 if (req.emr_rc != 0) { 295 rc = req.emr_rc; 296 goto fail1; 297 } 298 299 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { 300 rc = EMSGSIZE; 301 goto fail2; 302 } 303 304 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), 305 &elsp->epls.epls_adv_cap_mask); 306 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), 307 &elsp->epls.epls_lp_cap_mask); 308 309 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN) 310 fec = MC_CMD_FEC_NONE; 311 else 312 fec = MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_FEC_TYPE); 313 314 mcdi_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), 315 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), 316 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), 317 fec, &elsp->epls.epls_link_mode, 318 &elsp->epls.epls_fcntl, &elsp->epls.epls_fec); 319 320 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN) { 321 elsp->epls.epls_ld_cap_mask = 0; 322 } else { 323 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_LD_CAP), 324 &elsp->epls.epls_ld_cap_mask); 325 } 326 327 328 #if EFSYS_OPT_LOOPBACK 329 /* 330 * MC_CMD_LOOPBACK and EFX_LOOPBACK names are equivalent, so use the 331 * MCDI value directly. Agreement is checked in efx_loopback_mask(). 332 */ 333 elsp->els_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); 334 #endif /* EFSYS_OPT_LOOPBACK */ 335 336 elsp->els_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; 337 338 return (0); 339 340 fail2: 341 EFSYS_PROBE(fail2); 342 fail1: 343 EFSYS_PROBE1(fail1, efx_rc_t, rc); 344 345 return (rc); 346 } 347 348 static __checkReturn efx_rc_t 349 efx_mcdi_phy_set_link( 350 __in efx_nic_t *enp, 351 __in uint32_t cap_mask, 352 __in efx_loopback_type_t loopback_type, 353 __in efx_link_mode_t loopback_link_mode, 354 __in uint32_t phy_flags) 355 { 356 efx_mcdi_req_t req; 357 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_LINK_IN_LEN, 358 MC_CMD_SET_LINK_OUT_LEN); 359 unsigned int speed; 360 efx_rc_t rc; 361 362 req.emr_cmd = MC_CMD_SET_LINK; 363 req.emr_in_buf = payload; 364 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; 365 req.emr_out_buf = payload; 366 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; 367 368 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, 369 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, 370 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, 371 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, 372 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, 373 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, 374 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, 375 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, 376 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, 377 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, 378 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); 379 /* Too many fields for for POPULATE macros, so insert this afterwards */ 380 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 381 PHY_CAP_25000FDX, (cap_mask >> EFX_PHY_CAP_25000FDX) & 0x1); 382 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 383 PHY_CAP_40000FDX, (cap_mask >> EFX_PHY_CAP_40000FDX) & 0x1); 384 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 385 PHY_CAP_50000FDX, (cap_mask >> EFX_PHY_CAP_50000FDX) & 0x1); 386 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 387 PHY_CAP_100000FDX, (cap_mask >> EFX_PHY_CAP_100000FDX) & 0x1); 388 389 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 390 PHY_CAP_BASER_FEC, (cap_mask >> EFX_PHY_CAP_BASER_FEC) & 0x1); 391 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 392 PHY_CAP_BASER_FEC_REQUESTED, 393 (cap_mask >> EFX_PHY_CAP_BASER_FEC_REQUESTED) & 0x1); 394 395 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 396 PHY_CAP_RS_FEC, (cap_mask >> EFX_PHY_CAP_RS_FEC) & 0x1); 397 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 398 PHY_CAP_RS_FEC_REQUESTED, 399 (cap_mask >> EFX_PHY_CAP_RS_FEC_REQUESTED) & 0x1); 400 401 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 402 PHY_CAP_25G_BASER_FEC, 403 (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC) & 0x1); 404 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, 405 PHY_CAP_25G_BASER_FEC_REQUESTED, 406 (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) & 0x1); 407 408 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, loopback_type); 409 410 switch (loopback_link_mode) { 411 case EFX_LINK_100FDX: 412 speed = 100; 413 break; 414 case EFX_LINK_1000FDX: 415 speed = 1000; 416 break; 417 case EFX_LINK_10000FDX: 418 speed = 10000; 419 break; 420 case EFX_LINK_25000FDX: 421 speed = 25000; 422 break; 423 case EFX_LINK_40000FDX: 424 speed = 40000; 425 break; 426 case EFX_LINK_50000FDX: 427 speed = 50000; 428 break; 429 case EFX_LINK_100000FDX: 430 speed = 100000; 431 break; 432 default: 433 speed = 0; 434 break; 435 } 436 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); 437 438 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, phy_flags); 439 440 efx_mcdi_execute(enp, &req); 441 442 if (req.emr_rc != 0) { 443 rc = req.emr_rc; 444 goto fail1; 445 } 446 447 return (0); 448 449 fail1: 450 EFSYS_PROBE1(fail1, efx_rc_t, rc); 451 452 return (rc); 453 } 454 455 static __checkReturn efx_rc_t 456 efx_mcdi_phy_set_led( 457 __in efx_nic_t *enp, 458 __in efx_phy_led_mode_t phy_led_mode) 459 { 460 efx_mcdi_req_t req; 461 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_ID_LED_IN_LEN, 462 MC_CMD_SET_ID_LED_OUT_LEN); 463 unsigned int led_mode; 464 efx_rc_t rc; 465 466 req.emr_cmd = MC_CMD_SET_ID_LED; 467 req.emr_in_buf = payload; 468 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; 469 req.emr_out_buf = payload; 470 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; 471 472 switch (phy_led_mode) { 473 case EFX_PHY_LED_DEFAULT: 474 led_mode = MC_CMD_LED_DEFAULT; 475 break; 476 case EFX_PHY_LED_OFF: 477 led_mode = MC_CMD_LED_OFF; 478 break; 479 case EFX_PHY_LED_ON: 480 led_mode = MC_CMD_LED_ON; 481 break; 482 default: 483 EFSYS_ASSERT(0); 484 led_mode = MC_CMD_LED_DEFAULT; 485 break; 486 } 487 488 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); 489 490 efx_mcdi_execute(enp, &req); 491 492 if (req.emr_rc != 0) { 493 rc = req.emr_rc; 494 goto fail1; 495 } 496 497 return (0); 498 499 fail1: 500 EFSYS_PROBE1(fail1, efx_rc_t, rc); 501 502 return (rc); 503 } 504 505 __checkReturn efx_rc_t 506 ef10_phy_reconfigure( 507 __in efx_nic_t *enp) 508 { 509 efx_port_t *epp = &(enp->en_port); 510 efx_loopback_type_t loopback_type; 511 efx_link_mode_t loopback_link_mode; 512 uint32_t phy_flags; 513 efx_phy_led_mode_t phy_led_mode; 514 boolean_t supported; 515 efx_rc_t rc; 516 517 if ((rc = efx_mcdi_link_control_supported(enp, &supported)) != 0) 518 goto fail1; 519 if (supported == B_FALSE) 520 goto out; 521 522 #if EFSYS_OPT_LOOPBACK 523 loopback_type = epp->ep_loopback_type; 524 loopback_link_mode = epp->ep_loopback_link_mode; 525 #else 526 loopback_type = EFX_LOOPBACK_OFF; 527 loopback_link_mode = EFX_LINK_UNKNOWN; 528 #endif 529 #if EFSYS_OPT_PHY_FLAGS 530 phy_flags = epp->ep_phy_flags; 531 #else 532 phy_flags = 0; 533 #endif 534 535 rc = efx_mcdi_phy_set_link(enp, epp->ep_adv_cap_mask, 536 loopback_type, loopback_link_mode, phy_flags); 537 if (rc != 0) 538 goto fail2; 539 540 /* And set the blink mode */ 541 542 #if EFSYS_OPT_PHY_LED_CONTROL 543 phy_led_mode = epp->ep_phy_led_mode; 544 #else 545 phy_led_mode = EFX_PHY_LED_DEFAULT; 546 #endif 547 548 rc = efx_mcdi_phy_set_led(enp, phy_led_mode); 549 if (rc != 0) { 550 /* 551 * If LED control is not supported by firmware, we can 552 * silently ignore default mode set failure 553 * (see FWRIVERHD-198). 554 */ 555 if (rc == EOPNOTSUPP && phy_led_mode == EFX_PHY_LED_DEFAULT) 556 goto out; 557 goto fail3; 558 } 559 560 out: 561 return (0); 562 563 fail3: 564 EFSYS_PROBE(fail3); 565 fail2: 566 EFSYS_PROBE(fail2); 567 fail1: 568 EFSYS_PROBE1(fail1, efx_rc_t, rc); 569 570 return (rc); 571 } 572 573 __checkReturn efx_rc_t 574 ef10_phy_verify( 575 __in efx_nic_t *enp) 576 { 577 efx_mcdi_req_t req; 578 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_STATE_IN_LEN, 579 MC_CMD_GET_PHY_STATE_OUT_LEN); 580 uint32_t state; 581 efx_rc_t rc; 582 583 req.emr_cmd = MC_CMD_GET_PHY_STATE; 584 req.emr_in_buf = payload; 585 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; 586 req.emr_out_buf = payload; 587 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; 588 589 efx_mcdi_execute(enp, &req); 590 591 if (req.emr_rc != 0) { 592 rc = req.emr_rc; 593 goto fail1; 594 } 595 596 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { 597 rc = EMSGSIZE; 598 goto fail2; 599 } 600 601 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); 602 if (state != MC_CMD_PHY_STATE_OK) { 603 if (state != MC_CMD_PHY_STATE_ZOMBIE) 604 EFSYS_PROBE1(mc_pcol_error, int, state); 605 rc = ENOTACTIVE; 606 goto fail3; 607 } 608 609 return (0); 610 611 fail3: 612 EFSYS_PROBE(fail3); 613 fail2: 614 EFSYS_PROBE(fail2); 615 fail1: 616 EFSYS_PROBE1(fail1, efx_rc_t, rc); 617 618 return (rc); 619 } 620 621 __checkReturn efx_rc_t 622 ef10_phy_oui_get( 623 __in efx_nic_t *enp, 624 __out uint32_t *ouip) 625 { 626 _NOTE(ARGUNUSED(enp, ouip)) 627 628 return (ENOTSUP); 629 } 630 631 __checkReturn efx_rc_t 632 ef10_phy_link_state_get( 633 __in efx_nic_t *enp, 634 __out efx_phy_link_state_t *eplsp) 635 { 636 efx_rc_t rc; 637 ef10_link_state_t els; 638 639 /* Obtain the active link state */ 640 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 641 goto fail1; 642 643 *eplsp = els.epls; 644 645 return (0); 646 647 fail1: 648 EFSYS_PROBE1(fail1, efx_rc_t, rc); 649 650 return (rc); 651 } 652 653 654 #if EFSYS_OPT_PHY_STATS 655 656 __checkReturn efx_rc_t 657 ef10_phy_stats_update( 658 __in efx_nic_t *enp, 659 __in efsys_mem_t *esmp, 660 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) 661 { 662 /* TBD: no stats support in firmware yet */ 663 _NOTE(ARGUNUSED(enp, esmp)) 664 memset(stat, 0, EFX_PHY_NSTATS * sizeof (*stat)); 665 666 return (0); 667 } 668 669 #endif /* EFSYS_OPT_PHY_STATS */ 670 671 #if EFSYS_OPT_BIST 672 673 __checkReturn efx_rc_t 674 ef10_bist_enable_offline( 675 __in efx_nic_t *enp) 676 { 677 efx_rc_t rc; 678 679 if ((rc = efx_mcdi_bist_enable_offline(enp)) != 0) 680 goto fail1; 681 682 return (0); 683 684 fail1: 685 EFSYS_PROBE1(fail1, efx_rc_t, rc); 686 687 return (rc); 688 } 689 690 __checkReturn efx_rc_t 691 ef10_bist_start( 692 __in efx_nic_t *enp, 693 __in efx_bist_type_t type) 694 { 695 efx_rc_t rc; 696 697 if ((rc = efx_mcdi_bist_start(enp, type)) != 0) 698 goto fail1; 699 700 return (0); 701 702 fail1: 703 EFSYS_PROBE1(fail1, efx_rc_t, rc); 704 705 return (rc); 706 } 707 708 __checkReturn efx_rc_t 709 ef10_bist_poll( 710 __in efx_nic_t *enp, 711 __in efx_bist_type_t type, 712 __out efx_bist_result_t *resultp, 713 __out_opt __drv_when(count > 0, __notnull) 714 uint32_t *value_maskp, 715 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 716 unsigned long *valuesp, 717 __in size_t count) 718 { 719 /* 720 * MCDI_CTL_SDU_LEN_MAX_V1 is large enough cover all BIST results, 721 * whilst not wasting stack. 722 */ 723 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_POLL_BIST_IN_LEN, 724 MCDI_CTL_SDU_LEN_MAX_V1); 725 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 726 efx_mcdi_req_t req; 727 uint32_t value_mask = 0; 728 uint32_t result; 729 efx_rc_t rc; 730 731 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_LEN <= 732 MCDI_CTL_SDU_LEN_MAX_V1); 733 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_SFT9001_LEN <= 734 MCDI_CTL_SDU_LEN_MAX_V1); 735 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MRSFP_LEN <= 736 MCDI_CTL_SDU_LEN_MAX_V1); 737 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MEM_LEN <= 738 MCDI_CTL_SDU_LEN_MAX_V1); 739 740 _NOTE(ARGUNUSED(type)) 741 742 req.emr_cmd = MC_CMD_POLL_BIST; 743 req.emr_in_buf = payload; 744 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; 745 req.emr_out_buf = payload; 746 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX_V1; 747 748 efx_mcdi_execute(enp, &req); 749 750 if (req.emr_rc != 0) { 751 rc = req.emr_rc; 752 goto fail1; 753 } 754 755 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { 756 rc = EMSGSIZE; 757 goto fail2; 758 } 759 760 if (count > 0) 761 (void) memset(valuesp, '\0', count * sizeof (unsigned long)); 762 763 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); 764 765 if (result == MC_CMD_POLL_BIST_FAILED && 766 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MEM_LEN && 767 count > EFX_BIST_MEM_ECC_FATAL) { 768 if (valuesp != NULL) { 769 valuesp[EFX_BIST_MEM_TEST] = 770 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_TEST); 771 valuesp[EFX_BIST_MEM_ADDR] = 772 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ADDR); 773 valuesp[EFX_BIST_MEM_BUS] = 774 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_BUS); 775 valuesp[EFX_BIST_MEM_EXPECT] = 776 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_EXPECT); 777 valuesp[EFX_BIST_MEM_ACTUAL] = 778 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ACTUAL); 779 valuesp[EFX_BIST_MEM_ECC] = 780 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC); 781 valuesp[EFX_BIST_MEM_ECC_PARITY] = 782 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_PARITY); 783 valuesp[EFX_BIST_MEM_ECC_FATAL] = 784 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_FATAL); 785 } 786 value_mask |= (1 << EFX_BIST_MEM_TEST) | 787 (1 << EFX_BIST_MEM_ADDR) | 788 (1 << EFX_BIST_MEM_BUS) | 789 (1 << EFX_BIST_MEM_EXPECT) | 790 (1 << EFX_BIST_MEM_ACTUAL) | 791 (1 << EFX_BIST_MEM_ECC) | 792 (1 << EFX_BIST_MEM_ECC_PARITY) | 793 (1 << EFX_BIST_MEM_ECC_FATAL); 794 } else if (result == MC_CMD_POLL_BIST_FAILED && 795 encp->enc_phy_type == EFX_PHY_XFI_FARMI && 796 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && 797 count > EFX_BIST_FAULT_CODE) { 798 if (valuesp != NULL) 799 valuesp[EFX_BIST_FAULT_CODE] = 800 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); 801 value_mask |= 1 << EFX_BIST_FAULT_CODE; 802 } 803 804 if (value_maskp != NULL) 805 *value_maskp = value_mask; 806 807 EFSYS_ASSERT(resultp != NULL); 808 if (result == MC_CMD_POLL_BIST_RUNNING) 809 *resultp = EFX_BIST_RESULT_RUNNING; 810 else if (result == MC_CMD_POLL_BIST_PASSED) 811 *resultp = EFX_BIST_RESULT_PASSED; 812 else 813 *resultp = EFX_BIST_RESULT_FAILED; 814 815 return (0); 816 817 fail2: 818 EFSYS_PROBE(fail2); 819 fail1: 820 EFSYS_PROBE1(fail1, efx_rc_t, rc); 821 822 return (rc); 823 } 824 825 void 826 ef10_bist_stop( 827 __in efx_nic_t *enp, 828 __in efx_bist_type_t type) 829 { 830 /* There is no way to stop BIST on EF10. */ 831 _NOTE(ARGUNUSED(enp, type)) 832 } 833 834 #endif /* EFSYS_OPT_BIST */ 835 836 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 837