1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2012-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 #if EFSYS_OPT_MON_MCDI 10 #include "mcdi_mon.h" 11 #endif 12 13 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 14 15 #include "ef10_tlv_layout.h" 16 17 __checkReturn efx_rc_t 18 efx_mcdi_get_port_assignment( 19 __in efx_nic_t *enp, 20 __out uint32_t *portp) 21 { 22 efx_mcdi_req_t req; 23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN, 24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN); 25 efx_rc_t rc; 26 27 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 28 29 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT; 30 req.emr_in_buf = payload; 31 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN; 32 req.emr_out_buf = payload; 33 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN; 34 35 efx_mcdi_execute(enp, &req); 36 37 if (req.emr_rc != 0) { 38 rc = req.emr_rc; 39 goto fail1; 40 } 41 42 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) { 43 rc = EMSGSIZE; 44 goto fail2; 45 } 46 47 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT); 48 49 return (0); 50 51 fail2: 52 EFSYS_PROBE(fail2); 53 fail1: 54 EFSYS_PROBE1(fail1, efx_rc_t, rc); 55 56 return (rc); 57 } 58 59 __checkReturn efx_rc_t 60 efx_mcdi_get_port_modes( 61 __in efx_nic_t *enp, 62 __out uint32_t *modesp, 63 __out_opt uint32_t *current_modep, 64 __out_opt uint32_t *default_modep) 65 { 66 efx_mcdi_req_t req; 67 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN, 68 MC_CMD_GET_PORT_MODES_OUT_LEN); 69 efx_rc_t rc; 70 71 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 72 73 req.emr_cmd = MC_CMD_GET_PORT_MODES; 74 req.emr_in_buf = payload; 75 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN; 76 req.emr_out_buf = payload; 77 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN; 78 79 efx_mcdi_execute(enp, &req); 80 81 if (req.emr_rc != 0) { 82 rc = req.emr_rc; 83 goto fail1; 84 } 85 86 /* 87 * Require only Modes and DefaultMode fields, unless the current mode 88 * was requested (CurrentMode field was added for Medford). 89 */ 90 if (req.emr_out_length_used < 91 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) { 92 rc = EMSGSIZE; 93 goto fail2; 94 } 95 if ((current_modep != NULL) && (req.emr_out_length_used < 96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) { 97 rc = EMSGSIZE; 98 goto fail3; 99 } 100 101 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES); 102 103 if (current_modep != NULL) { 104 *current_modep = MCDI_OUT_DWORD(req, 105 GET_PORT_MODES_OUT_CURRENT_MODE); 106 } 107 108 if (default_modep != NULL) { 109 *default_modep = MCDI_OUT_DWORD(req, 110 GET_PORT_MODES_OUT_DEFAULT_MODE); 111 } 112 113 return (0); 114 115 fail3: 116 EFSYS_PROBE(fail3); 117 fail2: 118 EFSYS_PROBE(fail2); 119 fail1: 120 EFSYS_PROBE1(fail1, efx_rc_t, rc); 121 122 return (rc); 123 } 124 125 __checkReturn efx_rc_t 126 ef10_nic_get_port_mode_bandwidth( 127 __in efx_nic_t *enp, 128 __out uint32_t *bandwidth_mbpsp) 129 { 130 uint32_t port_modes; 131 uint32_t current_mode; 132 efx_port_t *epp = &(enp->en_port); 133 134 uint32_t single_lane; 135 uint32_t dual_lane; 136 uint32_t quad_lane; 137 uint32_t bandwidth; 138 efx_rc_t rc; 139 140 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, 141 ¤t_mode, NULL)) != 0) { 142 /* No port mode info available. */ 143 goto fail1; 144 } 145 146 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX)) 147 single_lane = 25000; 148 else 149 single_lane = 10000; 150 151 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX)) 152 dual_lane = 50000; 153 else 154 dual_lane = 20000; 155 156 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX)) 157 quad_lane = 100000; 158 else 159 quad_lane = 40000; 160 161 switch (current_mode) { 162 case TLV_PORT_MODE_1x1_NA: /* mode 0 */ 163 bandwidth = single_lane; 164 break; 165 case TLV_PORT_MODE_1x2_NA: /* mode 10 */ 166 case TLV_PORT_MODE_NA_1x2: /* mode 11 */ 167 bandwidth = dual_lane; 168 break; 169 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */ 170 bandwidth = single_lane + single_lane; 171 break; 172 case TLV_PORT_MODE_4x1_NA: /* mode 4 */ 173 case TLV_PORT_MODE_NA_4x1: /* mode 8 */ 174 bandwidth = 4 * single_lane; 175 break; 176 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */ 177 bandwidth = (2 * single_lane) + (2 * single_lane); 178 break; 179 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */ 180 bandwidth = dual_lane + dual_lane; 181 break; 182 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */ 183 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */ 184 bandwidth = dual_lane + (2 * single_lane); 185 break; 186 /* Legacy Medford-only mode. Do not use (see bug63270) */ 187 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */ 188 bandwidth = 4 * single_lane; 189 break; 190 case TLV_PORT_MODE_1x4_NA: /* mode 1 */ 191 case TLV_PORT_MODE_NA_1x4: /* mode 22 */ 192 bandwidth = quad_lane; 193 break; 194 case TLV_PORT_MODE_2x2_NA: /* mode 13 */ 195 case TLV_PORT_MODE_NA_2x2: /* mode 14 */ 196 bandwidth = 2 * dual_lane; 197 break; 198 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */ 199 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */ 200 bandwidth = quad_lane + (2 * single_lane); 201 break; 202 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */ 203 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */ 204 bandwidth = quad_lane + dual_lane; 205 break; 206 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */ 207 bandwidth = quad_lane + quad_lane; 208 break; 209 default: 210 rc = EINVAL; 211 goto fail2; 212 } 213 214 *bandwidth_mbpsp = bandwidth; 215 216 return (0); 217 218 fail2: 219 EFSYS_PROBE(fail2); 220 fail1: 221 EFSYS_PROBE1(fail1, efx_rc_t, rc); 222 223 return (rc); 224 } 225 226 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 227 228 #if EFX_OPTS_EF10() 229 230 __checkReturn efx_rc_t 231 efx_mcdi_vadaptor_alloc( 232 __in efx_nic_t *enp, 233 __in uint32_t port_id) 234 { 235 efx_mcdi_req_t req; 236 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN, 237 MC_CMD_VADAPTOR_ALLOC_OUT_LEN); 238 efx_rc_t rc; 239 240 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC; 241 req.emr_in_buf = payload; 242 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN; 243 req.emr_out_buf = payload; 244 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN; 245 246 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 247 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS, 248 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED, 249 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0); 250 251 efx_mcdi_execute(enp, &req); 252 253 if (req.emr_rc != 0) { 254 rc = req.emr_rc; 255 goto fail1; 256 } 257 258 return (0); 259 260 fail1: 261 EFSYS_PROBE1(fail1, efx_rc_t, rc); 262 263 return (rc); 264 } 265 266 __checkReturn efx_rc_t 267 efx_mcdi_vadaptor_free( 268 __in efx_nic_t *enp, 269 __in uint32_t port_id) 270 { 271 efx_mcdi_req_t req; 272 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN, 273 MC_CMD_VADAPTOR_FREE_OUT_LEN); 274 efx_rc_t rc; 275 276 req.emr_cmd = MC_CMD_VADAPTOR_FREE; 277 req.emr_in_buf = payload; 278 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN; 279 req.emr_out_buf = payload; 280 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN; 281 282 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 283 284 efx_mcdi_execute(enp, &req); 285 286 if (req.emr_rc != 0) { 287 rc = req.emr_rc; 288 goto fail1; 289 } 290 291 return (0); 292 293 fail1: 294 EFSYS_PROBE1(fail1, efx_rc_t, rc); 295 296 return (rc); 297 } 298 299 #endif /* EFX_OPTS_EF10() */ 300 301 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 302 303 __checkReturn efx_rc_t 304 efx_mcdi_get_mac_address_pf( 305 __in efx_nic_t *enp, 306 __out_ecount_opt(6) uint8_t mac_addrp[6]) 307 { 308 efx_mcdi_req_t req; 309 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN, 310 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 311 efx_rc_t rc; 312 313 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 314 315 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES; 316 req.emr_in_buf = payload; 317 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN; 318 req.emr_out_buf = payload; 319 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN; 320 321 efx_mcdi_execute(enp, &req); 322 323 if (req.emr_rc != 0) { 324 rc = req.emr_rc; 325 goto fail1; 326 } 327 328 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) { 329 rc = EMSGSIZE; 330 goto fail2; 331 } 332 333 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) { 334 rc = ENOENT; 335 goto fail3; 336 } 337 338 if (mac_addrp != NULL) { 339 uint8_t *addrp; 340 341 addrp = MCDI_OUT2(req, uint8_t, 342 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE); 343 344 EFX_MAC_ADDR_COPY(mac_addrp, addrp); 345 } 346 347 return (0); 348 349 fail3: 350 EFSYS_PROBE(fail3); 351 fail2: 352 EFSYS_PROBE(fail2); 353 fail1: 354 EFSYS_PROBE1(fail1, efx_rc_t, rc); 355 356 return (rc); 357 } 358 359 __checkReturn efx_rc_t 360 efx_mcdi_get_mac_address_vf( 361 __in efx_nic_t *enp, 362 __out_ecount_opt(6) uint8_t mac_addrp[6]) 363 { 364 efx_mcdi_req_t req; 365 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN, 366 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 367 efx_rc_t rc; 368 369 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 370 371 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES; 372 req.emr_in_buf = payload; 373 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN; 374 req.emr_out_buf = payload; 375 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX; 376 377 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 378 EVB_PORT_ID_ASSIGNED); 379 380 efx_mcdi_execute(enp, &req); 381 382 if (req.emr_rc != 0) { 383 rc = req.emr_rc; 384 goto fail1; 385 } 386 387 if (req.emr_out_length_used < 388 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) { 389 rc = EMSGSIZE; 390 goto fail2; 391 } 392 393 if (MCDI_OUT_DWORD(req, 394 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) { 395 rc = ENOENT; 396 goto fail3; 397 } 398 399 if (mac_addrp != NULL) { 400 uint8_t *addrp; 401 402 addrp = MCDI_OUT2(req, uint8_t, 403 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR); 404 405 EFX_MAC_ADDR_COPY(mac_addrp, addrp); 406 } 407 408 return (0); 409 410 fail3: 411 EFSYS_PROBE(fail3); 412 fail2: 413 EFSYS_PROBE(fail2); 414 fail1: 415 EFSYS_PROBE1(fail1, efx_rc_t, rc); 416 417 return (rc); 418 } 419 420 __checkReturn efx_rc_t 421 efx_mcdi_get_clock( 422 __in efx_nic_t *enp, 423 __out uint32_t *sys_freqp, 424 __out uint32_t *dpcpu_freqp) 425 { 426 efx_mcdi_req_t req; 427 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN, 428 MC_CMD_GET_CLOCK_OUT_LEN); 429 efx_rc_t rc; 430 431 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 432 433 req.emr_cmd = MC_CMD_GET_CLOCK; 434 req.emr_in_buf = payload; 435 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN; 436 req.emr_out_buf = payload; 437 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN; 438 439 efx_mcdi_execute(enp, &req); 440 441 if (req.emr_rc != 0) { 442 rc = req.emr_rc; 443 goto fail1; 444 } 445 446 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) { 447 rc = EMSGSIZE; 448 goto fail2; 449 } 450 451 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ); 452 if (*sys_freqp == 0) { 453 rc = EINVAL; 454 goto fail3; 455 } 456 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ); 457 if (*dpcpu_freqp == 0) { 458 rc = EINVAL; 459 goto fail4; 460 } 461 462 return (0); 463 464 fail4: 465 EFSYS_PROBE(fail4); 466 fail3: 467 EFSYS_PROBE(fail3); 468 fail2: 469 EFSYS_PROBE(fail2); 470 fail1: 471 EFSYS_PROBE1(fail1, efx_rc_t, rc); 472 473 return (rc); 474 } 475 476 __checkReturn efx_rc_t 477 efx_mcdi_get_rxdp_config( 478 __in efx_nic_t *enp, 479 __out uint32_t *end_paddingp) 480 { 481 efx_mcdi_req_t req; 482 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN, 483 MC_CMD_GET_RXDP_CONFIG_OUT_LEN); 484 uint32_t end_padding; 485 efx_rc_t rc; 486 487 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG; 488 req.emr_in_buf = payload; 489 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN; 490 req.emr_out_buf = payload; 491 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN; 492 493 efx_mcdi_execute(enp, &req); 494 495 if (req.emr_rc != 0) { 496 rc = req.emr_rc; 497 goto fail1; 498 } 499 500 if (req.emr_out_length_used < MC_CMD_GET_RXDP_CONFIG_OUT_LEN) { 501 rc = EMSGSIZE; 502 goto fail2; 503 } 504 505 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 506 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) { 507 /* RX DMA end padding is disabled */ 508 end_padding = 0; 509 } else { 510 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 511 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) { 512 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64: 513 end_padding = 64; 514 break; 515 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128: 516 end_padding = 128; 517 break; 518 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256: 519 end_padding = 256; 520 break; 521 default: 522 rc = ENOTSUP; 523 goto fail3; 524 } 525 } 526 527 *end_paddingp = end_padding; 528 529 return (0); 530 531 fail3: 532 EFSYS_PROBE(fail3); 533 fail2: 534 EFSYS_PROBE(fail2); 535 fail1: 536 EFSYS_PROBE1(fail1, efx_rc_t, rc); 537 538 return (rc); 539 } 540 541 __checkReturn efx_rc_t 542 efx_mcdi_get_vector_cfg( 543 __in efx_nic_t *enp, 544 __out_opt uint32_t *vec_basep, 545 __out_opt uint32_t *pf_nvecp, 546 __out_opt uint32_t *vf_nvecp) 547 { 548 efx_mcdi_req_t req; 549 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN, 550 MC_CMD_GET_VECTOR_CFG_OUT_LEN); 551 efx_rc_t rc; 552 553 req.emr_cmd = MC_CMD_GET_VECTOR_CFG; 554 req.emr_in_buf = payload; 555 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN; 556 req.emr_out_buf = payload; 557 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN; 558 559 efx_mcdi_execute(enp, &req); 560 561 if (req.emr_rc != 0) { 562 rc = req.emr_rc; 563 goto fail1; 564 } 565 566 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) { 567 rc = EMSGSIZE; 568 goto fail2; 569 } 570 571 if (vec_basep != NULL) 572 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE); 573 if (pf_nvecp != NULL) 574 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF); 575 if (vf_nvecp != NULL) 576 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF); 577 578 return (0); 579 580 fail2: 581 EFSYS_PROBE(fail2); 582 fail1: 583 EFSYS_PROBE1(fail1, efx_rc_t, rc); 584 585 return (rc); 586 } 587 588 __checkReturn efx_rc_t 589 efx_mcdi_alloc_vis( 590 __in efx_nic_t *enp, 591 __in uint32_t min_vi_count, 592 __in uint32_t max_vi_count, 593 __out uint32_t *vi_basep, 594 __out uint32_t *vi_countp, 595 __out uint32_t *vi_shiftp) 596 { 597 efx_mcdi_req_t req; 598 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN, 599 MC_CMD_ALLOC_VIS_EXT_OUT_LEN); 600 efx_rc_t rc; 601 602 if (vi_countp == NULL) { 603 rc = EINVAL; 604 goto fail1; 605 } 606 607 req.emr_cmd = MC_CMD_ALLOC_VIS; 608 req.emr_in_buf = payload; 609 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN; 610 req.emr_out_buf = payload; 611 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN; 612 613 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count); 614 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count); 615 616 efx_mcdi_execute(enp, &req); 617 618 if (req.emr_rc != 0) { 619 rc = req.emr_rc; 620 goto fail2; 621 } 622 623 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) { 624 rc = EMSGSIZE; 625 goto fail3; 626 } 627 628 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE); 629 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT); 630 631 /* Report VI_SHIFT if available (always zero for Huntington) */ 632 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN) 633 *vi_shiftp = 0; 634 else 635 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT); 636 637 return (0); 638 639 fail3: 640 EFSYS_PROBE(fail3); 641 fail2: 642 EFSYS_PROBE(fail2); 643 fail1: 644 EFSYS_PROBE1(fail1, efx_rc_t, rc); 645 646 return (rc); 647 } 648 649 650 __checkReturn efx_rc_t 651 efx_mcdi_free_vis( 652 __in efx_nic_t *enp) 653 { 654 efx_mcdi_req_t req; 655 efx_rc_t rc; 656 657 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0); 658 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0); 659 660 req.emr_cmd = MC_CMD_FREE_VIS; 661 req.emr_in_buf = NULL; 662 req.emr_in_length = 0; 663 req.emr_out_buf = NULL; 664 req.emr_out_length = 0; 665 666 efx_mcdi_execute_quiet(enp, &req); 667 668 /* Ignore ELREADY (no allocated VIs, so nothing to free) */ 669 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) { 670 rc = req.emr_rc; 671 goto fail1; 672 } 673 674 return (0); 675 676 fail1: 677 EFSYS_PROBE1(fail1, efx_rc_t, rc); 678 679 return (rc); 680 } 681 682 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 683 684 #if EFX_OPTS_EF10() 685 686 static __checkReturn efx_rc_t 687 efx_mcdi_alloc_piobuf( 688 __in efx_nic_t *enp, 689 __out efx_piobuf_handle_t *handlep) 690 { 691 efx_mcdi_req_t req; 692 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN, 693 MC_CMD_ALLOC_PIOBUF_OUT_LEN); 694 efx_rc_t rc; 695 696 if (handlep == NULL) { 697 rc = EINVAL; 698 goto fail1; 699 } 700 701 req.emr_cmd = MC_CMD_ALLOC_PIOBUF; 702 req.emr_in_buf = payload; 703 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN; 704 req.emr_out_buf = payload; 705 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN; 706 707 efx_mcdi_execute_quiet(enp, &req); 708 709 if (req.emr_rc != 0) { 710 rc = req.emr_rc; 711 goto fail2; 712 } 713 714 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 715 rc = EMSGSIZE; 716 goto fail3; 717 } 718 719 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 720 721 return (0); 722 723 fail3: 724 EFSYS_PROBE(fail3); 725 fail2: 726 EFSYS_PROBE(fail2); 727 fail1: 728 EFSYS_PROBE1(fail1, efx_rc_t, rc); 729 730 return (rc); 731 } 732 733 static __checkReturn efx_rc_t 734 efx_mcdi_free_piobuf( 735 __in efx_nic_t *enp, 736 __in efx_piobuf_handle_t handle) 737 { 738 efx_mcdi_req_t req; 739 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN, 740 MC_CMD_FREE_PIOBUF_OUT_LEN); 741 efx_rc_t rc; 742 743 req.emr_cmd = MC_CMD_FREE_PIOBUF; 744 req.emr_in_buf = payload; 745 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN; 746 req.emr_out_buf = payload; 747 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN; 748 749 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle); 750 751 efx_mcdi_execute_quiet(enp, &req); 752 753 if (req.emr_rc != 0) { 754 rc = req.emr_rc; 755 goto fail1; 756 } 757 758 return (0); 759 760 fail1: 761 EFSYS_PROBE1(fail1, efx_rc_t, rc); 762 763 return (rc); 764 } 765 766 static __checkReturn efx_rc_t 767 efx_mcdi_link_piobuf( 768 __in efx_nic_t *enp, 769 __in uint32_t vi_index, 770 __in efx_piobuf_handle_t handle) 771 { 772 efx_mcdi_req_t req; 773 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN, 774 MC_CMD_LINK_PIOBUF_OUT_LEN); 775 efx_rc_t rc; 776 777 req.emr_cmd = MC_CMD_LINK_PIOBUF; 778 req.emr_in_buf = payload; 779 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN; 780 req.emr_out_buf = payload; 781 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN; 782 783 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle); 784 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index); 785 786 efx_mcdi_execute(enp, &req); 787 788 if (req.emr_rc != 0) { 789 rc = req.emr_rc; 790 goto fail1; 791 } 792 793 return (0); 794 795 fail1: 796 EFSYS_PROBE1(fail1, efx_rc_t, rc); 797 798 return (rc); 799 } 800 801 static __checkReturn efx_rc_t 802 efx_mcdi_unlink_piobuf( 803 __in efx_nic_t *enp, 804 __in uint32_t vi_index) 805 { 806 efx_mcdi_req_t req; 807 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN, 808 MC_CMD_UNLINK_PIOBUF_OUT_LEN); 809 efx_rc_t rc; 810 811 req.emr_cmd = MC_CMD_UNLINK_PIOBUF; 812 req.emr_in_buf = payload; 813 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN; 814 req.emr_out_buf = payload; 815 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN; 816 817 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index); 818 819 efx_mcdi_execute_quiet(enp, &req); 820 821 if (req.emr_rc != 0) { 822 rc = req.emr_rc; 823 goto fail1; 824 } 825 826 return (0); 827 828 fail1: 829 EFSYS_PROBE1(fail1, efx_rc_t, rc); 830 831 return (rc); 832 } 833 834 static void 835 ef10_nic_alloc_piobufs( 836 __in efx_nic_t *enp, 837 __in uint32_t max_piobuf_count) 838 { 839 efx_piobuf_handle_t *handlep; 840 unsigned int i; 841 842 EFSYS_ASSERT3U(max_piobuf_count, <=, 843 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle)); 844 845 enp->en_arch.ef10.ena_piobuf_count = 0; 846 847 for (i = 0; i < max_piobuf_count; i++) { 848 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; 849 850 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0) 851 goto fail1; 852 853 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0; 854 enp->en_arch.ef10.ena_piobuf_count++; 855 } 856 857 return; 858 859 fail1: 860 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 861 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; 862 863 (void) efx_mcdi_free_piobuf(enp, *handlep); 864 *handlep = EFX_PIOBUF_HANDLE_INVALID; 865 } 866 enp->en_arch.ef10.ena_piobuf_count = 0; 867 } 868 869 870 static void 871 ef10_nic_free_piobufs( 872 __in efx_nic_t *enp) 873 { 874 efx_piobuf_handle_t *handlep; 875 unsigned int i; 876 877 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 878 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; 879 880 (void) efx_mcdi_free_piobuf(enp, *handlep); 881 *handlep = EFX_PIOBUF_HANDLE_INVALID; 882 } 883 enp->en_arch.ef10.ena_piobuf_count = 0; 884 } 885 886 /* Sub-allocate a block from a piobuf */ 887 __checkReturn efx_rc_t 888 ef10_nic_pio_alloc( 889 __inout efx_nic_t *enp, 890 __out uint32_t *bufnump, 891 __out efx_piobuf_handle_t *handlep, 892 __out uint32_t *blknump, 893 __out uint32_t *offsetp, 894 __out size_t *sizep) 895 { 896 efx_nic_cfg_t *encp = &enp->en_nic_cfg; 897 efx_drv_cfg_t *edcp = &enp->en_drv_cfg; 898 uint32_t blk_per_buf; 899 uint32_t buf, blk; 900 efx_rc_t rc; 901 902 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 903 EFSYS_ASSERT(bufnump); 904 EFSYS_ASSERT(handlep); 905 EFSYS_ASSERT(blknump); 906 EFSYS_ASSERT(offsetp); 907 EFSYS_ASSERT(sizep); 908 909 if ((edcp->edc_pio_alloc_size == 0) || 910 (enp->en_arch.ef10.ena_piobuf_count == 0)) { 911 rc = ENOMEM; 912 goto fail1; 913 } 914 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size; 915 916 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) { 917 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf]; 918 919 if (~(*map) == 0) 920 continue; 921 922 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map))); 923 for (blk = 0; blk < blk_per_buf; blk++) { 924 if ((*map & (1u << blk)) == 0) { 925 *map |= (1u << blk); 926 goto done; 927 } 928 } 929 } 930 rc = ENOMEM; 931 goto fail2; 932 933 done: 934 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf]; 935 *bufnump = buf; 936 *blknump = blk; 937 *sizep = edcp->edc_pio_alloc_size; 938 *offsetp = blk * (*sizep); 939 940 return (0); 941 942 fail2: 943 EFSYS_PROBE(fail2); 944 fail1: 945 EFSYS_PROBE1(fail1, efx_rc_t, rc); 946 947 return (rc); 948 } 949 950 /* Free a piobuf sub-allocated block */ 951 __checkReturn efx_rc_t 952 ef10_nic_pio_free( 953 __inout efx_nic_t *enp, 954 __in uint32_t bufnum, 955 __in uint32_t blknum) 956 { 957 uint32_t *map; 958 efx_rc_t rc; 959 960 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) || 961 (blknum >= (8 * sizeof (*map)))) { 962 rc = EINVAL; 963 goto fail1; 964 } 965 966 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum]; 967 if ((*map & (1u << blknum)) == 0) { 968 rc = ENOENT; 969 goto fail2; 970 } 971 *map &= ~(1u << blknum); 972 973 return (0); 974 975 fail2: 976 EFSYS_PROBE(fail2); 977 fail1: 978 EFSYS_PROBE1(fail1, efx_rc_t, rc); 979 980 return (rc); 981 } 982 983 __checkReturn efx_rc_t 984 ef10_nic_pio_link( 985 __inout efx_nic_t *enp, 986 __in uint32_t vi_index, 987 __in efx_piobuf_handle_t handle) 988 { 989 return (efx_mcdi_link_piobuf(enp, vi_index, handle)); 990 } 991 992 __checkReturn efx_rc_t 993 ef10_nic_pio_unlink( 994 __inout efx_nic_t *enp, 995 __in uint32_t vi_index) 996 { 997 return (efx_mcdi_unlink_piobuf(enp, vi_index)); 998 } 999 1000 #endif /* EFX_OPTS_EF10() */ 1001 1002 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1003 1004 static __checkReturn efx_rc_t 1005 ef10_mcdi_get_pf_count( 1006 __in efx_nic_t *enp, 1007 __out uint32_t *pf_countp) 1008 { 1009 efx_mcdi_req_t req; 1010 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN, 1011 MC_CMD_GET_PF_COUNT_OUT_LEN); 1012 efx_rc_t rc; 1013 1014 req.emr_cmd = MC_CMD_GET_PF_COUNT; 1015 req.emr_in_buf = payload; 1016 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN; 1017 req.emr_out_buf = payload; 1018 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN; 1019 1020 efx_mcdi_execute(enp, &req); 1021 1022 if (req.emr_rc != 0) { 1023 rc = req.emr_rc; 1024 goto fail1; 1025 } 1026 1027 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) { 1028 rc = EMSGSIZE; 1029 goto fail2; 1030 } 1031 1032 *pf_countp = *MCDI_OUT(req, uint8_t, 1033 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST); 1034 1035 EFSYS_ASSERT(*pf_countp != 0); 1036 1037 return (0); 1038 1039 fail2: 1040 EFSYS_PROBE(fail2); 1041 fail1: 1042 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1043 1044 return (rc); 1045 } 1046 1047 static __checkReturn efx_rc_t 1048 ef10_get_datapath_caps( 1049 __in efx_nic_t *enp) 1050 { 1051 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1052 efx_mcdi_req_t req; 1053 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN, 1054 MC_CMD_GET_CAPABILITIES_V9_OUT_LEN); 1055 efx_rc_t rc; 1056 1057 req.emr_cmd = MC_CMD_GET_CAPABILITIES; 1058 req.emr_in_buf = payload; 1059 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; 1060 req.emr_out_buf = payload; 1061 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V9_OUT_LEN; 1062 1063 efx_mcdi_execute_quiet(enp, &req); 1064 1065 if (req.emr_rc != 0) { 1066 rc = req.emr_rc; 1067 goto fail1; 1068 } 1069 1070 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 1071 rc = EMSGSIZE; 1072 goto fail2; 1073 } 1074 1075 #define CAP_FLAGS1(_req, _flag) \ 1076 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \ 1077 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))) 1078 1079 #define CAP_FLAGS2(_req, _flag) \ 1080 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \ 1081 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \ 1082 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))) 1083 1084 #define CAP_FLAGS3(_req, _flag) \ 1085 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) && \ 1086 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V7_OUT_FLAGS3) & \ 1087 (1u << (MC_CMD_GET_CAPABILITIES_V7_OUT_ ## _flag ## _LBN)))) 1088 1089 /* Check if RXDP firmware inserts 14 byte prefix */ 1090 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14)) 1091 encp->enc_rx_prefix_size = 14; 1092 else 1093 encp->enc_rx_prefix_size = 0; 1094 1095 #if EFSYS_OPT_RX_SCALE 1096 /* Check if the firmware supports additional RSS modes */ 1097 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES)) 1098 encp->enc_rx_scale_additional_modes_supported = B_TRUE; 1099 else 1100 encp->enc_rx_scale_additional_modes_supported = B_FALSE; 1101 #endif /* EFSYS_OPT_RX_SCALE */ 1102 1103 /* Check if the firmware supports TSO */ 1104 if (CAP_FLAGS1(req, TX_TSO)) 1105 encp->enc_fw_assisted_tso_enabled = B_TRUE; 1106 else 1107 encp->enc_fw_assisted_tso_enabled = B_FALSE; 1108 1109 /* Check if the firmware supports FATSOv2 */ 1110 if (CAP_FLAGS2(req, TX_TSO_V2)) { 1111 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE; 1112 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req, 1113 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS); 1114 } else { 1115 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE; 1116 encp->enc_fw_assisted_tso_v2_n_contexts = 0; 1117 } 1118 1119 /* Check if the firmware supports FATSOv2 encap */ 1120 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP)) 1121 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE; 1122 else 1123 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE; 1124 1125 /* Check if TSOv3 is supported */ 1126 if (CAP_FLAGS2(req, TX_TSO_V3)) 1127 encp->enc_tso_v3_enabled = B_TRUE; 1128 else 1129 encp->enc_tso_v3_enabled = B_FALSE; 1130 1131 /* Check if the firmware has vadapter/vport/vswitch support */ 1132 if (CAP_FLAGS1(req, EVB)) 1133 encp->enc_datapath_cap_evb = B_TRUE; 1134 else 1135 encp->enc_datapath_cap_evb = B_FALSE; 1136 1137 /* Check if the firmware supports vport reconfiguration */ 1138 if (CAP_FLAGS1(req, VPORT_RECONFIGURE)) 1139 encp->enc_vport_reconfigure_supported = B_TRUE; 1140 else 1141 encp->enc_vport_reconfigure_supported = B_FALSE; 1142 1143 /* Check if the firmware supports VLAN insertion */ 1144 if (CAP_FLAGS1(req, TX_VLAN_INSERTION)) 1145 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE; 1146 else 1147 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE; 1148 1149 /* Check if the firmware supports RX event batching */ 1150 if (CAP_FLAGS1(req, RX_BATCHING)) 1151 encp->enc_rx_batching_enabled = B_TRUE; 1152 else 1153 encp->enc_rx_batching_enabled = B_FALSE; 1154 1155 /* 1156 * Even if batching isn't reported as supported, we may still get 1157 * batched events (see bug61153). 1158 */ 1159 encp->enc_rx_batch_max = 16; 1160 1161 /* Check if the firmware supports disabling scatter on RXQs */ 1162 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER)) 1163 encp->enc_rx_disable_scatter_supported = B_TRUE; 1164 else 1165 encp->enc_rx_disable_scatter_supported = B_FALSE; 1166 1167 /* No limit on maximum number of Rx scatter elements per packet. */ 1168 encp->enc_rx_scatter_max = -1; 1169 1170 /* Check if the firmware supports packed stream mode */ 1171 if (CAP_FLAGS1(req, RX_PACKED_STREAM)) 1172 encp->enc_rx_packed_stream_supported = B_TRUE; 1173 else 1174 encp->enc_rx_packed_stream_supported = B_FALSE; 1175 1176 /* 1177 * Check if the firmware supports configurable buffer sizes 1178 * for packed stream mode (otherwise buffer size is 1Mbyte) 1179 */ 1180 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS)) 1181 encp->enc_rx_var_packed_stream_supported = B_TRUE; 1182 else 1183 encp->enc_rx_var_packed_stream_supported = B_FALSE; 1184 1185 /* Check if the firmware supports equal stride super-buffer mode */ 1186 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER)) 1187 encp->enc_rx_es_super_buffer_supported = B_TRUE; 1188 else 1189 encp->enc_rx_es_super_buffer_supported = B_FALSE; 1190 1191 /* Check if the firmware supports FW subvariant w/o Tx checksumming */ 1192 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM)) 1193 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE; 1194 else 1195 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE; 1196 1197 /* Check if the firmware supports set mac with running filters */ 1198 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED)) 1199 encp->enc_allow_set_mac_with_installed_filters = B_TRUE; 1200 else 1201 encp->enc_allow_set_mac_with_installed_filters = B_FALSE; 1202 1203 /* 1204 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows 1205 * specifying which parameters to configure. 1206 */ 1207 if (CAP_FLAGS1(req, SET_MAC_ENHANCED)) 1208 encp->enc_enhanced_set_mac_supported = B_TRUE; 1209 else 1210 encp->enc_enhanced_set_mac_supported = B_FALSE; 1211 1212 /* 1213 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows 1214 * us to let the firmware choose the settings to use on an EVQ. 1215 */ 1216 if (CAP_FLAGS2(req, INIT_EVQ_V2)) 1217 encp->enc_init_evq_v2_supported = B_TRUE; 1218 else 1219 encp->enc_init_evq_v2_supported = B_FALSE; 1220 1221 /* 1222 * Check if firmware supports extended width event queues, which have 1223 * a different event descriptor layout. 1224 */ 1225 if (CAP_FLAGS3(req, EXTENDED_WIDTH_EVQS_SUPPORTED)) 1226 encp->enc_init_evq_extended_width_supported = B_TRUE; 1227 else 1228 encp->enc_init_evq_extended_width_supported = B_FALSE; 1229 1230 /* 1231 * Check if the NO_CONT_EV mode for RX events is supported. 1232 */ 1233 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV)) 1234 encp->enc_no_cont_ev_mode_supported = B_TRUE; 1235 else 1236 encp->enc_no_cont_ev_mode_supported = B_FALSE; 1237 1238 /* 1239 * Check if buffer size may and must be specified on INIT_RXQ. 1240 * It may be always specified to efx_rx_qcreate(), but will be 1241 * just kept libefx internal if MCDI does not support it. 1242 */ 1243 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE)) 1244 encp->enc_init_rxq_with_buffer_size = B_TRUE; 1245 else 1246 encp->enc_init_rxq_with_buffer_size = B_FALSE; 1247 1248 /* 1249 * Check if firmware-verified NVRAM updates must be used. 1250 * 1251 * The firmware trusted installer requires all NVRAM updates to use 1252 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update) 1253 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated 1254 * partition and report the result). 1255 */ 1256 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT)) 1257 encp->enc_nvram_update_verify_result_supported = B_TRUE; 1258 else 1259 encp->enc_nvram_update_verify_result_supported = B_FALSE; 1260 1261 if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT)) 1262 encp->enc_nvram_update_poll_verify_result_supported = B_TRUE; 1263 else 1264 encp->enc_nvram_update_poll_verify_result_supported = B_FALSE; 1265 1266 /* 1267 * Check if firmware update via the BUNDLE partition is supported 1268 */ 1269 if (CAP_FLAGS2(req, BUNDLE_UPDATE)) 1270 encp->enc_nvram_bundle_update_supported = B_TRUE; 1271 else 1272 encp->enc_nvram_bundle_update_supported = B_FALSE; 1273 1274 /* 1275 * Check if firmware provides packet memory and Rx datapath 1276 * counters. 1277 */ 1278 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS)) 1279 encp->enc_pm_and_rxdp_counters = B_TRUE; 1280 else 1281 encp->enc_pm_and_rxdp_counters = B_FALSE; 1282 1283 /* 1284 * Check if the 40G MAC hardware is capable of reporting 1285 * statistics for Tx size bins. 1286 */ 1287 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS)) 1288 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE; 1289 else 1290 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE; 1291 1292 /* 1293 * Check if firmware supports VXLAN and NVGRE tunnels. 1294 * The capability indicates Geneve protocol support as well. 1295 */ 1296 if (CAP_FLAGS1(req, VXLAN_NVGRE)) { 1297 encp->enc_tunnel_encapsulations_supported = 1298 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) | 1299 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) | 1300 (1u << EFX_TUNNEL_PROTOCOL_NVGRE); 1301 1302 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES == 1303 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 1304 encp->enc_tunnel_config_udp_entries_max = 1305 EFX_TUNNEL_MAXNENTRIES; 1306 } else { 1307 encp->enc_tunnel_config_udp_entries_max = 0; 1308 } 1309 1310 /* 1311 * Check if firmware reports the VI window mode. 1312 * Medford2 has a variable VI window size (8K, 16K or 64K). 1313 * Medford and Huntington have a fixed 8K VI window size. 1314 */ 1315 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 1316 uint8_t mode = 1317 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 1318 1319 switch (mode) { 1320 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K: 1321 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; 1322 break; 1323 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K: 1324 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K; 1325 break; 1326 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K: 1327 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K; 1328 break; 1329 default: 1330 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; 1331 break; 1332 } 1333 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) || 1334 (enp->en_family == EFX_FAMILY_MEDFORD)) { 1335 /* Huntington and Medford have fixed 8K window size */ 1336 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; 1337 } else { 1338 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; 1339 } 1340 1341 /* Check if firmware supports extended MAC stats. */ 1342 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 1343 /* Extended stats buffer supported */ 1344 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req, 1345 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 1346 } else { 1347 /* Use Siena-compatible legacy MAC stats */ 1348 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS; 1349 } 1350 1351 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2) 1352 encp->enc_fec_counters = B_TRUE; 1353 else 1354 encp->enc_fec_counters = B_FALSE; 1355 1356 /* Check if the firmware provides head-of-line blocking counters */ 1357 if (CAP_FLAGS2(req, RXDP_HLB_IDLE)) 1358 encp->enc_hlb_counters = B_TRUE; 1359 else 1360 encp->enc_hlb_counters = B_FALSE; 1361 1362 #if EFSYS_OPT_RX_SCALE 1363 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) { 1364 /* Only one exclusive RSS context is available per port. */ 1365 encp->enc_rx_scale_max_exclusive_contexts = 1; 1366 1367 switch (enp->en_family) { 1368 case EFX_FAMILY_MEDFORD2: 1369 encp->enc_rx_scale_hash_alg_mask = 1370 (1U << EFX_RX_HASHALG_TOEPLITZ); 1371 break; 1372 1373 case EFX_FAMILY_MEDFORD: 1374 case EFX_FAMILY_HUNTINGTON: 1375 /* 1376 * Packed stream firmware variant maintains a 1377 * non-standard algorithm for hash computation. 1378 * It implies explicit XORing together 1379 * source + destination IP addresses (or last 1380 * four bytes in the case of IPv6) and using the 1381 * resulting value as the input to a Toeplitz hash. 1382 */ 1383 encp->enc_rx_scale_hash_alg_mask = 1384 (1U << EFX_RX_HASHALG_PACKED_STREAM); 1385 break; 1386 1387 default: 1388 rc = EINVAL; 1389 goto fail3; 1390 } 1391 1392 /* Port numbers cannot contribute to the hash value */ 1393 encp->enc_rx_scale_l4_hash_supported = B_FALSE; 1394 } else { 1395 /* 1396 * Maximum number of exclusive RSS contexts. 1397 * EF10 hardware supports 64 in total, but 6 are reserved 1398 * for shared contexts. They are a global resource so 1399 * not all may be available. 1400 */ 1401 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6; 1402 1403 encp->enc_rx_scale_hash_alg_mask = 1404 (1U << EFX_RX_HASHALG_TOEPLITZ); 1405 1406 /* 1407 * It is possible to use port numbers as 1408 * the input data for hash computation. 1409 */ 1410 encp->enc_rx_scale_l4_hash_supported = B_TRUE; 1411 } 1412 1413 if (CAP_FLAGS3(req, RSS_SELECTABLE_TABLE_SIZE)) 1414 encp->enc_rx_scale_tbl_entry_count_is_selectable = B_TRUE; 1415 else 1416 encp->enc_rx_scale_tbl_entry_count_is_selectable = B_FALSE; 1417 #endif /* EFSYS_OPT_RX_SCALE */ 1418 1419 /* Check if the firmware supports "FLAG" and "MARK" filter actions */ 1420 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG)) 1421 encp->enc_filter_action_flag_supported = B_TRUE; 1422 else 1423 encp->enc_filter_action_flag_supported = B_FALSE; 1424 1425 if (CAP_FLAGS2(req, FILTER_ACTION_MARK)) 1426 encp->enc_filter_action_mark_supported = B_TRUE; 1427 else 1428 encp->enc_filter_action_mark_supported = B_FALSE; 1429 1430 /* Get maximum supported value for "MARK" filter action */ 1431 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN) 1432 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req, 1433 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX); 1434 else 1435 encp->enc_filter_action_mark_max = 0; 1436 1437 #if EFSYS_OPT_MAE 1438 /* 1439 * Check support for EF100 Match Action Engine (MAE). 1440 * MAE hardware is present on Riverhead boards (from R2), 1441 * and on Keystone, and requires support in firmware. 1442 * 1443 * MAE control operations require MAE control privilege, 1444 * which is not available for VFs. 1445 * 1446 * Privileges can change dynamically at runtime: we assume 1447 * MAE support requires the privilege is granted initially, 1448 * and ignore later dynamic changes. 1449 */ 1450 if (CAP_FLAGS3(req, MAE_SUPPORTED)) { 1451 encp->enc_mae_supported = B_TRUE; 1452 if (EFX_MCDI_HAVE_PRIVILEGE(encp->enc_privilege_mask, MAE)) 1453 encp->enc_mae_admin = B_TRUE; 1454 else 1455 encp->enc_mae_admin = B_FALSE; 1456 } else { 1457 encp->enc_mae_supported = B_FALSE; 1458 encp->enc_mae_admin = B_FALSE; 1459 } 1460 1461 /* 1462 * Check support for MAE action set v2 features. 1463 * These provide support for packet edits. 1464 */ 1465 if (CAP_FLAGS3(req, MAE_ACTION_SET_ALLOC_V2_SUPPORTED)) 1466 encp->enc_mae_aset_v2_supported = B_TRUE; 1467 else 1468 encp->enc_mae_aset_v2_supported = B_FALSE; 1469 #else 1470 encp->enc_mae_supported = B_FALSE; 1471 encp->enc_mae_admin = B_FALSE; 1472 #endif /* EFSYS_OPT_MAE */ 1473 1474 #if EFSYS_OPT_RX_SCALE 1475 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V9_OUT_LEN) { 1476 encp->enc_rx_scale_indirection_max_nqueues = 1477 MCDI_OUT_DWORD(req, 1478 GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES); 1479 encp->enc_rx_scale_tbl_min_nentries = 1480 MCDI_OUT_DWORD(req, 1481 GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE); 1482 encp->enc_rx_scale_tbl_max_nentries = 1483 MCDI_OUT_DWORD(req, 1484 GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE); 1485 1486 if (CAP_FLAGS3(req, RSS_EVEN_SPREADING)) { 1487 #define RSS_MAX_EVEN_SPREADING_QUEUES \ 1488 GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES 1489 /* 1490 * The even spreading mode distributes traffic across 1491 * the specified number of queues without the need to 1492 * allocate precious indirection entry pool resources. 1493 */ 1494 encp->enc_rx_scale_even_spread_max_nqueues = 1495 MCDI_OUT_DWORD(req, RSS_MAX_EVEN_SPREADING_QUEUES); 1496 #undef RSS_MAX_EVEN_SPREADING_QUEUES 1497 } else { 1498 /* There is no support for the even spread contexts. */ 1499 encp->enc_rx_scale_even_spread_max_nqueues = 0; 1500 } 1501 } else { 1502 encp->enc_rx_scale_indirection_max_nqueues = EFX_MAXRSS; 1503 encp->enc_rx_scale_tbl_min_nentries = EFX_RSS_TBL_SIZE; 1504 encp->enc_rx_scale_tbl_max_nentries = EFX_RSS_TBL_SIZE; 1505 1506 /* 1507 * Assume that there is no support 1508 * for the even spread contexts. 1509 */ 1510 encp->enc_rx_scale_even_spread_max_nqueues = 0; 1511 } 1512 #endif /* EFSYS_OPT_RX_SCALE */ 1513 1514 #undef CAP_FLAGS1 1515 #undef CAP_FLAGS2 1516 #undef CAP_FLAGS3 1517 1518 return (0); 1519 1520 #if EFSYS_OPT_RX_SCALE 1521 fail3: 1522 EFSYS_PROBE(fail3); 1523 #endif /* EFSYS_OPT_RX_SCALE */ 1524 fail2: 1525 EFSYS_PROBE(fail2); 1526 fail1: 1527 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1528 1529 return (rc); 1530 } 1531 1532 1533 #define EF10_LEGACY_PF_PRIVILEGE_MASK \ 1534 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \ 1535 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \ 1536 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \ 1537 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \ 1538 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \ 1539 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \ 1540 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \ 1541 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \ 1542 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \ 1543 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \ 1544 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS) 1545 1546 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0 1547 1548 1549 __checkReturn efx_rc_t 1550 ef10_get_privilege_mask( 1551 __in efx_nic_t *enp, 1552 __out uint32_t *maskp) 1553 { 1554 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1555 uint32_t mask; 1556 efx_rc_t rc; 1557 1558 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf, 1559 &mask)) != 0) { 1560 if (rc != ENOTSUP) 1561 goto fail1; 1562 1563 /* Fallback for old firmware without privilege mask support */ 1564 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 1565 /* Assume PF has admin privilege */ 1566 mask = EF10_LEGACY_PF_PRIVILEGE_MASK; 1567 } else { 1568 /* VF is always unprivileged by default */ 1569 mask = EF10_LEGACY_VF_PRIVILEGE_MASK; 1570 } 1571 } 1572 1573 *maskp = mask; 1574 1575 return (0); 1576 1577 fail1: 1578 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1579 1580 return (rc); 1581 } 1582 1583 1584 #define EFX_EXT_PORT_MAX 4 1585 #define EFX_EXT_PORT_NA 0xFF 1586 1587 /* 1588 * Table of mapping schemes from port number to external number. 1589 * 1590 * Each port number ultimately corresponds to a connector: either as part of 1591 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on 1592 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T 1593 * "Salina"). In general: 1594 * 1595 * Port number (0-based) 1596 * | 1597 * port mapping (n:1) 1598 * | 1599 * v 1600 * External port number (1-based) 1601 * | 1602 * fixed (1:1) or cable assembly (1:m) 1603 * | 1604 * v 1605 * Connector 1606 * 1607 * The external numbering refers to the cages or magjacks on the board, 1608 * as visibly annotated on the board or back panel. This table describes 1609 * how to determine which external cage/magjack corresponds to the port 1610 * numbers used by the driver. 1611 * 1612 * The count of consecutive port numbers that map to each external number, 1613 * is determined by the chip family and the current port mode. 1614 * 1615 * For the Huntington family, the current port mode cannot be discovered, 1616 * but a single mapping is used by all modes for a given chip variant, 1617 * so the mapping used is instead the last match in the table to the full 1618 * set of port modes to which the NIC can be configured. Therefore the 1619 * ordering of entries in the mapping table is significant. 1620 */ 1621 static struct ef10_external_port_map_s { 1622 efx_family_t family; 1623 uint32_t modes_mask; 1624 uint8_t base_port[EFX_EXT_PORT_MAX]; 1625 } __ef10_external_port_mappings[] = { 1626 /* 1627 * Modes used by Huntington family controllers where each port 1628 * number maps to a separate cage. 1629 * SFN7x22F (Torino): 1630 * port 0 -> cage 1 1631 * port 1 -> cage 2 1632 * SFN7xx4F (Pavia): 1633 * port 0 -> cage 1 1634 * port 1 -> cage 2 1635 * port 2 -> cage 3 1636 * port 3 -> cage 4 1637 */ 1638 { 1639 EFX_FAMILY_HUNTINGTON, 1640 (1U << TLV_PORT_MODE_10G) | /* mode 0 */ 1641 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */ 1642 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */ 1643 { 0, 1, 2, 3 } 1644 }, 1645 /* 1646 * Modes which for Huntington identify a chip variant where 2 1647 * adjacent port numbers map to each cage. 1648 * SFN7x42Q (Monza): 1649 * port 0 -> cage 1 1650 * port 1 -> cage 1 1651 * port 2 -> cage 2 1652 * port 3 -> cage 2 1653 */ 1654 { 1655 EFX_FAMILY_HUNTINGTON, 1656 (1U << TLV_PORT_MODE_40G) | /* mode 1 */ 1657 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */ 1658 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */ 1659 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */ 1660 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1661 }, 1662 /* 1663 * Modes that on Medford allocate each port number to a separate 1664 * cage. 1665 * port 0 -> cage 1 1666 * port 1 -> cage 2 1667 * port 2 -> cage 3 1668 * port 3 -> cage 4 1669 */ 1670 { 1671 EFX_FAMILY_MEDFORD, 1672 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ 1673 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ 1674 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */ 1675 { 0, 1, 2, 3 } 1676 }, 1677 /* 1678 * Modes that on Medford allocate 2 adjacent port numbers to each 1679 * cage. 1680 * port 0 -> cage 1 1681 * port 1 -> cage 1 1682 * port 2 -> cage 2 1683 * port 3 -> cage 2 1684 */ 1685 { 1686 EFX_FAMILY_MEDFORD, 1687 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */ 1688 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */ 1689 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */ 1690 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */ 1691 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */ 1692 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */ 1693 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1694 }, 1695 /* 1696 * Modes that on Medford allocate 4 adjacent port numbers to 1697 * cage 1. 1698 * port 0 -> cage 1 1699 * port 1 -> cage 1 1700 * port 2 -> cage 1 1701 * port 3 -> cage 1 1702 */ 1703 { 1704 EFX_FAMILY_MEDFORD, 1705 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */ 1706 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */ 1707 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1708 }, 1709 /* 1710 * Modes that on Medford allocate 4 adjacent port numbers to 1711 * cage 2. 1712 * port 0 -> cage 2 1713 * port 1 -> cage 2 1714 * port 2 -> cage 2 1715 * port 3 -> cage 2 1716 */ 1717 { 1718 EFX_FAMILY_MEDFORD, 1719 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */ 1720 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1721 }, 1722 /* 1723 * Modes that on Medford2 allocate each port number to a separate 1724 * cage. 1725 * port 0 -> cage 1 1726 * port 1 -> cage 2 1727 * port 2 -> cage 3 1728 * port 3 -> cage 4 1729 */ 1730 { 1731 EFX_FAMILY_MEDFORD2, 1732 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ 1733 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ 1734 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */ 1735 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */ 1736 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */ 1737 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */ 1738 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */ 1739 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */ 1740 { 0, 1, 2, 3 } 1741 }, 1742 /* 1743 * Modes that on Medford2 allocate 1 port to cage 1 and the rest 1744 * to cage 2. 1745 * port 0 -> cage 1 1746 * port 1 -> cage 2 1747 * port 2 -> cage 2 1748 */ 1749 { 1750 EFX_FAMILY_MEDFORD2, 1751 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */ 1752 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */ 1753 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1754 }, 1755 /* 1756 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1 1757 * and the rest to cage 2. 1758 * port 0 -> cage 1 1759 * port 1 -> cage 1 1760 * port 2 -> cage 2 1761 * port 3 -> cage 2 1762 */ 1763 { 1764 EFX_FAMILY_MEDFORD2, 1765 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */ 1766 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */ 1767 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */ 1768 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */ 1769 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1770 }, 1771 /* 1772 * Modes that on Medford2 allocate up to 4 adjacent port numbers 1773 * to cage 1. 1774 * port 0 -> cage 1 1775 * port 1 -> cage 1 1776 * port 2 -> cage 1 1777 * port 3 -> cage 1 1778 */ 1779 { 1780 EFX_FAMILY_MEDFORD2, 1781 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */ 1782 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1783 }, 1784 /* 1785 * Modes that on Medford2 allocate up to 4 adjacent port numbers 1786 * to cage 2. 1787 * port 0 -> cage 2 1788 * port 1 -> cage 2 1789 * port 2 -> cage 2 1790 * port 3 -> cage 2 1791 */ 1792 { 1793 EFX_FAMILY_MEDFORD2, 1794 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */ 1795 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */ 1796 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */ 1797 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1798 }, 1799 /* 1800 * Modes that on Riverhead allocate each port number to a separate 1801 * cage. 1802 * port 0 -> cage 1 1803 * port 1 -> cage 2 1804 */ 1805 { 1806 EFX_FAMILY_RIVERHEAD, 1807 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ 1808 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ 1809 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */ 1810 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1811 }, 1812 }; 1813 1814 static __checkReturn efx_rc_t 1815 ef10_external_port_mapping( 1816 __in efx_nic_t *enp, 1817 __in uint32_t port, 1818 __out uint8_t *external_portp) 1819 { 1820 efx_rc_t rc; 1821 int i; 1822 uint32_t port_modes; 1823 uint32_t matches; 1824 uint32_t current; 1825 struct ef10_external_port_map_s *mapp = NULL; 1826 int ext_index = port; /* Default 1-1 mapping */ 1827 1828 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t, 1829 NULL)) != 0) { 1830 /* 1831 * No current port mode information (i.e. Huntington) 1832 * - infer mapping from available modes 1833 */ 1834 if ((rc = efx_mcdi_get_port_modes(enp, 1835 &port_modes, NULL, NULL)) != 0) { 1836 /* 1837 * No port mode information available 1838 * - use default mapping 1839 */ 1840 goto out; 1841 } 1842 } else { 1843 /* Only need to scan the current mode */ 1844 port_modes = 1 << current; 1845 } 1846 1847 /* 1848 * Infer the internal port -> external number mapping from 1849 * the possible port modes for this NIC. 1850 */ 1851 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) { 1852 struct ef10_external_port_map_s *eepmp = 1853 &__ef10_external_port_mappings[i]; 1854 if (eepmp->family != enp->en_family) 1855 continue; 1856 matches = (eepmp->modes_mask & port_modes); 1857 if (matches != 0) { 1858 /* 1859 * Some modes match. For some Huntington boards 1860 * there will be multiple matches. The mapping on the 1861 * last match is used. 1862 */ 1863 mapp = eepmp; 1864 port_modes &= ~matches; 1865 } 1866 } 1867 1868 if (port_modes != 0) { 1869 /* Some advertised modes are not supported */ 1870 rc = ENOTSUP; 1871 goto fail1; 1872 } 1873 1874 out: 1875 if (mapp != NULL) { 1876 /* 1877 * External ports are assigned a sequence of consecutive 1878 * port numbers, so find the one with the closest base_port. 1879 */ 1880 uint32_t delta = EFX_EXT_PORT_NA; 1881 1882 for (i = 0; i < EFX_EXT_PORT_MAX; i++) { 1883 uint32_t base = mapp->base_port[i]; 1884 if ((base != EFX_EXT_PORT_NA) && (base <= port)) { 1885 if ((port - base) < delta) { 1886 delta = (port - base); 1887 ext_index = i; 1888 } 1889 } 1890 } 1891 } 1892 *external_portp = (uint8_t)(ext_index + 1); 1893 1894 return (0); 1895 1896 fail1: 1897 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1898 1899 return (rc); 1900 } 1901 1902 static __checkReturn efx_rc_t 1903 efx_mcdi_get_nic_addr_caps( 1904 __in efx_nic_t *enp) 1905 { 1906 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1907 uint32_t mapping_type; 1908 efx_rc_t rc; 1909 1910 rc = efx_mcdi_get_nic_addr_info(enp, &mapping_type); 1911 if (rc != 0) { 1912 if (rc == ENOTSUP) { 1913 encp->enc_dma_mapping = EFX_NIC_DMA_MAPPING_FLAT; 1914 goto out; 1915 } 1916 goto fail1; 1917 } 1918 1919 switch (mapping_type) { 1920 case MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT: 1921 encp->enc_dma_mapping = EFX_NIC_DMA_MAPPING_FLAT; 1922 break; 1923 case MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED: 1924 encp->enc_dma_mapping = EFX_NIC_DMA_MAPPING_REGIONED; 1925 rc = efx_mcdi_get_nic_addr_regions(enp, 1926 &enp->en_dma.end_u.endu_region_info); 1927 if (rc != 0) 1928 goto fail2; 1929 break; 1930 default: 1931 goto fail3; 1932 } 1933 1934 out: 1935 return (0); 1936 1937 fail3: 1938 EFSYS_PROBE(fail3); 1939 fail2: 1940 EFSYS_PROBE(fail2); 1941 fail1: 1942 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1943 1944 return (rc); 1945 } 1946 1947 __checkReturn efx_rc_t 1948 efx_mcdi_nic_board_cfg( 1949 __in efx_nic_t *enp) 1950 { 1951 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 1952 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1953 ef10_link_state_t els; 1954 efx_port_t *epp = &(enp->en_port); 1955 efx_pcie_interface_t intf; 1956 uint32_t board_type = 0; 1957 uint32_t base, nvec; 1958 uint32_t port; 1959 uint32_t mask; 1960 uint32_t pf; 1961 uint32_t vf; 1962 uint8_t mac_addr[6] = { 0 }; 1963 efx_rc_t rc; 1964 1965 /* Get the (zero-based) MCDI port number */ 1966 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) 1967 goto fail1; 1968 1969 /* EFX MCDI interface uses one-based port numbers */ 1970 emip->emi_port = port + 1; 1971 1972 encp->enc_assigned_port = port; 1973 1974 if ((rc = ef10_external_port_mapping(enp, port, 1975 &encp->enc_external_port)) != 0) 1976 goto fail2; 1977 1978 /* 1979 * Get PCIe function number from firmware (used for 1980 * per-function privilege and dynamic config info). 1981 * - PCIe PF: pf = PF number, vf = 0xffff. 1982 * - PCIe VF: pf = parent PF, vf = VF number. 1983 */ 1984 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf, &intf)) != 0) 1985 goto fail3; 1986 1987 encp->enc_pf = pf; 1988 encp->enc_vf = vf; 1989 encp->enc_intf = intf; 1990 1991 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0) 1992 goto fail4; 1993 1994 rc = efx_mcdi_client_mac_addr_get(enp, CLIENT_HANDLE_SELF, mac_addr); 1995 if ((rc != 0) && EFX_PCI_FUNCTION_IS_PF(encp)) { 1996 /* Fallback for legacy MAC address get approach (PF) */ 1997 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); 1998 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC 1999 /* 2000 * Disable static config checking, ONLY for manufacturing test 2001 * and setup at the factory, to allow the static config to be 2002 * installed. 2003 */ 2004 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 2005 if ((rc == 0) && (mac_addr[0] & 0x02)) { 2006 /* 2007 * If the static config does not include a global MAC 2008 * address pool then the board may return a locally 2009 * administered MAC address (this should only happen on 2010 * incorrectly programmed boards). 2011 */ 2012 rc = EINVAL; 2013 } 2014 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 2015 } else if (rc != 0) { 2016 /* Fallback for legacy MAC address get approach (VF) */ 2017 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); 2018 } 2019 2020 if (rc != 0) 2021 goto fail5; 2022 2023 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); 2024 2025 /* 2026 * Get the current privilege mask. Note that this may be modified 2027 * dynamically, so for most cases the value is informational only. 2028 * If the privilege being discovered can't be granted dynamically, 2029 * it's fine to rely on the value. In all other cases, DO NOT use 2030 * the privilege mask to check for sufficient privileges, as that 2031 * can result in time-of-check/time-of-use bugs. 2032 */ 2033 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) 2034 goto fail6; 2035 encp->enc_privilege_mask = mask; 2036 2037 /* Board configuration (legacy) */ 2038 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); 2039 if (rc != 0) { 2040 /* Unprivileged functions may not be able to read board cfg */ 2041 if (rc == EACCES) 2042 board_type = 0; 2043 else 2044 goto fail7; 2045 } 2046 2047 encp->enc_board_type = board_type; 2048 2049 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ 2050 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) 2051 goto fail8; 2052 2053 /* 2054 * Firmware with support for *_FEC capability bits does not 2055 * report that the corresponding *_FEC_REQUESTED bits are supported. 2056 * Add them here so that drivers understand that they are supported. 2057 */ 2058 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC)) 2059 epp->ep_phy_cap_mask |= 2060 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED); 2061 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC)) 2062 epp->ep_phy_cap_mask |= 2063 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED); 2064 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC)) 2065 epp->ep_phy_cap_mask |= 2066 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED); 2067 2068 /* Obtain the default PHY advertised capabilities */ 2069 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 2070 goto fail9; 2071 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask; 2072 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask; 2073 2074 /* Check capabilities of running datapath firmware */ 2075 if ((rc = ef10_get_datapath_caps(enp)) != 0) 2076 goto fail10; 2077 2078 /* Get interrupt vector limits */ 2079 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { 2080 if (EFX_PCI_FUNCTION_IS_PF(encp)) 2081 goto fail11; 2082 2083 /* Ignore error (cannot query vector limits from a VF). */ 2084 base = 0; 2085 nvec = 1024; 2086 } 2087 encp->enc_intr_vec_base = base; 2088 encp->enc_intr_limit = nvec; 2089 2090 rc = efx_mcdi_get_nic_addr_caps(enp); 2091 if (rc != 0) 2092 goto fail12; 2093 2094 return (0); 2095 2096 fail12: 2097 EFSYS_PROBE(fail12); 2098 fail11: 2099 EFSYS_PROBE(fail11); 2100 fail10: 2101 EFSYS_PROBE(fail10); 2102 fail9: 2103 EFSYS_PROBE(fail9); 2104 fail8: 2105 EFSYS_PROBE(fail8); 2106 fail7: 2107 EFSYS_PROBE(fail7); 2108 fail6: 2109 EFSYS_PROBE(fail6); 2110 fail5: 2111 EFSYS_PROBE(fail5); 2112 fail4: 2113 EFSYS_PROBE(fail4); 2114 fail3: 2115 EFSYS_PROBE(fail3); 2116 fail2: 2117 EFSYS_PROBE(fail2); 2118 fail1: 2119 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2120 2121 return (rc); 2122 } 2123 2124 __checkReturn efx_rc_t 2125 efx_mcdi_entity_reset( 2126 __in efx_nic_t *enp) 2127 { 2128 efx_mcdi_req_t req; 2129 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN, 2130 MC_CMD_ENTITY_RESET_OUT_LEN); 2131 efx_rc_t rc; 2132 2133 req.emr_cmd = MC_CMD_ENTITY_RESET; 2134 req.emr_in_buf = payload; 2135 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN; 2136 req.emr_out_buf = payload; 2137 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN; 2138 2139 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG, 2140 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1); 2141 2142 efx_mcdi_execute(enp, &req); 2143 2144 if (req.emr_rc != 0) { 2145 rc = req.emr_rc; 2146 goto fail1; 2147 } 2148 2149 return (0); 2150 2151 fail1: 2152 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2153 2154 return (rc); 2155 } 2156 2157 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 2158 2159 #if EFX_OPTS_EF10() 2160 2161 static __checkReturn efx_rc_t 2162 ef10_set_workaround_bug26807( 2163 __in efx_nic_t *enp) 2164 { 2165 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2166 uint32_t flags; 2167 efx_rc_t rc; 2168 2169 /* 2170 * If the bug26807 workaround is enabled, then firmware has enabled 2171 * support for chained multicast filters. Firmware will reset (FLR) 2172 * functions which have filters in the hardware filter table when the 2173 * workaround is enabled/disabled. 2174 * 2175 * We must recheck if the workaround is enabled after inserting the 2176 * first hardware filter, in case it has been changed since this check. 2177 */ 2178 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807, 2179 B_TRUE, &flags); 2180 if (rc == 0) { 2181 encp->enc_bug26807_workaround = B_TRUE; 2182 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) { 2183 /* 2184 * Other functions had installed filters before the 2185 * workaround was enabled, and they have been reset 2186 * by firmware. 2187 */ 2188 EFSYS_PROBE(bug26807_workaround_flr_done); 2189 /* FIXME: bump MC warm boot count ? */ 2190 } 2191 } else if (rc == EACCES) { 2192 /* 2193 * Unprivileged functions cannot enable the workaround in older 2194 * firmware. 2195 */ 2196 encp->enc_bug26807_workaround = B_FALSE; 2197 } else if ((rc == ENOTSUP) || (rc == ENOENT)) { 2198 encp->enc_bug26807_workaround = B_FALSE; 2199 } else { 2200 goto fail1; 2201 } 2202 2203 return (0); 2204 2205 fail1: 2206 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2207 2208 return (rc); 2209 } 2210 2211 static __checkReturn efx_rc_t 2212 ef10_nic_board_cfg( 2213 __in efx_nic_t *enp) 2214 { 2215 const efx_nic_ops_t *enop = enp->en_enop; 2216 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2217 efx_rc_t rc; 2218 2219 if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0) 2220 goto fail1; 2221 2222 /* 2223 * Huntington RXDP firmware inserts a 0 or 14 byte prefix. 2224 * We only support the 14 byte prefix here. 2225 */ 2226 if (encp->enc_rx_prefix_size != 14) { 2227 rc = ENOTSUP; 2228 goto fail2; 2229 } 2230 2231 encp->enc_clk_mult = 1; /* not used for EF10 */ 2232 2233 /* Alignment for WPTR updates */ 2234 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; 2235 2236 encp->enc_rx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); 2237 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_TX_KER_BYTE_CNT); 2238 /* No boundary crossing limits */ 2239 encp->enc_tx_dma_desc_boundary = 0; 2240 2241 /* 2242 * Maximum number of bytes into the frame the TCP header can start for 2243 * firmware assisted TSO to work. 2244 */ 2245 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; 2246 2247 /* EF10 TSO engine demands that packet header be contiguous. */ 2248 encp->enc_tx_tso_max_header_ndescs = 1; 2249 2250 /* The overall TSO header length is not limited. */ 2251 encp->enc_tx_tso_max_header_length = UINT32_MAX; 2252 2253 /* 2254 * There are no specific limitations on the number of 2255 * TSO payload descriptors. 2256 */ 2257 encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX; 2258 2259 /* TSO superframe payload length is not limited. */ 2260 encp->enc_tx_tso_max_payload_length = UINT32_MAX; 2261 2262 /* 2263 * Limitation on the maximum number of outgoing packets per 2264 * TSO transaction described in SF-108452-SW. 2265 */ 2266 encp->enc_tx_tso_max_nframes = 32767; 2267 2268 /* 2269 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use 2270 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available 2271 * resources (allocated to this PCIe function), which is zero until 2272 * after we have allocated VIs. 2273 */ 2274 encp->enc_evq_limit = 1024; 2275 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; 2276 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; 2277 2278 encp->enc_buftbl_limit = UINT32_MAX; 2279 2280 if ((rc = ef10_set_workaround_bug26807(enp)) != 0) 2281 goto fail3; 2282 2283 /* Get remaining controller-specific board config */ 2284 if ((rc = enop->eno_board_cfg(enp)) != 0) 2285 if (rc != EACCES) 2286 goto fail4; 2287 2288 return (0); 2289 2290 fail4: 2291 EFSYS_PROBE(fail4); 2292 fail3: 2293 EFSYS_PROBE(fail3); 2294 fail2: 2295 EFSYS_PROBE(fail2); 2296 fail1: 2297 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2298 2299 return (rc); 2300 } 2301 2302 __checkReturn efx_rc_t 2303 ef10_nic_probe( 2304 __in efx_nic_t *enp) 2305 { 2306 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2307 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); 2308 efx_rc_t rc; 2309 2310 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2311 2312 /* Read and clear any assertion state */ 2313 if ((rc = efx_mcdi_read_assertion(enp)) != 0) 2314 goto fail1; 2315 2316 /* Exit the assertion handler */ 2317 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) 2318 if (rc != EACCES) 2319 goto fail2; 2320 2321 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0) 2322 goto fail3; 2323 2324 if ((rc = ef10_nic_board_cfg(enp)) != 0) 2325 goto fail4; 2326 2327 /* 2328 * Set default driver config limits (based on board config). 2329 * 2330 * FIXME: For now allocate a fixed number of VIs which is likely to be 2331 * sufficient and small enough to allow multiple functions on the same 2332 * port. 2333 */ 2334 edcp->edc_min_vi_count = edcp->edc_max_vi_count = 2335 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit)); 2336 2337 /* The client driver must configure and enable PIO buffer support */ 2338 edcp->edc_max_piobuf_count = 0; 2339 edcp->edc_pio_alloc_size = 0; 2340 2341 #if EFSYS_OPT_MAC_STATS 2342 /* Wipe the MAC statistics */ 2343 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0) 2344 goto fail5; 2345 #endif 2346 2347 #if EFSYS_OPT_LOOPBACK 2348 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0) 2349 goto fail6; 2350 #endif 2351 2352 #if EFSYS_OPT_MON_STATS 2353 if ((rc = mcdi_mon_cfg_build(enp)) != 0) { 2354 /* Unprivileged functions do not have access to sensors */ 2355 if (rc != EACCES) 2356 goto fail7; 2357 } 2358 #endif 2359 2360 return (0); 2361 2362 #if EFSYS_OPT_MON_STATS 2363 fail7: 2364 EFSYS_PROBE(fail7); 2365 #endif 2366 #if EFSYS_OPT_LOOPBACK 2367 fail6: 2368 EFSYS_PROBE(fail6); 2369 #endif 2370 #if EFSYS_OPT_MAC_STATS 2371 fail5: 2372 EFSYS_PROBE(fail5); 2373 #endif 2374 fail4: 2375 EFSYS_PROBE(fail4); 2376 fail3: 2377 EFSYS_PROBE(fail3); 2378 fail2: 2379 EFSYS_PROBE(fail2); 2380 fail1: 2381 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2382 2383 return (rc); 2384 } 2385 2386 __checkReturn efx_rc_t 2387 ef10_nic_set_drv_limits( 2388 __inout efx_nic_t *enp, 2389 __in efx_drv_limits_t *edlp) 2390 { 2391 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2392 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); 2393 uint32_t min_evq_count, max_evq_count; 2394 uint32_t min_rxq_count, max_rxq_count; 2395 uint32_t min_txq_count, max_txq_count; 2396 efx_rc_t rc; 2397 2398 if (edlp == NULL) { 2399 rc = EINVAL; 2400 goto fail1; 2401 } 2402 2403 /* Get minimum required and maximum usable VI limits */ 2404 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit); 2405 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit); 2406 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit); 2407 2408 edcp->edc_min_vi_count = 2409 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count)); 2410 2411 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit); 2412 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit); 2413 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit); 2414 2415 edcp->edc_max_vi_count = 2416 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count)); 2417 2418 /* 2419 * Check limits for sub-allocated piobuf blocks. 2420 * PIO is optional, so don't fail if the limits are incorrect. 2421 */ 2422 if ((encp->enc_piobuf_size == 0) || 2423 (encp->enc_piobuf_limit == 0) || 2424 (edlp->edl_min_pio_alloc_size == 0) || 2425 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) { 2426 /* Disable PIO */ 2427 edcp->edc_max_piobuf_count = 0; 2428 edcp->edc_pio_alloc_size = 0; 2429 } else { 2430 uint32_t blk_size, blk_count, blks_per_piobuf; 2431 2432 blk_size = 2433 MAX(edlp->edl_min_pio_alloc_size, 2434 encp->enc_piobuf_min_alloc_size); 2435 2436 blks_per_piobuf = encp->enc_piobuf_size / blk_size; 2437 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32); 2438 2439 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf); 2440 2441 /* A zero max pio alloc count means unlimited */ 2442 if ((edlp->edl_max_pio_alloc_count > 0) && 2443 (edlp->edl_max_pio_alloc_count < blk_count)) { 2444 blk_count = edlp->edl_max_pio_alloc_count; 2445 } 2446 2447 edcp->edc_pio_alloc_size = blk_size; 2448 edcp->edc_max_piobuf_count = 2449 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf; 2450 } 2451 2452 return (0); 2453 2454 fail1: 2455 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2456 2457 return (rc); 2458 } 2459 2460 2461 __checkReturn efx_rc_t 2462 ef10_nic_reset( 2463 __in efx_nic_t *enp) 2464 { 2465 efx_rc_t rc; 2466 2467 /* ef10_nic_reset() is called to recover from BADASSERT failures. */ 2468 if ((rc = efx_mcdi_read_assertion(enp)) != 0) 2469 goto fail1; 2470 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) 2471 goto fail2; 2472 2473 if ((rc = efx_mcdi_entity_reset(enp)) != 0) 2474 goto fail3; 2475 2476 /* Clear RX/TX DMA queue errors */ 2477 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR); 2478 2479 return (0); 2480 2481 fail3: 2482 EFSYS_PROBE(fail3); 2483 fail2: 2484 EFSYS_PROBE(fail2); 2485 fail1: 2486 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2487 2488 return (rc); 2489 } 2490 2491 #endif /* EFX_OPTS_EF10() */ 2492 2493 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 2494 2495 __checkReturn efx_rc_t 2496 ef10_upstream_port_vadaptor_alloc( 2497 __in efx_nic_t *enp) 2498 { 2499 uint32_t retry; 2500 uint32_t delay_us; 2501 efx_rc_t rc; 2502 2503 /* 2504 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF 2505 * driver has yet to bring up the EVB port. See bug 56147. In this case, 2506 * retry the request several times after waiting a while. The wait time 2507 * between retries starts small (10ms) and exponentially increases. 2508 * Total wait time is a little over two seconds. Retry logic in the 2509 * client driver may mean this whole loop is repeated if it continues to 2510 * fail. 2511 */ 2512 retry = 0; 2513 delay_us = 10000; 2514 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) { 2515 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) || 2516 (rc != ENOENT)) { 2517 /* 2518 * Do not retry alloc for PF, or for other errors on 2519 * a VF. 2520 */ 2521 goto fail1; 2522 } 2523 2524 /* VF startup before PF is ready. Retry allocation. */ 2525 if (retry > 5) { 2526 /* Too many attempts */ 2527 rc = EINVAL; 2528 goto fail2; 2529 } 2530 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry); 2531 EFSYS_SLEEP(delay_us); 2532 retry++; 2533 if (delay_us < 500000) 2534 delay_us <<= 2; 2535 } 2536 2537 return (0); 2538 2539 fail2: 2540 EFSYS_PROBE(fail2); 2541 fail1: 2542 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2543 2544 return (rc); 2545 } 2546 2547 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 2548 2549 #if EFX_OPTS_EF10() 2550 2551 __checkReturn efx_rc_t 2552 ef10_nic_init( 2553 __in efx_nic_t *enp) 2554 { 2555 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); 2556 uint32_t min_vi_count, max_vi_count; 2557 uint32_t vi_count, vi_base, vi_shift; 2558 uint32_t i; 2559 uint32_t vi_window_size; 2560 efx_rc_t rc; 2561 boolean_t alloc_vadaptor = B_TRUE; 2562 2563 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2564 2565 /* Enable reporting of some events (e.g. link change) */ 2566 if ((rc = efx_mcdi_log_ctrl(enp)) != 0) 2567 goto fail1; 2568 2569 /* Allocate (optional) on-chip PIO buffers */ 2570 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count); 2571 2572 /* 2573 * For best performance, PIO writes should use a write-combined 2574 * (WC) memory mapping. Using a separate WC mapping for the PIO 2575 * aperture of each VI would be a burden to drivers (and not 2576 * possible if the host page size is >4Kbyte). 2577 * 2578 * To avoid this we use a single uncached (UC) mapping for VI 2579 * register access, and a single WC mapping for extra VIs used 2580 * for PIO writes. 2581 * 2582 * Each piobuf must be linked to a VI in the WC mapping, and to 2583 * each VI that is using a sub-allocated block from the piobuf. 2584 */ 2585 min_vi_count = edcp->edc_min_vi_count; 2586 max_vi_count = 2587 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count; 2588 2589 /* Ensure that the previously attached driver's VIs are freed */ 2590 if ((rc = efx_mcdi_free_vis(enp)) != 0) 2591 goto fail2; 2592 2593 /* 2594 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this 2595 * fails then retrying the request for fewer VI resources may succeed. 2596 */ 2597 vi_count = 0; 2598 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count, 2599 &vi_base, &vi_count, &vi_shift)) != 0) 2600 goto fail3; 2601 2602 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count); 2603 2604 if (vi_count < min_vi_count) { 2605 rc = ENOMEM; 2606 goto fail4; 2607 } 2608 2609 enp->en_arch.ef10.ena_vi_base = vi_base; 2610 enp->en_arch.ef10.ena_vi_count = vi_count; 2611 enp->en_arch.ef10.ena_vi_shift = vi_shift; 2612 2613 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) { 2614 /* Not enough extra VIs to map piobufs */ 2615 ef10_nic_free_piobufs(enp); 2616 } 2617 2618 enp->en_arch.ef10.ena_pio_write_vi_base = 2619 vi_count - enp->en_arch.ef10.ena_piobuf_count; 2620 2621 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=, 2622 EFX_VI_WINDOW_SHIFT_INVALID); 2623 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=, 2624 EFX_VI_WINDOW_SHIFT_64K); 2625 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift; 2626 2627 /* Save UC memory mapping details */ 2628 enp->en_arch.ef10.ena_uc_mem_map_offset = 0; 2629 if (enp->en_arch.ef10.ena_piobuf_count > 0) { 2630 enp->en_arch.ef10.ena_uc_mem_map_size = 2631 (vi_window_size * 2632 enp->en_arch.ef10.ena_pio_write_vi_base); 2633 } else { 2634 enp->en_arch.ef10.ena_uc_mem_map_size = 2635 (vi_window_size * 2636 enp->en_arch.ef10.ena_vi_count); 2637 } 2638 2639 /* Save WC memory mapping details */ 2640 enp->en_arch.ef10.ena_wc_mem_map_offset = 2641 enp->en_arch.ef10.ena_uc_mem_map_offset + 2642 enp->en_arch.ef10.ena_uc_mem_map_size; 2643 2644 enp->en_arch.ef10.ena_wc_mem_map_size = 2645 (vi_window_size * 2646 enp->en_arch.ef10.ena_piobuf_count); 2647 2648 /* Link piobufs to extra VIs in WC mapping */ 2649 if (enp->en_arch.ef10.ena_piobuf_count > 0) { 2650 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 2651 rc = efx_mcdi_link_piobuf(enp, 2652 enp->en_arch.ef10.ena_pio_write_vi_base + i, 2653 enp->en_arch.ef10.ena_piobuf_handle[i]); 2654 if (rc != 0) 2655 break; 2656 } 2657 } 2658 2659 /* 2660 * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs 2661 * during NIC initialization when vSwitch is created and vports are 2662 * allocated. Hence, skip vAdaptor allocation for EVB and update vport 2663 * id in NIC structure with the one allocated for PF. 2664 */ 2665 2666 enp->en_vport_id = EVB_PORT_ID_ASSIGNED; 2667 #if EFSYS_OPT_EVB 2668 if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) { 2669 /* For EVB use vport allocated on vswitch */ 2670 enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id; 2671 alloc_vadaptor = B_FALSE; 2672 } 2673 #endif 2674 if (alloc_vadaptor != B_FALSE) { 2675 /* Allocate a vAdaptor attached to our upstream vPort/pPort */ 2676 if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0) 2677 goto fail5; 2678 } 2679 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2; 2680 2681 return (0); 2682 2683 fail5: 2684 EFSYS_PROBE(fail5); 2685 fail4: 2686 EFSYS_PROBE(fail4); 2687 fail3: 2688 EFSYS_PROBE(fail3); 2689 fail2: 2690 EFSYS_PROBE(fail2); 2691 2692 ef10_nic_free_piobufs(enp); 2693 2694 fail1: 2695 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2696 2697 return (rc); 2698 } 2699 2700 __checkReturn efx_rc_t 2701 ef10_nic_get_vi_pool( 2702 __in efx_nic_t *enp, 2703 __out uint32_t *vi_countp) 2704 { 2705 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2706 2707 /* 2708 * Report VIs that the client driver can use. 2709 * Do not include VIs used for PIO buffer writes. 2710 */ 2711 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base; 2712 2713 return (0); 2714 } 2715 2716 __checkReturn efx_rc_t 2717 ef10_nic_get_bar_region( 2718 __in efx_nic_t *enp, 2719 __in efx_nic_region_t region, 2720 __out uint32_t *offsetp, 2721 __out size_t *sizep) 2722 { 2723 efx_rc_t rc; 2724 2725 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2726 2727 /* 2728 * TODO: Specify host memory mapping alignment and granularity 2729 * in efx_drv_limits_t so that they can be taken into account 2730 * when allocating extra VIs for PIO writes. 2731 */ 2732 switch (region) { 2733 case EFX_REGION_VI: 2734 /* UC mapped memory BAR region for VI registers */ 2735 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset; 2736 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size; 2737 break; 2738 2739 case EFX_REGION_PIO_WRITE_VI: 2740 /* WC mapped memory BAR region for piobuf writes */ 2741 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset; 2742 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size; 2743 break; 2744 2745 default: 2746 rc = EINVAL; 2747 goto fail1; 2748 } 2749 2750 return (0); 2751 2752 fail1: 2753 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2754 2755 return (rc); 2756 } 2757 2758 __checkReturn boolean_t 2759 ef10_nic_hw_unavailable( 2760 __in efx_nic_t *enp) 2761 { 2762 efx_dword_t dword; 2763 2764 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL) 2765 return (B_TRUE); 2766 2767 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE); 2768 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff) 2769 goto unavail; 2770 2771 return (B_FALSE); 2772 2773 unavail: 2774 ef10_nic_set_hw_unavailable(enp); 2775 2776 return (B_TRUE); 2777 } 2778 2779 void 2780 ef10_nic_set_hw_unavailable( 2781 __in efx_nic_t *enp) 2782 { 2783 EFSYS_PROBE(hw_unavail); 2784 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL; 2785 } 2786 2787 2788 void 2789 ef10_nic_fini( 2790 __in efx_nic_t *enp) 2791 { 2792 uint32_t i; 2793 efx_rc_t rc; 2794 boolean_t do_vadaptor_free = B_TRUE; 2795 2796 #if EFSYS_OPT_EVB 2797 if (enp->en_vswitchp != NULL) { 2798 /* 2799 * For SR-IOV the vAdaptor is freed with the vswitch, 2800 * so do not free it here. 2801 */ 2802 do_vadaptor_free = B_FALSE; 2803 } 2804 #endif 2805 if (do_vadaptor_free != B_FALSE) { 2806 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id); 2807 enp->en_vport_id = EVB_PORT_ID_NULL; 2808 } 2809 2810 /* Unlink piobufs from extra VIs in WC mapping */ 2811 if (enp->en_arch.ef10.ena_piobuf_count > 0) { 2812 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 2813 rc = efx_mcdi_unlink_piobuf(enp, 2814 enp->en_arch.ef10.ena_pio_write_vi_base + i); 2815 if (rc != 0) 2816 break; 2817 } 2818 } 2819 2820 ef10_nic_free_piobufs(enp); 2821 2822 (void) efx_mcdi_free_vis(enp); 2823 enp->en_arch.ef10.ena_vi_count = 0; 2824 } 2825 2826 void 2827 ef10_nic_unprobe( 2828 __in efx_nic_t *enp) 2829 { 2830 #if EFSYS_OPT_MON_STATS 2831 mcdi_mon_cfg_free(enp); 2832 #endif /* EFSYS_OPT_MON_STATS */ 2833 (void) efx_mcdi_drv_attach(enp, B_FALSE); 2834 } 2835 2836 #if EFSYS_OPT_DIAG 2837 2838 __checkReturn efx_rc_t 2839 ef10_nic_register_test( 2840 __in efx_nic_t *enp) 2841 { 2842 efx_rc_t rc; 2843 2844 /* FIXME */ 2845 _NOTE(ARGUNUSED(enp)) 2846 _NOTE(CONSTANTCONDITION) 2847 if (B_FALSE) { 2848 rc = ENOTSUP; 2849 goto fail1; 2850 } 2851 /* FIXME */ 2852 2853 return (0); 2854 2855 fail1: 2856 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2857 2858 return (rc); 2859 } 2860 2861 #endif /* EFSYS_OPT_DIAG */ 2862 2863 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 2864 2865 __checkReturn efx_rc_t 2866 efx_mcdi_get_nic_global( 2867 __in efx_nic_t *enp, 2868 __in uint32_t key, 2869 __out uint32_t *valuep) 2870 { 2871 efx_mcdi_req_t req; 2872 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN, 2873 MC_CMD_GET_NIC_GLOBAL_OUT_LEN); 2874 efx_rc_t rc; 2875 2876 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL; 2877 req.emr_in_buf = payload; 2878 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN; 2879 req.emr_out_buf = payload; 2880 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN; 2881 2882 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key); 2883 2884 efx_mcdi_execute(enp, &req); 2885 2886 if (req.emr_rc != 0) { 2887 rc = req.emr_rc; 2888 goto fail1; 2889 } 2890 2891 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) { 2892 rc = EMSGSIZE; 2893 goto fail2; 2894 } 2895 2896 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE); 2897 2898 return (0); 2899 2900 fail2: 2901 EFSYS_PROBE(fail2); 2902 fail1: 2903 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2904 2905 return (rc); 2906 } 2907 2908 __checkReturn efx_rc_t 2909 efx_mcdi_set_nic_global( 2910 __in efx_nic_t *enp, 2911 __in uint32_t key, 2912 __in uint32_t value) 2913 { 2914 efx_mcdi_req_t req; 2915 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0); 2916 efx_rc_t rc; 2917 2918 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL; 2919 req.emr_in_buf = payload; 2920 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN; 2921 req.emr_out_buf = NULL; 2922 req.emr_out_length = 0; 2923 2924 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key); 2925 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value); 2926 2927 efx_mcdi_execute(enp, &req); 2928 2929 if (req.emr_rc != 0) { 2930 rc = req.emr_rc; 2931 goto fail1; 2932 } 2933 2934 return (0); 2935 2936 fail1: 2937 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2938 2939 return (rc); 2940 } 2941 2942 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 2943 2944 #endif /* EFX_OPTS_EF10() */ 2945