1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2015-2018 Intel Corporation 3 */ 4 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H 5 #define ADF_TRANSPORT_ACCESS_MACROS_H 6 7 #include <rte_io.h> 8 9 /* CSR write macro */ 10 #define ADF_CSR_WR(csrAddr, csrOffset, val) \ 11 rte_write32(val, (((uint8_t *)csrAddr) + csrOffset)) 12 #define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \ 13 rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset)) 14 15 /* CSR read macro */ 16 #define ADF_CSR_RD(csrAddr, csrOffset) \ 17 rte_read32((((uint8_t *)csrAddr) + csrOffset)) 18 19 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL 20 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL 21 #define ADF_RING_CSR_RING_CONFIG 0x000 22 #define ADF_RING_CSR_RING_LBASE 0x040 23 #define ADF_RING_CSR_RING_UBASE 0x080 24 #define ADF_RING_CSR_RING_HEAD 0x0C0 25 #define ADF_RING_CSR_RING_TAIL 0x100 26 #define ADF_RING_CSR_E_STAT 0x14C 27 #define ADF_RING_CSR_INT_SRCSEL 0x174 28 #define ADF_RING_CSR_INT_SRCSEL_2 0x178 29 #define ADF_RING_CSR_INT_COL_EN 0x17C 30 #define ADF_RING_CSR_INT_COL_CTL 0x180 31 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 32 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 33 #define ADF_RING_BUNDLE_SIZE 0x1000 34 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A 35 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05 36 #define ADF_COALESCING_MIN_TIME 0x1FF 37 #define ADF_COALESCING_MAX_TIME 0xFFFFF 38 #define ADF_COALESCING_DEF_TIME 0x27FF 39 #define ADF_RING_NEAR_WATERMARK_512 0x08 40 #define ADF_RING_NEAR_WATERMARK_0 0x00 41 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F 42 #define ADF_RING_EMPTY_SIG_BYTE 0x7F 43 44 /* Valid internal ring size values */ 45 #define ADF_RING_SIZE_128 0x01 46 #define ADF_RING_SIZE_256 0x02 47 #define ADF_RING_SIZE_512 0x03 48 #define ADF_RING_SIZE_4K 0x06 49 #define ADF_RING_SIZE_16K 0x08 50 #define ADF_RING_SIZE_4M 0x10 51 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128 52 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M 53 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K 54 55 /* Maximum number of qps on a device for any service type */ 56 #define ADF_MAX_QPS_ON_ANY_SERVICE 2 57 #define ADF_RING_DIR_TX 0 58 #define ADF_RING_DIR_RX 1 59 60 /* Valid internal msg size values */ 61 #define ADF_MSG_SIZE_32 0x01 62 #define ADF_MSG_SIZE_64 0x02 63 #define ADF_MSG_SIZE_128 0x04 64 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32 65 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128 66 67 /* Size to bytes conversion macros for ring and msg size values */ 68 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5) 69 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5) 70 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7) 71 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7) 72 73 /* Minimum ring bufer size for memory allocation */ 74 #define ADF_RING_SIZE_BYTES_MIN(SIZE) ((SIZE < ADF_RING_SIZE_4K) ? \ 75 ADF_RING_SIZE_4K : SIZE) 76 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6) 77 #define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \ 78 SIZE) & ~0x4) 79 /* Max outstanding requests */ 80 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \ 81 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1) 82 #define BUILD_RING_CONFIG(size) \ 83 ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \ 84 | (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \ 85 | size) 86 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \ 87 ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) \ 88 | (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \ 89 | size) 90 #define BUILD_RING_BASE_ADDR(addr, size) \ 91 ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size)) 92 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 93 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 94 ADF_RING_CSR_RING_HEAD + (ring << 2)) 95 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 96 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 97 ADF_RING_CSR_RING_TAIL + (ring << 2)) 98 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 99 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 100 ADF_RING_CSR_E_STAT) 101 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 102 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 103 ADF_RING_CSR_RING_CONFIG + (ring << 2), value) 104 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 105 do { \ 106 uint32_t l_base = 0, u_base = 0; \ 107 l_base = (uint32_t)(value & 0xFFFFFFFF); \ 108 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \ 109 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 110 ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \ 111 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 112 ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \ 113 } while (0) 114 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 115 ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 116 ADF_RING_CSR_RING_HEAD + (ring << 2), value) 117 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 118 ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 119 ADF_RING_CSR_RING_TAIL + (ring << 2), value) 120 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 121 do { \ 122 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 123 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \ 124 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 125 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \ 126 } while (0) 127 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 128 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 129 ADF_RING_CSR_INT_COL_EN, value) 130 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 131 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 132 ADF_RING_CSR_INT_COL_CTL, \ 133 ADF_RING_CSR_INT_COL_CTL_ENABLE | value) 134 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 135 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 136 ADF_RING_CSR_INT_FLAG_AND_COL, value) 137 138 #endif /*ADF_TRANSPORT_ACCESS_MACROS_H */ 139