1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2019 Marvell International Ltd. 3 */ 4 5 #ifndef _NITROX_HAL_H_ 6 #define _NITROX_HAL_H_ 7 8 #include <rte_cycles.h> 9 #include <rte_byteorder.h> 10 11 #include "nitrox_csr.h" 12 13 union nps_pkt_slc_cnts { 14 uint64_t u64; 15 struct { 16 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 17 uint64_t slc_int : 1; 18 uint64_t uns_int : 1; 19 uint64_t in_int : 1; 20 uint64_t mbox_int : 1; 21 uint64_t resend : 1; 22 uint64_t raz : 5; 23 uint64_t timer : 22; 24 uint64_t cnt : 32; 25 #else 26 uint64_t cnt : 32; 27 uint64_t timer : 22; 28 uint64_t raz : 5; 29 uint64_t resend : 1; 30 uint64_t mbox_int : 1; 31 uint64_t in_int : 1; 32 uint64_t uns_int : 1; 33 uint64_t slc_int : 1; 34 #endif 35 } s; 36 }; 37 38 union nps_pkt_slc_int_levels { 39 uint64_t u64; 40 struct { 41 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 42 uint64_t bmode : 1; 43 uint64_t raz : 9; 44 uint64_t timet : 22; 45 uint64_t cnt : 32; 46 #else 47 uint64_t cnt : 32; 48 uint64_t timet : 22; 49 uint64_t raz : 9; 50 uint64_t bmode : 1; 51 #endif 52 } s; 53 }; 54 55 union nps_pkt_slc_ctl { 56 uint64_t u64; 57 struct { 58 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 59 uint64_t raz : 61; 60 uint64_t rh : 1; 61 uint64_t z : 1; 62 uint64_t enb : 1; 63 #else 64 uint64_t enb : 1; 65 uint64_t z : 1; 66 uint64_t rh : 1; 67 uint64_t raz : 61; 68 #endif 69 } s; 70 }; 71 72 union nps_pkt_in_instr_ctl { 73 uint64_t u64; 74 struct { 75 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 76 uint64_t raz : 62; 77 uint64_t is64b : 1; 78 uint64_t enb : 1; 79 #else 80 uint64_t enb : 1; 81 uint64_t is64b : 1; 82 uint64_t raz : 62; 83 #endif 84 } s; 85 }; 86 87 union nps_pkt_in_instr_rsize { 88 uint64_t u64; 89 struct { 90 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 91 uint64_t raz : 32; 92 uint64_t rsize : 32; 93 #else 94 uint64_t rsize : 32; 95 uint64_t raz : 32; 96 #endif 97 } s; 98 }; 99 100 union nps_pkt_in_instr_baoff_dbell { 101 uint64_t u64; 102 struct { 103 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 104 uint64_t aoff : 32; 105 uint64_t dbell : 32; 106 #else 107 uint64_t dbell : 32; 108 uint64_t aoff : 32; 109 #endif 110 } s; 111 }; 112 113 union nps_pkt_in_done_cnts { 114 uint64_t u64; 115 struct { 116 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 117 uint64_t slc_int : 1; 118 uint64_t uns_int : 1; 119 uint64_t in_int : 1; 120 uint64_t mbox_int : 1; 121 uint64_t resend : 1; 122 uint64_t raz : 27; 123 uint64_t cnt : 32; 124 #else 125 uint64_t cnt : 32; 126 uint64_t raz : 27; 127 uint64_t resend : 1; 128 uint64_t mbox_int : 1; 129 uint64_t in_int : 1; 130 uint64_t uns_int : 1; 131 uint64_t slc_int : 1; 132 #endif 133 } s; 134 }; 135 136 union aqmq_qsz { 137 uint64_t u64; 138 struct { 139 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 140 uint64_t raz : 32; 141 uint64_t host_queue_size : 32; 142 #else 143 uint64_t host_queue_size : 32; 144 uint64_t raz : 32; 145 #endif 146 } s; 147 }; 148 149 union zqmq_activity_stat { 150 uint64_t u64; 151 struct { 152 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 153 uint64_t raz : 63; 154 uint64_t queue_active : 1; 155 #else 156 uint64_t queue_active : 1; 157 uint64_t raz : 63; 158 #endif 159 } s; 160 }; 161 162 union zqmq_en { 163 uint64_t u64; 164 struct { 165 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 166 uint64_t raz : 63; 167 uint64_t queue_enable : 1; 168 #else 169 uint64_t queue_enable : 1; 170 uint64_t raz : 63; 171 #endif 172 } s; 173 }; 174 175 union zqmq_cmp_cnt { 176 uint64_t u64; 177 struct { 178 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 179 uint64_t raz : 30; 180 uint64_t resend : 1; 181 uint64_t completion_status : 1; 182 uint64_t commands_completed_count: 32; 183 #else 184 uint64_t commands_completed_count: 32; 185 uint64_t completion_status : 1; 186 uint64_t resend : 1; 187 uint64_t raz : 30; 188 #endif 189 } s; 190 }; 191 192 union zqmq_drbl { 193 uint64_t u64; 194 struct { 195 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 196 uint64_t raz : 32; 197 uint64_t dbell_count : 32; 198 #else 199 uint64_t dbell_count : 32; 200 uint64_t raz : 32; 201 #endif 202 } s; 203 }; 204 205 union zqmq_qsz { 206 uint64_t u64; 207 struct { 208 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 209 uint64_t raz : 32; 210 uint64_t host_queue_size: 32; 211 #else 212 uint64_t host_queue_size: 32; 213 uint64_t raz : 32; 214 #endif 215 } s; 216 }; 217 218 union zqmq_cmp_thr { 219 uint64_t u64; 220 struct { 221 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 222 uint64_t raz : 32; 223 uint64_t commands_completed_threshold : 32; 224 #else 225 uint64_t commands_completed_threshold : 32; 226 uint64_t raz : 32; 227 #endif 228 } s; 229 }; 230 231 union zqmq_timer_ld { 232 uint64_t u64; 233 struct { 234 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 235 uint64_t raz : 32; 236 uint64_t timer_load_value: 32; 237 #else 238 uint64_t timer_load_value: 32; 239 uint64_t raz : 32; 240 #endif 241 } s; 242 }; 243 244 enum nitrox_vf_mode { 245 NITROX_MODE_PF = 0x0, 246 NITROX_MODE_VF16 = 0x1, 247 NITROX_MODE_VF32 = 0x2, 248 NITROX_MODE_VF64 = 0x3, 249 NITROX_MODE_VF128 = 0x4, 250 }; 251 252 static inline int 253 inc_zqmq_next_cmd(uint8_t *bar_addr, uint16_t ring) 254 { 255 uint64_t reg_addr = 0; 256 uint64_t val; 257 258 reg_addr = ZQMQ_NXT_CMDX(ring); 259 val = nitrox_read_csr(bar_addr, reg_addr); 260 val++; 261 nitrox_write_csr(bar_addr, reg_addr, val); 262 rte_delay_us_block(CSR_DELAY); 263 if (nitrox_read_csr(bar_addr, reg_addr) != val) 264 return -EIO; 265 266 return 0; 267 } 268 269 int vf_get_vf_config_mode(uint8_t *bar_addr); 270 int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode); 271 void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize, 272 phys_addr_t raddr); 273 void setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port); 274 void nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring); 275 void nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port); 276 int setup_zqmq_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize, 277 phys_addr_t raddr); 278 int zqmq_input_ring_disable(uint8_t *bar_addr, uint16_t ring); 279 280 #endif /* _NITROX_HAL_H_ */ 281