1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2023 Corigine, Inc. 3 * All rights reserved. 4 */ 5 6 #include "nfp_dev.h" 7 8 #include <nfp_platform.h> 9 #include <rte_bitops.h> 10 11 /* 12 * Note: The value of 'max_qc_size' is different from kernel driver, 13 * because DPDK use 'uint16_t' as the data type. 14 */ 15 const struct nfp_dev_info nfp_dev_info[NFP_DEV_CNT] = { 16 [NFP_DEV_NFP3800] = { 17 .qc_idx_mask = GENMASK(8, 0), 18 .qc_addr_offset = 0x400000, 19 .min_qc_size = 512, 20 .max_qc_size = RTE_BIT32(15), /**< 32K */ 21 22 .chip_names = "NFP3800", 23 .pcie_cfg_expbar_offset = 0x0a00, 24 .qc_area_sz = 0x100000, 25 .pf_num_per_unit = 4, 26 }, 27 [NFP_DEV_NFP3800_VF] = { 28 .qc_idx_mask = GENMASK(8, 0), 29 .qc_addr_offset = 0, 30 .min_qc_size = 512, 31 .max_qc_size = RTE_BIT32(15), /**< 32K */ 32 }, 33 [NFP_DEV_NFP6000] = { 34 .qc_idx_mask = GENMASK(7, 0), 35 .qc_addr_offset = 0x80000, 36 .min_qc_size = 256, 37 .max_qc_size = RTE_BIT32(15), /**< 32K */ 38 39 .chip_names = "NFP4000/NFP6000", 40 .pcie_cfg_expbar_offset = 0x0400, 41 .qc_area_sz = 0x80000, 42 .pf_num_per_unit = 1, 43 }, 44 [NFP_DEV_NFP6000_VF] = { 45 .qc_idx_mask = GENMASK(7, 0), 46 .qc_addr_offset = 0, 47 .min_qc_size = 256, 48 .max_qc_size = RTE_BIT32(15), /**< 32K */ 49 }, 50 }; 51 52 const struct nfp_dev_info * 53 nfp_dev_info_get(uint16_t device_id) 54 { 55 enum nfp_dev_id id; 56 57 switch (device_id) { 58 case PCI_DEVICE_ID_NFP3800_PF_NIC: 59 id = NFP_DEV_NFP3800; 60 break; 61 case PCI_DEVICE_ID_NFP3800_VF_NIC: 62 id = NFP_DEV_NFP3800_VF; 63 break; 64 case PCI_DEVICE_ID_NFP4000_PF_NIC: 65 case PCI_DEVICE_ID_NFP6000_PF_NIC: 66 id = NFP_DEV_NFP6000; 67 break; 68 case PCI_DEVICE_ID_NFP6000_VF_NIC: 69 id = NFP_DEV_NFP6000_VF; 70 break; 71 default: 72 id = NFP_DEV_CNT; 73 break; 74 } 75 76 if (id >= NFP_DEV_CNT) 77 return NULL; 78 79 return &nfp_dev_info[id]; 80 } 81