xref: /dpdk/drivers/common/nfp/nfp_dev.c (revision 4967a1c8224286072ba4d72d3463ceca253bedd5)
1*4967a1c8SChaoyong He /* SPDX-License-Identifier: BSD-3-Clause
2*4967a1c8SChaoyong He  * Copyright(c) 2023 Corigine, Inc.
3*4967a1c8SChaoyong He  * All rights reserved.
4*4967a1c8SChaoyong He  */
5*4967a1c8SChaoyong He 
6*4967a1c8SChaoyong He #include "nfp_dev.h"
7*4967a1c8SChaoyong He 
8*4967a1c8SChaoyong He #include <nfp_platform.h>
9*4967a1c8SChaoyong He #include <rte_bitops.h>
10*4967a1c8SChaoyong He 
11*4967a1c8SChaoyong He /*
12*4967a1c8SChaoyong He  * Note: The value of 'max_qc_size' is different from kernel driver,
13*4967a1c8SChaoyong He  * because DPDK use 'uint16_t' as the data type.
14*4967a1c8SChaoyong He  */
15*4967a1c8SChaoyong He const struct nfp_dev_info nfp_dev_info[NFP_DEV_CNT] = {
16*4967a1c8SChaoyong He 	[NFP_DEV_NFP3800] = {
17*4967a1c8SChaoyong He 		.qc_idx_mask            = GENMASK(8, 0),
18*4967a1c8SChaoyong He 		.qc_addr_offset         = 0x400000,
19*4967a1c8SChaoyong He 		.min_qc_size            = 512,
20*4967a1c8SChaoyong He 		.max_qc_size            = RTE_BIT32(15),    /**< 32K */
21*4967a1c8SChaoyong He 
22*4967a1c8SChaoyong He 		.chip_names             = "NFP3800",
23*4967a1c8SChaoyong He 		.pcie_cfg_expbar_offset = 0x0a00,
24*4967a1c8SChaoyong He 		.qc_area_sz             = 0x100000,
25*4967a1c8SChaoyong He 		.pf_num_per_unit        = 4,
26*4967a1c8SChaoyong He 	},
27*4967a1c8SChaoyong He 	[NFP_DEV_NFP3800_VF] = {
28*4967a1c8SChaoyong He 		.qc_idx_mask            = GENMASK(8, 0),
29*4967a1c8SChaoyong He 		.qc_addr_offset         = 0,
30*4967a1c8SChaoyong He 		.min_qc_size            = 512,
31*4967a1c8SChaoyong He 		.max_qc_size            = RTE_BIT32(15),    /**< 32K */
32*4967a1c8SChaoyong He 	},
33*4967a1c8SChaoyong He 	[NFP_DEV_NFP6000] = {
34*4967a1c8SChaoyong He 		.qc_idx_mask            = GENMASK(7, 0),
35*4967a1c8SChaoyong He 		.qc_addr_offset         = 0x80000,
36*4967a1c8SChaoyong He 		.min_qc_size            = 256,
37*4967a1c8SChaoyong He 		.max_qc_size            = RTE_BIT32(15),    /**< 32K */
38*4967a1c8SChaoyong He 
39*4967a1c8SChaoyong He 		.chip_names             = "NFP4000/NFP6000",
40*4967a1c8SChaoyong He 		.pcie_cfg_expbar_offset = 0x0400,
41*4967a1c8SChaoyong He 		.qc_area_sz             = 0x80000,
42*4967a1c8SChaoyong He 		.pf_num_per_unit        = 1,
43*4967a1c8SChaoyong He 	},
44*4967a1c8SChaoyong He 	[NFP_DEV_NFP6000_VF] = {
45*4967a1c8SChaoyong He 		.qc_idx_mask            = GENMASK(7, 0),
46*4967a1c8SChaoyong He 		.qc_addr_offset         = 0,
47*4967a1c8SChaoyong He 		.min_qc_size            = 256,
48*4967a1c8SChaoyong He 		.max_qc_size            = RTE_BIT32(15),    /**< 32K */
49*4967a1c8SChaoyong He 	},
50*4967a1c8SChaoyong He };
51*4967a1c8SChaoyong He 
52*4967a1c8SChaoyong He const struct nfp_dev_info *
nfp_dev_info_get(uint16_t device_id)53*4967a1c8SChaoyong He nfp_dev_info_get(uint16_t device_id)
54*4967a1c8SChaoyong He {
55*4967a1c8SChaoyong He 	enum nfp_dev_id id;
56*4967a1c8SChaoyong He 
57*4967a1c8SChaoyong He 	switch (device_id) {
58*4967a1c8SChaoyong He 	case PCI_DEVICE_ID_NFP3800_PF_NIC:
59*4967a1c8SChaoyong He 		id = NFP_DEV_NFP3800;
60*4967a1c8SChaoyong He 		break;
61*4967a1c8SChaoyong He 	case PCI_DEVICE_ID_NFP3800_VF_NIC:
62*4967a1c8SChaoyong He 		id = NFP_DEV_NFP3800_VF;
63*4967a1c8SChaoyong He 		break;
64*4967a1c8SChaoyong He 	case PCI_DEVICE_ID_NFP4000_PF_NIC:
65*4967a1c8SChaoyong He 	case PCI_DEVICE_ID_NFP6000_PF_NIC:
66*4967a1c8SChaoyong He 		id = NFP_DEV_NFP6000;
67*4967a1c8SChaoyong He 		break;
68*4967a1c8SChaoyong He 	case PCI_DEVICE_ID_NFP6000_VF_NIC:
69*4967a1c8SChaoyong He 		id = NFP_DEV_NFP6000_VF;
70*4967a1c8SChaoyong He 		break;
71*4967a1c8SChaoyong He 	default:
72*4967a1c8SChaoyong He 		id = NFP_DEV_CNT;
73*4967a1c8SChaoyong He 		break;
74*4967a1c8SChaoyong He 	}
75*4967a1c8SChaoyong He 
76*4967a1c8SChaoyong He 	if (id >= NFP_DEV_CNT)
77*4967a1c8SChaoyong He 		return NULL;
78*4967a1c8SChaoyong He 
79*4967a1c8SChaoyong He 	return &nfp_dev_info[id];
80*4967a1c8SChaoyong He }
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