1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2023 Corigine, Inc. 3 * All rights reserved. 4 */ 5 6 #ifndef __NFP_COMMON_CTRL_H__ 7 #define __NFP_COMMON_CTRL_H__ 8 9 /* 10 * Configuration BAR size. 11 * 12 * On the NFP6000, due to THB-350, the configuration BAR is 32K in size. 13 */ 14 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 15 16 /* 17 * Configuration sriov VF. 18 * The configuration memory begins with a mailbox region for communication with 19 * the firmware followed by individual VF entries. 20 */ 21 #define NFP_NET_VF_CFG_SZ 16 22 #define NFP_NET_VF_CFG_MB_SZ 16 23 24 /* VF config mailbox */ 25 #define NFP_NET_VF_CFG_MB 0x0 26 #define NFP_NET_VF_CFG_MB_CAP 0x0 27 #define NFP_NET_VF_CFG_MB_CAP_QUEUE_CONFIG (0x1 << 7) 28 #define NFP_NET_VF_CFG_MB_CAP_SPLIT (0x1 << 8) 29 #define NFP_NET_VF_CFG_MB_RET 0x2 30 #define NFP_NET_VF_CFG_MB_UPD 0x4 31 #define NFP_NET_VF_CFG_MB_UPD_QUEUE_CONFIG (0x1 << 7) 32 #define NFP_NET_VF_CFG_MB_UPD_SPLIT (0x1 << 8) 33 #define NFP_NET_VF_CFG_MB_VF_CNT 0x6 34 #define NFP_NET_VF_CFG_MB_VF_NUM 0x7 35 36 /* 37 * @NFP_NET_TXR_MAX: Maximum number of TX rings 38 * @NFP_NET_TXR_MASK: Mask for TX rings 39 * @NFP_NET_RXR_MAX: Maximum number of RX rings 40 * @NFP_NET_RXR_MASK: Mask for RX rings 41 */ 42 #define NFP_NET_TXR_MAX 64 43 #define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1) 44 #define NFP_NET_RXR_MAX 64 45 #define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1) 46 47 /* 48 * Read/Write config words (0x0000 - 0x002c) 49 * @NFP_NET_CFG_CTRL: Global control 50 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated 51 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 52 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 53 * @NFP_NET_CFG_MTU: Set MTU size 54 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 55 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions 56 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes 57 * @NFP_NET_CFG_MACADDR: MAC address 58 * 59 * TODO: 60 * - define Error details in UPDATE 61 */ 62 #define NFP_NET_CFG_CTRL 0x0000 63 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 64 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 65 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 66 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 67 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 68 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 69 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 70 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 71 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 72 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 73 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */ 74 #define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable QINQ strip */ 75 #define NFP_NET_CFG_CTRL_RXVLAN_V2 (0x1 << 15) /* Enable VLAN strip with metadata */ 76 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 77 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */ 78 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 79 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 80 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 81 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring */ 82 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 83 #define NFP_NET_CFG_CTRL_TXVLAN_V2 (0x1 << 23) /* Enable VLAN insert with metadata */ 84 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */ 85 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */ 86 #define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */ 87 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 88 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 89 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 90 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31) /* Live MAC addr change */ 91 #define NFP_NET_CFG_UPDATE 0x0004 92 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 93 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 94 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 95 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 96 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 97 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 98 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 99 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 100 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 101 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 102 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 103 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 104 #define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */ 105 #define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */ 106 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 107 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 108 #define NFP_NET_CFG_MTU 0x0018 109 #define NFP_NET_CFG_FLBUFSZ 0x001c 110 #define NFP_NET_CFG_EXN 0x001f 111 #define NFP_NET_CFG_LSC 0x0020 112 #define NFP_NET_CFG_MACADDR 0x0024 113 114 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2) 115 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | NFP_NET_CFG_CTRL_RSS2) 116 117 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 118 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 119 120 /* Version number helper defines */ 121 struct nfp_net_fw_ver { 122 uint8_t minor; 123 uint8_t major; 124 uint8_t class; 125 /** 126 * This byte can be extended for more use. 127 * BIT0: NFD dp type, refer NFP_NET_CFG_VERSION_DP_NFDx 128 * BIT[7:1]: reserved 129 */ 130 uint8_t extend; 131 }; 132 133 /* 134 * Read-only words (0x0030 - 0x0050): 135 * @NFP_NET_CFG_VERSION: Firmware version number 136 * @NFP_NET_CFG_STS: Status 137 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL) 138 * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings 139 * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings 140 * @NFP_NET_MAX_MTU: Maximum support MTU 141 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 142 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 143 * 144 * TODO: 145 * - define more STS bits 146 */ 147 #define NFP_NET_CFG_VERSION 0x0030 148 #define NFP_NET_CFG_VERSION_DP_NFD3 0 149 #define NFP_NET_CFG_VERSION_DP_NFDK 1 150 #define NFP_NET_CFG_STS 0x0034 151 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 152 /* Link rate */ 153 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 154 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 155 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 156 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 157 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 158 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 159 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 160 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 161 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 162 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 163 164 /* 165 * NSP Link rate is a 16-bit word. It is no longer determined by 166 * firmware, instead it is read from the nfp_eth_table of the 167 * associated pf_dev and written to the NFP_NET_CFG_STS_NSP_LINK_RATE 168 * address by the PMD each time the port is reconfigured. 169 */ 170 #define NFP_NET_CFG_STS_NSP_LINK_RATE 0x0036 171 172 #define NFP_NET_CFG_CAP 0x0038 173 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 174 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 175 #define NFP_NET_CFG_MAX_MTU 0x0044 176 /* Next two words are being used by VFs for solving THB350 issue */ 177 #define NFP_NET_CFG_START_TXQ 0x0048 178 #define NFP_NET_CFG_START_RXQ 0x004c 179 180 /* 181 * NFP6000/NFP4000 - Prepend configuration 182 */ 183 #define NFP_NET_CFG_RX_OFFSET 0x0050 184 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 185 186 /* Start anchor of the TLV area */ 187 #define NFP_NET_CFG_TLV_BASE 0x0058 188 189 #define NFP_NET_CFG_VXLAN_PORT 0x0060 190 #define NFP_NET_CFG_VXLAN_SZ 0x0008 191 192 /* Offload definitions */ 193 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t)) 194 195 /* 196 * 3 words reserved for extended ctrl words (0x0098 - 0x00a4) 197 * 3 words reserved for extended cap words (0x00a4 - 0x00b0) 198 * Currently only one word is used, can be extended in future. 199 */ 200 #define NFP_NET_CFG_CTRL_WORD1 0x0098 201 #define NFP_NET_CFG_CTRL_PKT_TYPE (0x1 << 0) 202 #define NFP_NET_CFG_CTRL_IPSEC (0x1 << 1) /**< IPsec offload */ 203 #define NFP_NET_CFG_CTRL_MCAST_FILTER (0x1 << 2) /**< Multicast Filter */ 204 #define NFP_NET_CFG_CTRL_IPSEC_SM_LOOKUP (0x1 << 3) /**< SA short match lookup */ 205 #define NFP_NET_CFG_CTRL_IPSEC_LM_LOOKUP (0x1 << 4) /**< SA long match lookup */ 206 #define NFP_NET_CFG_CTRL_MULTI_PF (0x1 << 5) 207 #define NFP_NET_CFG_CTRL_FLOW_STEER (0x1 << 8) /**< Flow Steering */ 208 #define NFP_NET_CFG_CTRL_IN_ORDER (0x1 << 11) /**< Virtio in-order flag */ 209 #define NFP_NET_CFG_CTRL_USO (0x1 << 16) /**< UDP segmentation offload */ 210 211 #define NFP_NET_CFG_CAP_WORD1 0x00a4 212 213 /* 16B reserved for future use (0x00b0 - 0x00c0). */ 214 #define NFP_NET_CFG_RESERVED 0x00b0 215 #define NFP_NET_CFG_RESERVED_SZ 0x0010 216 217 /* 218 * RSS configuration (0x0100 - 0x01ac): 219 * Used only when NFP_NET_CFG_CTRL_RSS_ANY is enabled 220 * @NFP_NET_CFG_RSS_CFG: RSS configuration word 221 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key 222 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table 223 */ 224 #define NFP_NET_CFG_RSS_BASE 0x0100 225 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 226 #define NFP_NET_CFG_RSS_MASK (0x7f) 227 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 228 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 229 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 230 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 231 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 232 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 233 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 234 #define NFP_NET_CFG_RSS_IPV4_SCTP (1 << 14) /* RSS for IPv4/SCTP */ 235 #define NFP_NET_CFG_RSS_IPV6_SCTP (1 << 15) /* RSS for IPv6/SCTP */ 236 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 237 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 hash */ 238 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 239 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 240 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 241 NFP_NET_CFG_RSS_KEY_SZ) 242 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 243 244 /* 245 * TX ring configuration (0x200 - 0x800) 246 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 247 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 248 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 249 * @NFP_NET_CFG_TXR_SZ: Per TX ring size (1B entries) 250 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 251 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 252 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 253 */ 254 #define NFP_NET_CFG_TXR_BASE 0x0200 255 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 256 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 257 ((_x) * 0x8)) 258 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 259 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 260 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 261 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 262 ((_x) * 0x4)) 263 264 /* 265 * RX ring configuration (0x0800 - 0x0c00) 266 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 267 * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries) 268 * @NFP_NET_CFG_RXR_SZ: Per TX ring size (1B entries) 269 * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries) 270 * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries) 271 * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 272 */ 273 #define NFP_NET_CFG_RXR_BASE 0x0800 274 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 275 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 276 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 277 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 278 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 279 ((_x) * 0x4)) 280 281 /* 282 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 283 * These registers are only used when MSI-X auto-masking is not 284 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 285 * by MSI-X entry and are 1B in size. If an entry is zero, the 286 * corresponding entry is enabled. If the FW generates an interrupt, 287 * it writes a cause into the corresponding field. This also masks 288 * the MSI-X entry and the host driver must clear the register to 289 * re-enable the interrupt. 290 */ 291 #define NFP_NET_CFG_ICR_BASE 0x0c00 292 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 293 #define NFP_NET_CFG_ICR_UNMASKED 0x0 294 #define NFP_NET_CFG_ICR_RXTX 0x1 295 #define NFP_NET_CFG_ICR_LSC 0x2 296 297 /* 298 * General device stats (0x0d00 - 0x0d90) 299 * All counters are 64bit. 300 */ 301 #define NFP_NET_CFG_STATS_BASE 0x0d00 302 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 303 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 304 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 305 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 306 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 307 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 308 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 309 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 310 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 311 312 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 313 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 314 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 315 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 316 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 317 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 318 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 319 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 320 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 321 322 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 323 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 324 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 325 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 326 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 327 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 328 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 329 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 330 331 /* 332 * Per ring stats (0x1000 - 0x1800) 333 * Options, 64bit per entry 334 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 335 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 336 */ 337 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 338 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 339 ((_x) * 0x10)) 340 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 341 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 342 ((_x) * 0x10)) 343 344 #endif /* __NFP_COMMON_CTRL_H__ */ 345