1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2023 Corigine, Inc. 3 * All rights reserved. 4 */ 5 6 #ifndef __NFP_COMMON_CTRL_H__ 7 #define __NFP_COMMON_CTRL_H__ 8 9 /* 10 * Configuration BAR size. 11 * 12 * On the NFP6000, due to THB-350, the configuration BAR is 32K in size. 13 */ 14 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 15 16 /* Offset in Freelist buffer where packet starts on RX */ 17 #define NFP_NET_RX_OFFSET 32 18 19 /* Working with metadata api (NFD version > 3.0) */ 20 #define NFP_NET_META_FIELD_SIZE 4 21 #define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1) 22 #define NFP_NET_META_HEADER_SIZE 4 23 #define NFP_NET_META_NFDK_LENGTH 8 24 25 /* Working with metadata vlan api (NFD version >= 2.0) */ 26 #define NFP_NET_META_VLAN_INFO 16 27 #define NFP_NET_META_VLAN_OFFLOAD 31 28 #define NFP_NET_META_VLAN_TPID 3 29 #define NFP_NET_META_VLAN_MASK ((1 << NFP_NET_META_VLAN_INFO) - 1) 30 #define NFP_NET_META_VLAN_TPID_MASK ((1 << NFP_NET_META_VLAN_TPID) - 1) 31 #define NFP_NET_META_TPID(d) (((d) >> NFP_NET_META_VLAN_INFO) & \ 32 NFP_NET_META_VLAN_TPID_MASK) 33 34 /* Prepend field types */ 35 #define NFP_NET_META_HASH 1 /* Next field carries hash type */ 36 #define NFP_NET_META_MARK 2 37 #define NFP_NET_META_VLAN 4 38 #define NFP_NET_META_PORTID 5 39 #define NFP_NET_META_IPSEC 9 40 41 #define NFP_META_PORT_ID_CTRL ~0U 42 43 /* Hash type prepended when a RSS hash was computed */ 44 #define NFP_NET_RSS_NONE 0 45 #define NFP_NET_RSS_IPV4 1 46 #define NFP_NET_RSS_IPV6 2 47 #define NFP_NET_RSS_IPV6_EX 3 48 #define NFP_NET_RSS_IPV4_TCP 4 49 #define NFP_NET_RSS_IPV6_TCP 5 50 #define NFP_NET_RSS_IPV6_EX_TCP 6 51 #define NFP_NET_RSS_IPV4_UDP 7 52 #define NFP_NET_RSS_IPV6_UDP 8 53 #define NFP_NET_RSS_IPV6_EX_UDP 9 54 #define NFP_NET_RSS_IPV4_SCTP 10 55 #define NFP_NET_RSS_IPV6_SCTP 11 56 57 /* 58 * @NFP_NET_TXR_MAX: Maximum number of TX rings 59 * @NFP_NET_TXR_MASK: Mask for TX rings 60 * @NFP_NET_RXR_MAX: Maximum number of RX rings 61 * @NFP_NET_RXR_MASK: Mask for RX rings 62 */ 63 #define NFP_NET_TXR_MAX 64 64 #define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1) 65 #define NFP_NET_RXR_MAX 64 66 #define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1) 67 68 /* 69 * Read/Write config words (0x0000 - 0x002c) 70 * @NFP_NET_CFG_CTRL: Global control 71 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated 72 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 73 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 74 * @NFP_NET_CFG_MTU: Set MTU size 75 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 76 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions 77 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes 78 * @NFP_NET_CFG_MACADDR: MAC address 79 * 80 * TODO: 81 * - define Error details in UPDATE 82 */ 83 #define NFP_NET_CFG_CTRL 0x0000 84 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 85 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 86 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 87 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 88 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 89 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 90 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 91 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 92 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 93 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 94 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */ 95 #define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable QINQ strip */ 96 #define NFP_NET_CFG_CTRL_RXVLAN_V2 (0x1 << 15) /* Enable VLAN strip with metadata */ 97 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 98 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */ 99 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 100 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 101 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 102 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring */ 103 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 104 #define NFP_NET_CFG_CTRL_TXVLAN_V2 (0x1 << 23) /* Enable VLAN insert with metadata */ 105 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */ 106 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */ 107 #define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */ 108 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 109 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 110 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 111 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31) /* Live MAC addr change */ 112 #define NFP_NET_CFG_UPDATE 0x0004 113 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 114 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 115 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 116 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 117 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 118 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 119 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 120 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 121 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 122 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 123 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 124 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 125 #define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */ 126 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 127 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 128 #define NFP_NET_CFG_MTU 0x0018 129 #define NFP_NET_CFG_FLBUFSZ 0x001c 130 #define NFP_NET_CFG_EXN 0x001f 131 #define NFP_NET_CFG_LSC 0x0020 132 #define NFP_NET_CFG_MACADDR 0x0024 133 134 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2) 135 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | NFP_NET_CFG_CTRL_RSS2) 136 137 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 138 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 139 140 /* Version number helper defines */ 141 struct nfp_net_fw_ver { 142 uint8_t minor; 143 uint8_t major; 144 uint8_t class; 145 /** 146 * This byte can be extended for more use. 147 * BIT0: NFD dp type, refer NFP_NET_CFG_VERSION_DP_NFDx 148 * BIT[7:1]: reserved 149 */ 150 uint8_t extend; 151 }; 152 153 /* 154 * Read-only words (0x0030 - 0x0050): 155 * @NFP_NET_CFG_VERSION: Firmware version number 156 * @NFP_NET_CFG_STS: Status 157 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL) 158 * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings 159 * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings 160 * @NFP_NET_MAX_MTU: Maximum support MTU 161 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 162 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 163 * 164 * TODO: 165 * - define more STS bits 166 */ 167 #define NFP_NET_CFG_VERSION 0x0030 168 #define NFP_NET_CFG_VERSION_DP_NFD3 0 169 #define NFP_NET_CFG_VERSION_DP_NFDK 1 170 #define NFP_NET_CFG_STS 0x0034 171 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 172 /* Link rate */ 173 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 174 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 175 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 176 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 177 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 178 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 179 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 180 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 181 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 182 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 183 184 /* 185 * NSP Link rate is a 16-bit word. It is no longer determined by 186 * firmware, instead it is read from the nfp_eth_table of the 187 * associated pf_dev and written to the NFP_NET_CFG_STS_NSP_LINK_RATE 188 * address by the PMD each time the port is reconfigured. 189 */ 190 #define NFP_NET_CFG_STS_NSP_LINK_RATE 0x0036 191 192 #define NFP_NET_CFG_CAP 0x0038 193 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 194 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 195 #define NFP_NET_CFG_MAX_MTU 0x0044 196 /* Next two words are being used by VFs for solving THB350 issue */ 197 #define NFP_NET_CFG_START_TXQ 0x0048 198 #define NFP_NET_CFG_START_RXQ 0x004c 199 200 /* 201 * NFP6000/NFP4000 - Prepend configuration 202 */ 203 #define NFP_NET_CFG_RX_OFFSET 0x0050 204 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 205 206 /* Start anchor of the TLV area */ 207 #define NFP_NET_CFG_TLV_BASE 0x0058 208 209 #define NFP_NET_CFG_VXLAN_PORT 0x0060 210 #define NFP_NET_CFG_VXLAN_SZ 0x0008 211 212 /* Offload definitions */ 213 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t)) 214 215 /* 216 * 3 words reserved for extended ctrl words (0x0098 - 0x00a4) 217 * 3 words reserved for extended cap words (0x00a4 - 0x00b0) 218 * Currently only one word is used, can be extended in future. 219 */ 220 #define NFP_NET_CFG_CTRL_WORD1 0x0098 221 #define NFP_NET_CFG_CTRL_PKT_TYPE (0x1 << 0) 222 #define NFP_NET_CFG_CTRL_IPSEC (0x1 << 1) /**< IPsec offload */ 223 #define NFP_NET_CFG_CTRL_MCAST_FILTER (0x1 << 2) /**< Multicast Filter */ 224 #define NFP_NET_CFG_CTRL_IPSEC_SM_LOOKUP (0x1 << 3) /**< SA short match lookup */ 225 #define NFP_NET_CFG_CTRL_IPSEC_LM_LOOKUP (0x1 << 4) /**< SA long match lookup */ 226 #define NFP_NET_CFG_CTRL_MULTI_PF (0x1 << 5) 227 #define NFP_NET_CFG_CTRL_FLOW_STEER (0x1 << 8) /**< Flow Steering */ 228 #define NFP_NET_CFG_CTRL_IN_ORDER (0x1 << 11) /**< Virtio in-order flag */ 229 #define NFP_NET_CFG_CTRL_USO (0x1 << 16) /**< UDP segmentation offload */ 230 231 #define NFP_NET_CFG_CAP_WORD1 0x00a4 232 233 /* 16B reserved for future use (0x00b0 - 0x00c0). */ 234 #define NFP_NET_CFG_RESERVED 0x00b0 235 #define NFP_NET_CFG_RESERVED_SZ 0x0010 236 237 /* 238 * RSS configuration (0x0100 - 0x01ac): 239 * Used only when NFP_NET_CFG_CTRL_RSS_ANY is enabled 240 * @NFP_NET_CFG_RSS_CFG: RSS configuration word 241 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key 242 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table 243 */ 244 #define NFP_NET_CFG_RSS_BASE 0x0100 245 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 246 #define NFP_NET_CFG_RSS_MASK (0x7f) 247 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 248 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 249 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 250 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 251 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 252 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 253 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 254 #define NFP_NET_CFG_RSS_IPV4_SCTP (1 << 14) /* RSS for IPv4/SCTP */ 255 #define NFP_NET_CFG_RSS_IPV6_SCTP (1 << 15) /* RSS for IPv6/SCTP */ 256 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 257 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 hash */ 258 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 259 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 260 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 261 NFP_NET_CFG_RSS_KEY_SZ) 262 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 263 264 /* 265 * TX ring configuration (0x200 - 0x800) 266 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 267 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 268 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 269 * @NFP_NET_CFG_TXR_SZ: Per TX ring size (1B entries) 270 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 271 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 272 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 273 */ 274 #define NFP_NET_CFG_TXR_BASE 0x0200 275 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 276 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 277 ((_x) * 0x8)) 278 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 279 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 280 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 281 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 282 ((_x) * 0x4)) 283 284 /* 285 * RX ring configuration (0x0800 - 0x0c00) 286 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 287 * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries) 288 * @NFP_NET_CFG_RXR_SZ: Per TX ring size (1B entries) 289 * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries) 290 * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries) 291 * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 292 */ 293 #define NFP_NET_CFG_RXR_BASE 0x0800 294 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 295 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 296 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 297 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 298 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 299 ((_x) * 0x4)) 300 301 /* 302 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 303 * These registers are only used when MSI-X auto-masking is not 304 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 305 * by MSI-X entry and are 1B in size. If an entry is zero, the 306 * corresponding entry is enabled. If the FW generates an interrupt, 307 * it writes a cause into the corresponding field. This also masks 308 * the MSI-X entry and the host driver must clear the register to 309 * re-enable the interrupt. 310 */ 311 #define NFP_NET_CFG_ICR_BASE 0x0c00 312 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 313 #define NFP_NET_CFG_ICR_UNMASKED 0x0 314 #define NFP_NET_CFG_ICR_RXTX 0x1 315 #define NFP_NET_CFG_ICR_LSC 0x2 316 317 /* 318 * General device stats (0x0d00 - 0x0d90) 319 * All counters are 64bit. 320 */ 321 #define NFP_NET_CFG_STATS_BASE 0x0d00 322 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 323 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 324 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 325 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 326 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 327 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 328 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 329 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 330 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 331 332 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 333 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 334 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 335 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 336 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 337 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 338 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 339 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 340 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 341 342 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 343 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 344 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 345 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 346 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 347 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 348 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 349 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 350 351 /* 352 * Per ring stats (0x1000 - 0x1800) 353 * Options, 64bit per entry 354 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 355 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 356 */ 357 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 358 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 359 ((_x) * 0x10)) 360 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 361 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 362 ((_x) * 0x10)) 363 364 #endif /* __NFP_COMMON_CTRL_H__ */ 365