1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2023 Corigine, Inc. 3 * All rights reserved. 4 */ 5 6 #ifndef __NFP_COMMON_CTRL_H__ 7 #define __NFP_COMMON_CTRL_H__ 8 9 /* 10 * Configuration BAR size. 11 * 12 * On the NFP6000, due to THB-350, the configuration BAR is 32K in size. 13 */ 14 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 15 16 /* Offset in Freelist buffer where packet starts on RX */ 17 #define NFP_NET_RX_OFFSET 32 18 19 /* Working with metadata api (NFD version > 3.0) */ 20 #define NFP_NET_META_FIELD_SIZE 4 21 #define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1) 22 #define NFP_NET_META_HEADER_SIZE 4 23 #define NFP_NET_META_NFDK_LENGTH 8 24 25 /* Working with metadata vlan api (NFD version >= 2.0) */ 26 #define NFP_NET_META_VLAN_INFO 16 27 #define NFP_NET_META_VLAN_OFFLOAD 31 28 #define NFP_NET_META_VLAN_TPID 3 29 #define NFP_NET_META_VLAN_MASK ((1 << NFP_NET_META_VLAN_INFO) - 1) 30 #define NFP_NET_META_VLAN_TPID_MASK ((1 << NFP_NET_META_VLAN_TPID) - 1) 31 #define NFP_NET_META_TPID(d) (((d) >> NFP_NET_META_VLAN_INFO) & \ 32 NFP_NET_META_VLAN_TPID_MASK) 33 34 /* Prepend field types */ 35 #define NFP_NET_META_HASH 1 /* Next field carries hash type */ 36 #define NFP_NET_META_VLAN 4 37 #define NFP_NET_META_PORTID 5 38 #define NFP_NET_META_IPSEC 9 39 40 #define NFP_META_PORT_ID_CTRL ~0U 41 42 /* Hash type prepended when a RSS hash was computed */ 43 #define NFP_NET_RSS_NONE 0 44 #define NFP_NET_RSS_IPV4 1 45 #define NFP_NET_RSS_IPV6 2 46 #define NFP_NET_RSS_IPV6_EX 3 47 #define NFP_NET_RSS_IPV4_TCP 4 48 #define NFP_NET_RSS_IPV6_TCP 5 49 #define NFP_NET_RSS_IPV6_EX_TCP 6 50 #define NFP_NET_RSS_IPV4_UDP 7 51 #define NFP_NET_RSS_IPV6_UDP 8 52 #define NFP_NET_RSS_IPV6_EX_UDP 9 53 #define NFP_NET_RSS_IPV4_SCTP 10 54 #define NFP_NET_RSS_IPV6_SCTP 11 55 56 /* 57 * @NFP_NET_TXR_MAX: Maximum number of TX rings 58 * @NFP_NET_TXR_MASK: Mask for TX rings 59 * @NFP_NET_RXR_MAX: Maximum number of RX rings 60 * @NFP_NET_RXR_MASK: Mask for RX rings 61 */ 62 #define NFP_NET_TXR_MAX 64 63 #define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1) 64 #define NFP_NET_RXR_MAX 64 65 #define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1) 66 67 /* 68 * Read/Write config words (0x0000 - 0x002c) 69 * @NFP_NET_CFG_CTRL: Global control 70 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated 71 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 72 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 73 * @NFP_NET_CFG_MTU: Set MTU size 74 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 75 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions 76 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes 77 * @NFP_NET_CFG_MACADDR: MAC address 78 * 79 * TODO: 80 * - define Error details in UPDATE 81 */ 82 #define NFP_NET_CFG_CTRL 0x0000 83 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 84 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 85 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 86 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 87 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 88 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 89 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 90 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 91 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 92 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 93 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */ 94 #define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable QINQ strip */ 95 #define NFP_NET_CFG_CTRL_RXVLAN_V2 (0x1 << 15) /* Enable VLAN strip with metadata */ 96 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 97 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */ 98 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 99 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 100 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 101 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring */ 102 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 103 #define NFP_NET_CFG_CTRL_TXVLAN_V2 (0x1 << 23) /* Enable VLAN insert with metadata */ 104 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */ 105 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */ 106 #define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */ 107 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 108 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 109 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 110 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31) /* Live MAC addr change */ 111 #define NFP_NET_CFG_UPDATE 0x0004 112 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 113 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 114 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 115 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 116 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 117 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 118 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 119 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 120 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 121 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 122 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 123 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 124 #define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */ 125 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 126 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 127 #define NFP_NET_CFG_MTU 0x0018 128 #define NFP_NET_CFG_FLBUFSZ 0x001c 129 #define NFP_NET_CFG_EXN 0x001f 130 #define NFP_NET_CFG_LSC 0x0020 131 #define NFP_NET_CFG_MACADDR 0x0024 132 133 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2) 134 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | NFP_NET_CFG_CTRL_RSS2) 135 136 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 137 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 138 139 /* Version number helper defines */ 140 struct nfp_net_fw_ver { 141 uint8_t minor; 142 uint8_t major; 143 uint8_t class; 144 /** 145 * This byte can be extended for more use. 146 * BIT0: NFD dp type, refer NFP_NET_CFG_VERSION_DP_NFDx 147 * BIT[7:1]: reserved 148 */ 149 uint8_t extend; 150 }; 151 152 /* 153 * Read-only words (0x0030 - 0x0050): 154 * @NFP_NET_CFG_VERSION: Firmware version number 155 * @NFP_NET_CFG_STS: Status 156 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL) 157 * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings 158 * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings 159 * @NFP_NET_MAX_MTU: Maximum support MTU 160 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 161 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 162 * 163 * TODO: 164 * - define more STS bits 165 */ 166 #define NFP_NET_CFG_VERSION 0x0030 167 #define NFP_NET_CFG_VERSION_DP_NFD3 0 168 #define NFP_NET_CFG_VERSION_DP_NFDK 1 169 #define NFP_NET_CFG_STS 0x0034 170 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 171 /* Link rate */ 172 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 173 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 174 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 175 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 176 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 177 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 178 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 179 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 180 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 181 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 182 183 /* 184 * NSP Link rate is a 16-bit word. It is no longer determined by 185 * firmware, instead it is read from the nfp_eth_table of the 186 * associated pf_dev and written to the NFP_NET_CFG_STS_NSP_LINK_RATE 187 * address by the PMD each time the port is reconfigured. 188 */ 189 #define NFP_NET_CFG_STS_NSP_LINK_RATE 0x0036 190 191 #define NFP_NET_CFG_CAP 0x0038 192 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 193 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 194 #define NFP_NET_CFG_MAX_MTU 0x0044 195 /* Next two words are being used by VFs for solving THB350 issue */ 196 #define NFP_NET_CFG_START_TXQ 0x0048 197 #define NFP_NET_CFG_START_RXQ 0x004c 198 199 /* 200 * NFP6000/NFP4000 - Prepend configuration 201 */ 202 #define NFP_NET_CFG_RX_OFFSET 0x0050 203 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 204 205 /* Start anchor of the TLV area */ 206 #define NFP_NET_CFG_TLV_BASE 0x0058 207 208 #define NFP_NET_CFG_VXLAN_PORT 0x0060 209 #define NFP_NET_CFG_VXLAN_SZ 0x0008 210 211 /* Offload definitions */ 212 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t)) 213 214 /* 215 * 3 words reserved for extended ctrl words (0x0098 - 0x00a4) 216 * 3 words reserved for extended cap words (0x00a4 - 0x00b0) 217 * Currently only one word is used, can be extended in future. 218 */ 219 #define NFP_NET_CFG_CTRL_WORD1 0x0098 220 #define NFP_NET_CFG_CTRL_PKT_TYPE (0x1 << 0) 221 #define NFP_NET_CFG_CTRL_IPSEC (0x1 << 1) /**< IPsec offload */ 222 #define NFP_NET_CFG_CTRL_MCAST_FILTER (0x1 << 2) /**< Multicast Filter */ 223 #define NFP_NET_CFG_CTRL_IPSEC_SM_LOOKUP (0x1 << 3) /**< SA short match lookup */ 224 #define NFP_NET_CFG_CTRL_IPSEC_LM_LOOKUP (0x1 << 4) /**< SA long match lookup */ 225 #define NFP_NET_CFG_CTRL_MULTI_PF (0x1 << 5) 226 #define NFP_NET_CFG_CTRL_IN_ORDER (0x1 << 11) /**< Virtio in-order flag */ 227 228 #define NFP_NET_CFG_CAP_WORD1 0x00a4 229 230 /* 16B reserved for future use (0x00b0 - 0x00c0). */ 231 #define NFP_NET_CFG_RESERVED 0x00b0 232 #define NFP_NET_CFG_RESERVED_SZ 0x0010 233 234 /* 235 * RSS configuration (0x0100 - 0x01ac): 236 * Used only when NFP_NET_CFG_CTRL_RSS_ANY is enabled 237 * @NFP_NET_CFG_RSS_CFG: RSS configuration word 238 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key 239 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table 240 */ 241 #define NFP_NET_CFG_RSS_BASE 0x0100 242 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 243 #define NFP_NET_CFG_RSS_MASK (0x7f) 244 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 245 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 246 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 247 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 248 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 249 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 250 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 251 #define NFP_NET_CFG_RSS_IPV4_SCTP (1 << 14) /* RSS for IPv4/SCTP */ 252 #define NFP_NET_CFG_RSS_IPV6_SCTP (1 << 15) /* RSS for IPv6/SCTP */ 253 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 254 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 255 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 256 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 257 NFP_NET_CFG_RSS_KEY_SZ) 258 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 259 260 /* 261 * TX ring configuration (0x200 - 0x800) 262 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 263 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 264 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 265 * @NFP_NET_CFG_TXR_SZ: Per TX ring size (1B entries) 266 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 267 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 268 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 269 */ 270 #define NFP_NET_CFG_TXR_BASE 0x0200 271 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 272 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 273 ((_x) * 0x8)) 274 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 275 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 276 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 277 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 278 ((_x) * 0x4)) 279 280 /* 281 * RX ring configuration (0x0800 - 0x0c00) 282 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 283 * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries) 284 * @NFP_NET_CFG_RXR_SZ: Per TX ring size (1B entries) 285 * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries) 286 * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries) 287 * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 288 */ 289 #define NFP_NET_CFG_RXR_BASE 0x0800 290 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 291 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 292 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 293 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 294 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 295 ((_x) * 0x4)) 296 297 /* 298 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 299 * These registers are only used when MSI-X auto-masking is not 300 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 301 * by MSI-X entry and are 1B in size. If an entry is zero, the 302 * corresponding entry is enabled. If the FW generates an interrupt, 303 * it writes a cause into the corresponding field. This also masks 304 * the MSI-X entry and the host driver must clear the register to 305 * re-enable the interrupt. 306 */ 307 #define NFP_NET_CFG_ICR_BASE 0x0c00 308 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 309 #define NFP_NET_CFG_ICR_UNMASKED 0x0 310 #define NFP_NET_CFG_ICR_RXTX 0x1 311 #define NFP_NET_CFG_ICR_LSC 0x2 312 313 /* 314 * General device stats (0x0d00 - 0x0d90) 315 * All counters are 64bit. 316 */ 317 #define NFP_NET_CFG_STATS_BASE 0x0d00 318 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 319 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 320 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 321 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 322 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 323 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 324 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 325 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 326 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 327 328 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 329 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 330 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 331 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 332 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 333 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 334 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 335 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 336 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 337 338 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 339 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 340 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 341 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 342 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 343 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 344 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 345 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 346 347 /* 348 * Per ring stats (0x1000 - 0x1800) 349 * Options, 64bit per entry 350 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 351 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 352 */ 353 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 354 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 355 ((_x) * 0x10)) 356 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 357 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 358 ((_x) * 0x10)) 359 360 #endif /* __NFP_COMMON_CTRL_H__ */ 361