1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2023 Corigine, Inc. 3 * All rights reserved. 4 */ 5 6 #ifndef __NFP_COMMON_H__ 7 #define __NFP_COMMON_H__ 8 9 #include <rte_byteorder.h> 10 #include <rte_ether.h> 11 #include <rte_io.h> 12 #include <rte_spinlock.h> 13 14 #include "nfp_common_ctrl.h" 15 16 #define NFP_QCP_QUEUE_ADDR_SZ (0x800) 17 18 /* Macros for accessing the Queue Controller Peripheral 'CSRs' */ 19 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800) 20 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000 21 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004 22 #define NFP_QCP_QUEUE_STS_LO 0x0008 23 #define NFP_QCP_QUEUE_STS_LO_READPTR_MASK (0x3ffff) 24 #define NFP_QCP_QUEUE_STS_HI 0x000c 25 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK (0x3ffff) 26 27 /* Read or Write Pointer of a queue */ 28 enum nfp_qcp_ptr { 29 NFP_QCP_READ_PTR = 0, 30 NFP_QCP_WRITE_PTR 31 }; 32 33 struct nfp_hw { 34 uint8_t *ctrl_bar; 35 uint8_t *qcp_cfg; 36 uint32_t cap; 37 uint32_t cap_ext; 38 uint32_t ctrl; 39 uint32_t ctrl_ext; 40 rte_spinlock_t reconfig_lock; 41 struct rte_ether_addr mac_addr; 42 }; 43 44 static inline uint8_t 45 nn_readb(volatile const void *addr) 46 { 47 return rte_read8(addr); 48 } 49 50 static inline void 51 nn_writeb(uint8_t val, 52 volatile void *addr) 53 { 54 rte_write8(val, addr); 55 } 56 57 static inline uint32_t 58 nn_readl(volatile const void *addr) 59 { 60 return rte_read32(addr); 61 } 62 63 static inline void 64 nn_writel(uint32_t val, 65 volatile void *addr) 66 { 67 rte_write32(val, addr); 68 } 69 70 static inline uint16_t 71 nn_readw(volatile const void *addr) 72 { 73 return rte_read16(addr); 74 } 75 76 static inline void 77 nn_writew(uint16_t val, 78 volatile void *addr) 79 { 80 rte_write16(val, addr); 81 } 82 83 static inline uint64_t 84 nn_readq(volatile void *addr) 85 { 86 uint32_t low; 87 uint32_t high; 88 const volatile uint32_t *p = addr; 89 90 high = nn_readl((volatile const void *)(p + 1)); 91 low = nn_readl((volatile const void *)p); 92 93 return low + ((uint64_t)high << 32); 94 } 95 96 static inline void 97 nn_writeq(uint64_t val, 98 volatile void *addr) 99 { 100 nn_writel(val >> 32, (volatile char *)addr + 4); 101 nn_writel(val, addr); 102 } 103 104 static inline uint8_t 105 nn_cfg_readb(struct nfp_hw *hw, 106 uint32_t off) 107 { 108 return nn_readb(hw->ctrl_bar + off); 109 } 110 111 static inline void 112 nn_cfg_writeb(struct nfp_hw *hw, 113 uint32_t off, 114 uint8_t val) 115 { 116 nn_writeb(val, hw->ctrl_bar + off); 117 } 118 119 static inline uint16_t 120 nn_cfg_readw(struct nfp_hw *hw, 121 uint32_t off) 122 { 123 return rte_le_to_cpu_16(nn_readw(hw->ctrl_bar + off)); 124 } 125 126 static inline void 127 nn_cfg_writew(struct nfp_hw *hw, 128 uint32_t off, 129 uint16_t val) 130 { 131 nn_writew(rte_cpu_to_le_16(val), hw->ctrl_bar + off); 132 } 133 134 static inline uint32_t 135 nn_cfg_readl(struct nfp_hw *hw, 136 uint32_t off) 137 { 138 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off)); 139 } 140 141 static inline void 142 nn_cfg_writel(struct nfp_hw *hw, 143 uint32_t off, 144 uint32_t val) 145 { 146 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off); 147 } 148 149 static inline uint64_t 150 nn_cfg_readq(struct nfp_hw *hw, 151 uint32_t off) 152 { 153 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off)); 154 } 155 156 static inline void 157 nn_cfg_writeq(struct nfp_hw *hw, 158 uint32_t off, 159 uint64_t val) 160 { 161 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off); 162 } 163 164 /** 165 * Add the value to the selected pointer of a queue. 166 * 167 * @param queue 168 * Base address for queue structure 169 * @param ptr 170 * Add to the read or write pointer 171 * @param val 172 * Value to add to the queue pointer 173 */ 174 static inline void 175 nfp_qcp_ptr_add(uint8_t *queue, 176 enum nfp_qcp_ptr ptr, 177 uint32_t val) 178 { 179 uint32_t off; 180 181 if (ptr == NFP_QCP_READ_PTR) 182 off = NFP_QCP_QUEUE_ADD_RPTR; 183 else 184 off = NFP_QCP_QUEUE_ADD_WPTR; 185 186 nn_writel(rte_cpu_to_le_32(val), queue + off); 187 } 188 189 /** 190 * Read the current read/write pointer value for a queue. 191 * 192 * @param queue 193 * Base address for queue structure 194 * @param ptr 195 * Read or Write pointer 196 */ 197 static inline uint32_t 198 nfp_qcp_read(uint8_t *queue, 199 enum nfp_qcp_ptr ptr) 200 { 201 uint32_t off; 202 uint32_t val; 203 204 if (ptr == NFP_QCP_READ_PTR) 205 off = NFP_QCP_QUEUE_STS_LO; 206 else 207 off = NFP_QCP_QUEUE_STS_HI; 208 209 val = rte_cpu_to_le_32(nn_readl(queue + off)); 210 211 if (ptr == NFP_QCP_READ_PTR) 212 return val & NFP_QCP_QUEUE_STS_LO_READPTR_MASK; 213 else 214 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK; 215 } 216 217 __rte_internal 218 int nfp_reconfig_real(struct nfp_hw *hw, uint32_t update); 219 220 __rte_internal 221 int nfp_reconfig(struct nfp_hw *hw, uint32_t ctrl, uint32_t update); 222 223 __rte_internal 224 int nfp_ext_reconfig(struct nfp_hw *hw, uint32_t ctrl_ext, uint32_t update); 225 226 __rte_internal 227 void nfp_read_mac(struct nfp_hw *hw); 228 229 __rte_internal 230 void nfp_write_mac(struct nfp_hw *hw, uint8_t *mac); 231 232 __rte_internal 233 void nfp_enable_queues(struct nfp_hw *hw, uint16_t nb_rx_queues, 234 uint16_t nb_tx_queues); 235 236 __rte_internal 237 void nfp_disable_queues(struct nfp_hw *hw); 238 239 #endif/* __NFP_COMMON_H__ */ 240