1*7a39d1b0SLiron Himi /* SPDX-License-Identifier: BSD-3-Clause 2*7a39d1b0SLiron Himi * Copyright(c) 2018 Marvell International Ltd. 3*7a39d1b0SLiron Himi */ 4*7a39d1b0SLiron Himi 5*7a39d1b0SLiron Himi #include <rte_common.h> 6*7a39d1b0SLiron Himi 7*7a39d1b0SLiron Himi #include <env/mv_autogen_comp_flags.h> 8*7a39d1b0SLiron Himi #include <env/mv_sys_dma.h> 9*7a39d1b0SLiron Himi 10*7a39d1b0SLiron Himi #include "rte_mvep_common.h" 11*7a39d1b0SLiron Himi 12*7a39d1b0SLiron Himi /* Memory size (in bytes) for MUSDK dma buffers */ 13*7a39d1b0SLiron Himi #define MRVL_MUSDK_DMA_MEMSIZE (40 * 1024 * 1024) 14*7a39d1b0SLiron Himi 15*7a39d1b0SLiron Himi struct mvep { 16*7a39d1b0SLiron Himi uint32_t ref_count; 17*7a39d1b0SLiron Himi }; 18*7a39d1b0SLiron Himi 19*7a39d1b0SLiron Himi static struct mvep mvep; 20*7a39d1b0SLiron Himi rte_mvep_init(enum mvep_module_type module __rte_unused,struct rte_kvargs * kvlist __rte_unused)21*7a39d1b0SLiron Himiint rte_mvep_init(enum mvep_module_type module __rte_unused, 22*7a39d1b0SLiron Himi struct rte_kvargs *kvlist __rte_unused) 23*7a39d1b0SLiron Himi { 24*7a39d1b0SLiron Himi int ret; 25*7a39d1b0SLiron Himi 26*7a39d1b0SLiron Himi if (!mvep.ref_count) { 27*7a39d1b0SLiron Himi ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE); 28*7a39d1b0SLiron Himi if (ret) 29*7a39d1b0SLiron Himi return ret; 30*7a39d1b0SLiron Himi } 31*7a39d1b0SLiron Himi 32*7a39d1b0SLiron Himi mvep.ref_count++; 33*7a39d1b0SLiron Himi 34*7a39d1b0SLiron Himi return 0; 35*7a39d1b0SLiron Himi } 36*7a39d1b0SLiron Himi rte_mvep_deinit(enum mvep_module_type module __rte_unused)37*7a39d1b0SLiron Himiint rte_mvep_deinit(enum mvep_module_type module __rte_unused) 38*7a39d1b0SLiron Himi { 39*7a39d1b0SLiron Himi mvep.ref_count--; 40*7a39d1b0SLiron Himi 41*7a39d1b0SLiron Himi if (!mvep.ref_count) 42*7a39d1b0SLiron Himi mv_sys_dma_mem_destroy(); 43*7a39d1b0SLiron Himi 44*7a39d1b0SLiron Himi return 0; 45*7a39d1b0SLiron Himi } 46